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The document following this cover page is marked as “Cypress” document as this is the
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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
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CY7C1355C
CY7C1357C
9-Mbit (256K × 36/512K × 18)
Flow-Through SRAM
with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
The CY7C1355C/CY7C1357C is a 3.3 V, 256K × 36/512K × 18
synchronous flow-through burst SRAM designed specifically to
support unlimited true back-to-back read/write operations
without
the
insertion
of
wait
states.
The
CY7C1355C/CY7C1357C is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
write-read transitions.
■
Can support up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow-through operation
■
Byte write capability
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock enable (CEN) pin to enable clock and suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Available in JEDEC-standard and Pb-free 100-pin TQFP and
165-ball FBGA package
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
■
Three chip enables for simple depth expansion.
For a complete list of related documentation, click here.
■
Automatic power-down feature available using ZZ mode or CE
deselect
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability – linear or interleaved burst order
■
Low standby power
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum access time
6.5
7.5
ns
Maximum operating current
250
180
mA
Maximum CMOS standby current
40
40
mA
Cypress Semiconductor Corporation
Document Number: 38-05539 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 9, 2018
CY7C1355C
CY7C1357C
Logic Block Diagram – CY7C1355C
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
BWC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWD
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05539 Rev. *N
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 33
CY7C1355C
CY7C1357C
Logic Block Diagram – CY7C1357C
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05539 Rev. *N
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 3 of 33
CY7C1355C
CY7C1357C
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
Document Number: 38-05539 Rev. *N
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 4 of 33
CY7C1355C
CY7C1357C
Pin Configurations
A
81
A
82
A
83
84
NC/18M
ADV/LD
85
OE
86
CEN
90
87
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
BWC
96
BWB
BWD
97
95
CE2
98
A
CE1
42
43
44
45
46
47
48
49
50
NC/36M
A
A
A
A
A
A
A
41
NC/72M
40
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
Document Number: 38-05539 Rev. *N
NC/288M
31
A
BYTE D
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
Vss/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (CY7C1355C)
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 5 of 33
CY7C1355C
CY7C1357C
Pin Configurations (continued)
A
81
A
82
A
83
84
NC/18M
ADV/LD
85
OE
86
CEN
90
87
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
NC
BWB
95
NC
97
96
CE2
98
A
CE1
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
VDD
37
A0
40
36
A1
VSS
35
A
39
34
A
NC/144M
33
A
38
32
A
Document Number: 38-05539 Rev. *N
NC/288M
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
Vss/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (CY7C1357C)
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 6 of 33
CY7C1355C
CY7C1357C
Pin Configurations (continued)
Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enables with JTAG)
CY7C1357C (512K × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWB
NC
CE3
CEN
ADV/LD
A
A
A
NC/1G
A
CE2
NC
BWA
CLK
WE
OE
NC/18M
A
NC
NC
NC
NC
DQB
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
NC
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
NC
DQB
DQB
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
NC
NC
DQA
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC/144M NC/72M
A
A
R
MODE
NC/36M
A
A
DQB
NC
NC
Document Number: 38-05539 Rev. *N
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
TDI
NC
A1
TDO
A
A
A
NC/288M
TMS
A0
TCK
A
A
A
A
Page 7 of 33
CY7C1355C
CY7C1357C
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous A[1:0] are fed to the two-bit burst counter.
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2,
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input strap pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
VSS
TDO
I/O power
supply
Ground
Power supply for the I/O circuitry.
Ground for the device.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
output
not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.
synchronous
Document Number: 38-05539 Rev. *N
Page 8 of 33
CY7C1355C
CY7C1357C
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available
input
synchronous on TQFP packages.
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TCK
JTAG
clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 18-Mbit, 36-Mbit, 72-Mbit, 144-Mbit, 288-Mbit,
576-Mbit and 1-Gbit are address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU This pin can be connected to Ground or should be left floating.
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states during
write-read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. Maximum access delay from the clock rise (tCDV) is
6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 7.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output will be tri-stated immediately.
Document Number: 38-05539 Rev. *N
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Accesses section
above. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1355C/CY7C1357C provides byte write
capability that is described in the Truth Table. Asserting the write
enable input (WE) with the selected byte write select input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the Write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1355C/CY7C1357C is a common I/O device,
data should not be driven into the device while the outputs are
Page 9 of 33
CY7C1355C
CY7C1357C
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQPX inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs and
DQPX are automatically tri-stated during the data portion of a
write cycle, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BWX
inputs must be driven in each cycle of the burst write, in order to
write the correct bytes of data.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ inactive to exit sleep current
Document Number: 38-05539 Rev. *N
Min
Max
Unit
–
50
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 10 of 33
CY7C1355C
CY7C1357C
Truth Table
The Truth Table for parts CY7C1355C/CY7C1357C is as follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-state
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-state
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-state
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-state
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
WRITE cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-state
WRITE ABORT (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-state
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle (begin burst)
READ cycle (continue burst)
NOP/DUMMY READ (begin burst)
DUMMY READ (continue burst)
WRITE cycle (begin burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Partial Truth Table for Read/Write
The Partial Truth Table for read or write for parts CY7C1355C is as follows. [1, 2, 8]
WE
BWA
BWB
BWC
BWD
Read
Function (CY7C1355C)
H
X
X
X
X
Write no bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all bytes
L
L
L
L
L
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects
are asserted, see Truth Table for details.
2. Write is defined by BWX, and WE. See Truth Table for read/write.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05539 Rev. *N
Page 11 of 33
CY7C1355C
CY7C1357C
Partial Truth Table for Read/Write
The Partial Truth Table for read or write for parts CY7C1357C is as follows. [9, 10, 11]
Function (CY7C1357C)
WE
BWA
BWB
Read
H
X
X
Write - no bytes written
L
H
H
Write byte A – (DQA and DQPA)
L
H
H
Write byte B – (DQB and DQPB)
L
H
H
Write all bytes
L
L
L
Notes
9. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects
are asserted, see Truth Table for details.
10. Write is defined by BWX, and WE. See Truth Table for read/write.
11. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05539 Rev. *N
Page 12 of 33
CY7C1355C
CY7C1357C
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1357C incorporates a serial boundary scan test
access port (TAP) in the BGA package only. The TQFP package
does not offer this functionality. This part operates in accordance
with IEEE Standard 1149.1-1900, but doesn’t have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note the TAP controller functions in a manner that does not
conflict with the operation of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC-standard 3.3 V
or 2.5 V I/O logic levels.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
The CY7C1357C contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Disabling the JTAG Feature
Instruction Register
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Test Access Port (TAP)
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Clock (TCK)
Bypass Register
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Document Number: 38-05539 Rev. *N
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 20 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Page 13 of 33
CY7C1355C
CY7C1357C
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
Document Number: 38-05539 Rev. *N
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 33
CY7C1355C
CY7C1357C
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
Document Number: 38-05539 Rev. *N
Page 15 of 33
CY7C1355C
CY7C1357C
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
. 2 1 0
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05539 Rev. *N
UNDEFINED
Page 16 of 33
CY7C1355C
CY7C1357C
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Set-up Times
Hold Times
Notes
12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 38-05539 Rev. *N
Page 17 of 33
CY7C1355C
CY7C1357C
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [14]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
IOH = –1.0 mA, VDDQ = 2.5 V
2.4
–
V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 8.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Input HIGH voltage
Input LOW voltage
Input load current
GND < VIN < VDDQ
Note
14. All voltages referenced to VSS (GND).
Document Number: 38-05539 Rev. *N
Page 18 of 33
CY7C1355C
CY7C1357C
Identification Register Definitions
CY7C1357C
(512K × 18)
Instruction Field
Revision number (31:29)
010
Description
Describes the version number
Device depth (28:24)
01010
Reserved for Internal Use
Device width (23:18)
001001
Defines memory type and architecture
Cypress device ID (17:12)
010110
Defines width and density
Cypress JEDEC ID code (11:1)
00000110100
ID register presence indicator (0)
1
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 18)
Instruction
3
Bypass
1
ID
32
Boundary scan order (165-ball FBGA package)
69
Identification Codes
Code
Description
EXTEST
Instruction
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 38-05539 Rev. *N
Page 19 of 33
CY7C1355C
CY7C1357C
Boundary Scan Order
165-ball FBGA
CY7C1357C (512K × 18)
Bit#
ball ID
Signal Name
Bit#
ball ID
Signal Name
1
B6
CLK
37
R4
A
2
B7
WE
38
P4
A
3
A7
CEN
39
R3
A
4
B8
OE
40
P3
A
5
A8
ADV/LD
41
R1
MODE
6
A9
A
42
Internal
Internal
7
B10
A
43
Internal
Internal
8
A10
A
44
Internal
Internal
9
A11
A
45
Internal
Internal
10
Internal
Internal
46
N1
DQPB
11
Internal
Internal
47
M1
DQB
12
Internal
Internal
48
L1
DQB
13
C11
DQPA
49
K1
DQB
14
D11
DQA
50
J1
DQB
15
E11
DQA
51
Internal
Internal
16
F11
DQA
52
G2
DQB
17
G11
DQA
53
F2
DQB
18
H11
ZZ
54
E2
DQB
19
J10
DQA
55
D2
DQB
20
K10
DQA
56
Internal
Internal
21
L10
DQA
57
Internal
Internal
22
M10
DQA
58
Internal
Internal
23
Internal
Internal
59
Internal
Internal
24
Internal
Internal
60
Internal
Internal
25
Internal
Internal
61
B2
A
26
Internal
Internal
62
A2
A
27
Internal
Internal
63
A3
CE1
28
R11
A
64
B3
CE2
29
R10
A
65
Internal
Internal
30
P10
A
66
Internal
Internal
31
R9
A
67
A4
BWB
32
P9
A
68
B5
BWA
33
R8
A
69
A6
CE3
34
P8
A
35
R6
A0
36
P6
A1
Document Number: 38-05539 Rev. *N
Page 20 of 33
CY7C1355C
CY7C1357C
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
Ambient
Temperature
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V
2.5 V – 5% to
– 5% / + 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [15, 16]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH
voltage[15]
Test Conditions
Min
Max
Unit
3.135
3.6
V
For 3.3 V I/O
3.135
VDD
V
For 2.5 V I/O
2.375
2.625
V
For 3.3 V I/O, IOH =4.0 mA
2.4
–
V
For 2.5 V I/O, IOH =1.0 mA
2.0
–
V
For 3.3 V I/O, IOL=8.0 mA
–
0.4
V
For 2.5 V I/O, IOL= 1.0 mA
–
0.4
V
For 3.3 V I/O
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 3.3 V I/O
–0.3
0.8
V
For 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
µA
Input current of MODE
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
Input LOW
voltage[15]
Input current of ZZ
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
5
µA
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
–
250
mA
10-ns cycle,
100 MHz
–
180
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX, inputs switching
All speeds
–
110
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDD – 0.3 V,
f = 0, inputs static
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = fMAX, inputs switching
–
100
mA
Notes
15. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
16. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05539 Rev. *N
Page 21 of 33
CY7C1355C
CY7C1357C
Electrical Characteristics (continued)
Over the Operating Range
Parameter [15, 16]
ISB4
Description
Test Conditions
Automatic CE power-down
current – TTL Inputs
All speeds
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = 0, inputs static
Min
Max
Unit
–
40
mA
Capacitance
Parameter [17]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
pF
5
5
pF
5
7
pF
Thermal Resistance
Parameter [17]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
29.41
16.8
C/W
6.31
3.0
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50
Z0 = 50
VT = 1.25 V
(a)
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
1 ns
(b)
GND
5 pF
90%
10%
90%
1 ns
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
R = 1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
17. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05539 Rev. *N
Page 22 of 33
CY7C1355C
CY7C1357C
Switching Characteristics
Over the Operating Range
Parameter [18, 19]
tPOWER
Description
VDD(typical) to the first access [20]
-133
-100
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
3.0
–
4.0
–
ns
tCL
Clock LOW
3.0
–
4.0
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
7.5
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
0
–
0
–
ns
–
3.5
–
3.5
ns
–
3.5
–
3.5
ns
0
–
0
–
ns
–
3.5
–
3.5
ns
[21, 22, 23]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [21, 22, 23]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[21, 22, 23]
OE HIGH to output high Z
[21, 22, 23]
Set-up Times
tAS
Address set-up before CLK rise
1.5
–
1.5
–
ns
tALS
ADV/LD set-up before CLK rise
1.5
–
1.5
–
ns
tWES
WE, BWX set-up before CLK rise
1.5
–
1.5
–
ns
tCENS
CEN set-up before CLK rise
1.5
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.5
–
1.5
–
ns
tCES
Chip enable set-up before CLK rise
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
18. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
19. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
20. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage.
22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 38-05539 Rev. *N
Page 23 of 33
CY7C1355C
CY7C1357C
Switching Waveforms
Figure 5. Read/Write Waveforms [24, 25, 26]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05539 Rev. *N
Page 24 of 33
CY7C1355C
CY7C1357C
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [27, 28, 29]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
27. For this waveform ZZ is tied LOW.
28. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
29. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05539 Rev. *N
Page 25 of 33
CY7C1355C
CY7C1357C
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05539 Rev. *N
Page 26 of 33
CY7C1355C
CY7C1357C
Ordering Information
The following table contains only the list of parts that are currently available. If you do not see what you are looking for, contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1355C-133AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Commercial
CY7C1357C-133AXC
100
CY7C1357C-100BZC
Ordering Code Definitions
CY 7
C 135X
C - XXX XX X C
Temperature Range: C = Commercial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 133 MHz or 100 MHz
Process Technology: C 90nm
Part Identifier: 135X = 1355 or 1357
1355 = FT, 256Kb × 36 (9Mb)
1357 = FT, 512Kb × 18 (9Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05539 Rev. *N
Page 27 of 33
CY7C1355C
CY7C1357C
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05539 Rev. *N
Page 28 of 33
CY7C1355C
CY7C1357C
Package Diagrams (continued)
Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05539 Rev. *N
Page 29 of 33
CY7C1355C
CY7C1357C
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
ball grid array
CE
chip enable
°C
degree Celsius
CEN
clock enable
MHz
megahertz
FPBGA
fine-pitch ball grid array
µA
microampere
JTAG
joint test action group
mA
milliampere
NoBL
no bus latency
ms
millisecond
OE
output enable
ns
nanosecond
SEL
single event latchup
TCK
test clock
TDI
test data input
TMS
test mode select
TDO
test data output
TQFP
thin quad flat pack
WE
write enable
Document Number: 38-05539 Rev. *N
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 30 of 33
CY7C1355C
CY7C1357C
Document History Page
Document Title: CY7C1355C/CY7C1357C, 9-Mbit (256K × 36/512K × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05539
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
242032
RKF
07/13/2004
New data sheet.
*A
332059
PCI
03/11/2005
Changed status from Preliminary to Final.
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Changed maximum value of IDDZZ parameter from 35 mA to 50 mA).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Updated TAP Instruction
Set (Removed the sub-section Extest Output Bus Tri-state)).
Updated Boundary Scan Order (Changed to match the B rev of these devices).
Updated Boundary Scan Order (Changed to match the B rev of these devices).
Updated Electrical Characteristics (Removed 117 MHz frequency related
information, updated Test Conditions of VOL, VOH parameters, changed
maximum value of ISB1 parameter from 40 mA to 110 mA, changed maximum
value of ISB3 parameter from 40 mA to 100 mA, Changed Test Condition of ISB4
parameter from (VIN VDD – 0.3 V or VIN 0.3 V) to (VIN VIH or VIN VIL)).
Updated Thermal Resistance (Changed JA and Jc for 100-pin TQFP
Package from 25 °C/W and 9 °C/W to 29.41 °C/W and 6.13 °C/W respectively,
changed JA and Jc for 119-ball BGA Package from 25 °C/W and 6 °C/W to
34.1 °C/W and 14.0 °C/W respectively, changed JA and Jc for 165-ball FBGA
Package from 27 °C/W and 6 °C/W to 16.8 °C/W and 3.0 °C/W respectively).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (Added lead-free
information for 100-pin TQFP, 119-ball BGA and 165-ball FBGA Packages)).
*B
351895
PCI
04/19/2005
Updated Electrical Characteristics (Changed maximum value of ISB2
parameter from 30 mA to 40 mA).
Updated Ordering Information (Updated part numbers).
*C
377095
PCI
06/10/2005
Updated Electrical Characteristics (Updated Note 16 (Modified test condition
in from VIH < VDD to VIH VDD)).
*D
408298
RXU
11/16/2005
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE” in the description
of IX parameter).
Updated Ordering Information (Updated part numbers; replaced Package
Name column with Package Diagram in the Ordering Information table).
Replaced three-state with tri-state in all instances across the document.
*E
501793
VKN
09/13/2006
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH,
tTL parameters from 25 ns to 20 ns and maximum value of tTDOV parameter
from 5 ns to 10 ns).
Updated Ordering Information (Updated part numbers).
*F
2896585
NJY
03/20/2010
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
spec 51-85180 – Changed revision from *A to *C.
Updated to new template.
Document Number: 38-05539 Rev. *N
Description of Change
Page 31 of 33
CY7C1355C
CY7C1357C
Document History Page (continued)
Document Title: CY7C1355C/CY7C1357C, 9-Mbit (256K × 36/512K × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05539
Rev.
ECN No.
Orig. of
Change
Submission
Date
*G
3032633
NJY
09/17/2010
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
*H
3210400
NJY
03/30/2011
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (spec 51-85050 (changed revision from *C to *D)).
*I
3353361
PRIT
08/24/2011
Updated Functional Description (Updated Note as “For best practices
recommendations, refer to SRAM System Design Guidelines.”).
Completing Sunset Review.
*J
3612268
PRIT
05/09/2012
Updated Features (Removed 119-ball BGA Package related information).
Updated Functional Description (Removed the Note “For best practices
recommendations, refer to SRAM System Design Guidelines.” and its
reference).
Updated Pin Configurations (Removed 119-ball BGA Package related
information, updated Figure 3 (removed CY7C1355C related information)).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1355C
related information).
Updated Identification Register Definitions (Removed CY7C1355C related
information).
Updated Scan Register Sizes (Removed “Bit Size (× 36)” column).
Removed Boundary Scan Order (Corresponding to 119-ball BGA).
Updated Boundary Scan Order (Removed CY7C1355C related information).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Capacitance (Removed 119-ball BGA Package related information).
Updated Thermal Resistance (Removed 119-ball BGA Package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (Removed 119-ball BGA Package related
information (spec 51-85115 Rev. *C), spec 51-85180 (changed revision from
*C to *E)).
Updated to new template.
*K
3753175
PRIT
09/24/2012
Updated Package Diagrams (spec 51-85180 (changed revision from *E to *F)).
Completing Sunset Review.
*L
4571917
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*M
5509821
PRIT
11/04/2016
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*N
6020935
RMES
01/09/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05539 Rev. *N
Description of Change
Page 32 of 33
CY7C1355C
CY7C1357C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05539 Rev. *N
Revised January 9, 2018
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation.
Page 33 of 33
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