CY7C1361A-100BGC

1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). However, the CE2 chip enable input is only available for TA(GVTI)/A(CY) package version. Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for TA(GVTI)/A(CY) package version and two chip enables for B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions Address pipeline capability Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications JTAG boundary scan for B and T package version Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs (DQa and DQb) along with BWa and BWb (no BWc, BWd, DQc, and DQd). For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. Functional Description The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The GVT71256B36/CY7C1361A and GVT71512B18/ CY7C1363A SRAMs integrate 262,144x36 and 524,288x18 SRAM cells with advanced synchronous peripheral circuitry The GVT71256B36 and GVT71512B18 operate from a +3.3V power supply. All inputs and outputs are LVTTL compatible. Selection Guide 7C1361A-150 7C1363A-150 71256B36-6 71512B18-6 7C1361A-133 7C1363A-133 71256B36-6.5 71512B18-6.5 7C1361A-117 7C1363A-117 71256B36-7 71512B18-7 7C1361A-100 7C1363A-100 71256B36-8 71512B18-8 Maximum Access Time (ns) 6.0 6.5 7.0 8.0 Maximum Operating Current (mA) 400 360 320 270 Maximum CMOS Standby Current (mA) 10 10 10 10 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 11, 2001 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36 (CY7C1361A/GVT71256B36) Functional Block Diagram[1] BYTE a WRITE BWa# BWE# D Q CLK BYTE b WRITE BWb# D Q GW# BYTE c WRITE BWc# D Q BYTE d WRITE ENABLE D CE2 Q byte b write byte a write CE# Q byte c write D byte d write BWd# [2] CE2# OE# ZZ Power Down Logic Input Register ADSP# 16 A Address Register CLR ADV# Output Buffers 256K x 9 x 4 SRAM Array ADSC# Binary Counter & Logic A1-A0 DQa,DQb DQc,DQd MODE 512K x 18 (CY7C1363A/GVT71512B18)Functional Block Diagram BYTE b WRITE BWb# BWE# D Q BYTE a WRITE BWa# D Q ENABLE D CE2 Q byte b write CE# byte a write GW# [2]CE2# ZZ Power Down Logic OE# ADSP# Input Register 17 Address Register 512K x 9 x 2 SRAM Array ADSC# CLR ADV# A1-A0 Binary Counter & Logic Output Buffers A DQa,D Qb MODE Notes: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. 2. CE2 is for AJ/TA version only. 2 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 66 15 16 100-pin TQFP 65 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 67 14 15 100-pin TQFP TA version 16 64 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TA(A) Package Version 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 68 13 67 14 15 16 100-pin TQFP TA version MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A 65 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3 66 17 MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A 16 DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa A A CE# CE2 NC NC BWb# BWa# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A A A CE# CE2 NC NC BWb# BWa# A VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A 10 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 0 1 100-pin TQFP 65 18 CY7C1363A/GVT71512B18 T(AJ) Package Version 512Kx18 100-Pin TQFP NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC 66 17 MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A 17 DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd TA(A) Package Version A A CE# CE2 BWd# BWc# BWb# BWa# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A CY7C1361A/GVT71256B36 256Kx36 100-Pin TQFP A A CE# CE2 BWd# BWc# BWb# BWa# A VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A T(AJ) Package Version A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 Pin Configurations (continued) CY7C1361A/GVT71256B36 256Kx36 119-Ball BGA Top View 1 2 3 4 5 6 7 A VCCQ A A ADSP A A VCCQ B NC CE2 A ADSC A A NC C NC A A VCC A A NC D DQc DQc VSS NC VSS DQb DQb E DQc DQc VSS CE VSS DQb DQb F VCCQ DQc VSS OE VSS DQb VCCQ G DQc DQc BWc ADV BWb DQb DQb H DQc DQc VSS GW VSS DQb DQb J VCCQ VCC NC VCC NC VCC VCCQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VCCQ DQd VSS BWE VSS DQa VCCQ N DQd DQd VSS A1 VSS DQa DQa P DQd DQd VSS A0 VSS DQa DQa R NC A MODE VCC NC A NC T NC NC A A A NC ZZ U VCCQ TMS TDI TCK TDO NC VCCQ CY7C1361A/GVT71256B36 512Kx18 119-Ball BGA Top View 1 2 3 4 5 6 7 A ADSP A A VCCQ A VCCQ A B NC CE2 A ADSC A A NC C NC A A VCC A A NC D DQb NC VSS NC VSS DQa NC VSS NC DQa E NC DQb VSS CE F VCCQ NC VSS OE VSS DQa VCCQ G NC DQb BWb ADV VSS NC DQa H DQb NC VSS GW VSS DQa NC NC VCC NC VCC VCCQ J VCCQ VCC K NC DQb VSS CLK VSS NC DQa L DQb NC VSS NC BWa DQa NC M VCCQ DQb VSS BWE VSS NC VCCQ VSS DQa NC N DQb NC VSS A1 P NC DQb VSS A0 VSS NC DQa R NC A MODE VCC NC A NC T NC A A A A A ZZ VCCQ TMS TDI TCK TDO NC VCCQ U 4 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36 Pin Descriptions x36 PBGA Pins x36 QFP Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (A/T version) 43 (AJ/TA version) 5L 5G 3G 3L Pin Name Type Description A0 A1 A InputSynchronous Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 93 94 95 96 BWa BWb BWc BWd InputSynchronous Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. 4M 87 BWE InputSynchronous Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. 4H 88 GW InputSynchronous Global Write: This active LOW input allows a full 36-bit WRITE to occur independent of the BWE and BWn lines and must meet the set up and hold times around the rising edge of CLK. 4K 89 CLK InputSynchronous Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set up and hold times around the clock’s rising edge. 4E 98 CE InputSynchronous Chip Enable: This active LOW input is used to enable the device and to gate ADSP. 2B 97 CE2 InputSynchronous Chip Enable: This active HIGH input is used to enable the device. (not available for PBGA) 92 (for AJ/TA version only) CE2 InputSynchronous Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions. 4F 86 OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. 4G 83 ADV InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP InputSynchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. 4B 85 ADSC InputSynchronous Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. 3R 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. A NC or HIGH on this pin selects interleaved burst. 7T 64 ZZ InputAsynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). 5 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36 Pin Descriptions (continued) Pin Name x36 PBGA Pins x36 QFP Pins Type Description (a) 6P, 7P, 7N, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G, 6F, 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 DQa DQb DQc DQd Input/ Output Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb. Third Byte is DQc. Fourth Byte is DQd. Input data must meet set up and hold times around the rising edge of CLK. 2U 3U 4U 38 39 43 for BG/B and A/T version TMS TDI TCK Input IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for AJ/TA package version. 5U 42 for BG/B and A/T version TDO Output IEEE 1149.1 test output. LVTTL-level output. Not available for AJ/TA package version. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Core power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Ground Ground: GND. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4, 11, 20, 27, 54, 61, 70, 77 VCCQ I/O Supply 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 6U 14, 16, 66 NC - Pin Name Type Description 38, 39, 42 for AJ/TA Version Output Buffer Supply: +2.5V or +3.3V. No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS. 512K X 18 Pin Descriptions x18 PBGA Pins X18 QFP Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 92 (A/T version) 43 (AJ/TA version) A0 A1 A InputSynchronous Addresses: These inputs are registered and must meet the set up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 5L 3G 93 94 BWa BWb InputSynchronous Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa. BWb controls DQb. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. 4M 87 BWE InputSynchronous Write Enable: This active LOW input gates byte write operations and must meet the set up and hold times around the rising edge of CLK. 6 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 512K X 18 Pin Descriptions (continued) x18 PBGA Pins X18 QFP Pins Pin Name Type Description 4H 88 GW InputSynchronous Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE# and WEn# lines and must meet the set up and hold times around the rising edge of CLK. 4K 89 CLK InputSynchronous Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set up and hold times around the clock’s rising edge. 4E 98 CE InputSynchronous Chip Enable: This active LOW input is used to enable the device and to gate ADSP. 2B 97 CE2 inputSynchronous Chip Enable: This active HIGH input is used to enable the device. (not available for PBGA) 92 (for AJ/TA Version only) CE2 inputSynchronous Chip Elnable: This active LOW input is used to enable the device. Not available for B and T package versions. 4F 86 OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. 4G 83 ADV InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP InputSynchronous Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. 4B 85 ADSC InputSynchronous Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. 3R 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. A NC or HIGH on this pin selects interleaved burst. 7T 64 ZZ Input-Asynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQa DQb Input/ Output Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input data must meet setup and hold times around the rising edge of CLK. 2U 3U 4U 38 39 43 for B and T version TMS TDI TCK Input IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for AJ/TA package version. 5U 42 for B and T version TDO Output IEEE 1149.1 test output. LVTTL-level output. Not available for AJ/TA package version. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Core power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Ground Ground: GND. 7 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 512K X 18 Pin Descriptions (continued) x18 PBGA Pins X18 QFP Pins Pin Name Type 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 4, 11, 20, 27, 54, 61, 70, 77 VCCQ I/O Supply 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 6U 1-3, 6, 7, 14, 16, 25, 28-30, 5153, 56, 57, 66, 75, 78, 79, 80, 95, 96 NC - Description Output Buffer Supply: +2.5V or +3.3V. No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS. 38, 39, 42 for AJ/TA version Burst Address Table (MODE = NC/VCC) Burst Address Table (MODE = GND) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 8 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 Truth Table[3, 4, 5, 6, 7, 8, 9] Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D Partial Truth Table for Read/Write[10] FUNCTION GW BWE BWa BWb BWc BWd READ H H X X X X READ H L H H H H WRITE one byte H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X Notes: 3. X = “Don’t Care.” H = logic HIGH. L = logic LOW. For x36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. For x18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH. 4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd. 5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 6. Suspending burst generates wait cycle. 7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 9. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. 10. For X18 product, There are only BWa and BWb. 9 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. Overview This device incorporates a Serial Boundary Scan Access Port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state. Test Access Port (TAP) Registers Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Test Access Port (TAP) TCK - Test Clock (Input) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS - Test Mode Select (Input) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. TDI - Test Data In (Input) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 2.) Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for x36 device and 51 bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. TDO - Test Data Out (Output) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.) The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name, the third column is the TQFP pin number, and the fourth column is the PBGA bump number. 10 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 Identification (ID) Register Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. TAP Controller Instruction Set SAMPLE/PRELOAD Overview SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device’s input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. Reserved Do not use these instructions. They are reserved for future use. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in 11 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 1 TEST-LOGIC RESET 0 0 REUN-TEST/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 Figure 1. TAP Controller State Diagram[11] Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. 12 UPDATE-IR 1 0 CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register x . . . . 2 Boundary Scan Register [12] TDI TAP Controller TDI Figure 2. TAP Controller Block Diagram TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted) Parameter VIH Min. Max. Unit Input High (Logic 1) Voltage[13, 14] Description Test Conditions 2.0 VCC + 0.3 V Voltage[13, 14] –0.3 0.8 V –5.0 5.0 µA VIl Input Low (Logic 0) ILI Input Leakage Current 0V < VIN < VCC ILI TMS and TDI input Leakage Current 0V < VIN < VCC –30 30 µA ILO Output Leakage Current Output disabled, 0V < VIN < VCCQ –5.0 5.0 µA VOLC LVCMOS Output Low Voltage[13, 15] IOLC = 100 µA 0.2 V VOHC LVCMOS Output High Voltage[13, 15] IOHC = 100 µA VOLT VOHT LVTTL Output Low Voltage[13] IOLT = 8.0 mA LVTTL Output High Voltage[13] IOHT = 8.0 mA VCC – 0.2 V 0.4 2.4 V V Notes: 12. X = 69 for the x36 configuration; X = 50 for the x18 configuration. 13. All Voltage referenced to VSS (GND). 14. Overshoot: VIH(AC)