CY7C1361C_2009

CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1361C/CY7C1363C[1] is a 3.3V, 256K x 36/512K x 18 synchronous flow-through SRAMs, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1361C/CY7C1363C enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1361C/CY7C1363C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Supports 100, 133 MHz Bus Operations Supports 100 MHz Bus Operations (Automotive) 256K × 36/512K × 18 Common I/O 3.3V –5% and +10% Core Power Supply (VDD) 2.5V or 3.3V I/O Power Supply (VDDQ) Fast Clock-to-Output Times ❐ 6.5 ns (133-MHz version) Provide High Performance 2-1-1-1 Access Rate User-selectable Burst Counter supporting Intel® Pentium® Interleaved or Linear Burst Sequences Separate Processor and Controller Address Strobes Synchronous Self-timed Write Asynchronous Output Enable Available in Pb-free 100-Pin TQFP Package, Pb-free and non Pb-free 119-Ball BGA Package, and 165-Ball FBGA Package TQFP Available with 3-Chip Enable and 2-Chip Enable IEEE 1149.1 JTAG-Compatible Boundary Scan “ZZ” Sleep Mode option ■ ■ ■ ■ ■ ■ ■ ■ ■ Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial/ Industrial Automotive 133 MHz 6.5 250 40 100 MHz 8.5 180 40 60 Unit ns mA mA mA Notes 1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05541 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 26, 2009 [+] Feedback CY7C1361C/CY7C1363C Logic Block Diagram – CY7C1361C (256K x 36) A 0, A1, A ADDRESS REGISTER A [1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D , DQP D BW D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE REGISTER DQ A , DQP A BW A BWE GW CE1 CE2 CE3 OE DQ A , DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQ D , DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BW B BYTE WRITE REGISTER BW C MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL Logic Block Diagram – CY7C1363C (512K x 18) A 0,A1,A MODE ADDRESS REGISTER A[1:0] ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B ,DQP B WRITE REGISTER DQ B ,DQP B WRITE DRIVER BW B MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS BW A BWE GW DQ A ,DQP A WRITE REGISTER DQ A ,DQP A WRITE DRIVER INPUT REGISTERS DQs DQP A DQP B CE 1 CE 2 CE 3 OE ENABLE REGISTER ZZ SLEEP CONTROL Document #: 38-05541 Rev. *G Page 2 of 32 [+] Feedback CY7C1361C/CY7C1363C Pin Configurations Figure 1. 100-Pin TQFP (3 Chip Enables - A version) A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1361C (A) (256K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1363C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A Document #: 38-05541 Rev. *G MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 2. 100-Pin TQFP (2 Chip Enables - AJ Version) A A CE1 CE2 BWD BWC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1361C (256K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1363C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 MODE NC NC VSS VDD NC NC A A A A A A A Document #: 38-05541 Rev. *G A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 3. 100- Ball BGA (2 Chip Enables with JTAG) CY7C1361C (256K x 36) 1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M TMS 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC/512M NC/1G DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ CY7C1363C (512K x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC/72M VDDQ 2 A CE2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC/36M TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC/512M NC/1G NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Document #: 38-05541 Rev. *G Page 5 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 4. 165-Ball FBGA (3 Chip Enable) CY7C1361C (256K x 36) 1 A B C D E F G H J K L M N P R NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC/72M NC/36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/18M A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A CY7C1363C (512K x 18) 1 A B C D E F G H J K L M N P R NC/288M NC/144M NC NC NC NC NC VSS DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB VSS NC NC NC NC NC NC/72M NC/36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/18M A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A Document #: 38-05541 Rev. *G Page 6 of 32 [+] Feedback CY7C1361C/CY7C1363C Pin Definitions Name A0, A1, A I/O InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull up. Power supply inputs to the core of the device. Page 7 of 32 BWA,BWB BWC,BWD GW CLK CE1 CE2 CE3[2] OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous BWE ZZ InputSynchronous InputAsynchronous I/OSynchronous DQs DQPX MODE I/OSynchronous InputStatic Power Supply VDD Document #: 38-05541 Rev. *G [+] Feedback CY7C1361C/CY7C1363C Pin Definitions (continued) Name VDDQ VSS VSSQ TDO I/O I/O Power Supply Power supply for the I/O circuitry. Ground I/O Ground Ground for the core of the device. Ground for the I/O circuitry. Description JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being used, this pin should be left unconnected. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock – Ground/DNU Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. This pin can be connected to Ground or should be left floating. TDI TMS TCK NC VSS/DNU Document #: 38-05541 Rev. *G Page 8 of 32 [+] Feedback CY7C1361C/CY7C1363C Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). The CY7C1361C/CY7C1363C supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] is written into the specified address location. Byte writes are allowed. All I/Os are tristated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1361C/CY7C1363C provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Table 1. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted active and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Partial Truth Table for Read/Write on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device.Byte writes are allowed. All I/Os are tristated during a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Table 2. Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation ‘sleep’ mode. Two clock cycles are required to enter into or exit from this ‘sleep’ mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the ‘sleep’ mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the ‘sleep’ mode. CE1, CE2, CE3[2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 9 of 32 Document #: 38-05541 Rev. *G [+] Feedback CY7C1361C/CY7C1363C ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Comm/ind’l Automotive 2tCYC 2tCYC 0 Min Max 50 60 2tCYC Unit mA mA ns ns ns ns Truth Table The Truth Table for CY7C1361C and CY7C1363C follows. [3, 4, 5, 6, 7] Cycle Description Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Sleep Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address CE CE CE ZZ 1 2 3 Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L X X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE OE CLK X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tristate Tristate Tristate Tristate Tristate Tristate Q Tristate D Q Tristate Q Tristate Q Tristate D D Q Tristate Q Tristate D D Notes 3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05541 Rev. *G Page 10 of 32 [+] Feedback CY7C1361C/CY7C1363C Partial Truth Table for Read/Write The Partial Truth Table for Read/Write follows.[3, 8] Function (CY7C1361C) Read Read Write Byte (A, DQPA) Write Byte (B, DQPB) Write Bytes (B, A, DQPA, DQPB) Write Byte (C, DQPC) Write Bytes (C, A, DQPC, DQPA) Write Bytes (C, B, DQPC, DQPB) Write Bytes (C, B, A, DQPC, DQPB, DQPA) Write Byte (D, DQPD) Write Bytes (D, A, DQPD, DQPA) Write Bytes (D, B, DQPD, DQPA) Write Bytes (D, B, A, DQPD, DQPB, DQPA) Write Bytes (D, B, DQPD, DQPB) Write Bytes (D, B, A, DQPD, DQPC, DQPA) Write Bytes (D, C, A, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Truth Table for Read/Write The Truth Table for Read/Write follows.[3, 8] Function (CY7C1363C) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X Note 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05541 Rev. *G Page 11 of 32 [+] Feedback CY7C1361C/CY7C1363C IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361C/CY7C1363C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1361C/CY7C1363C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 1 TAP Controller Block Diagram 0 Bypass Register 210 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TM S TAP CONTROLLER The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document #: 38-05541 Rev. *G Page 12 of 32 [+] Feedback CY7C1361C/CY7C1363C Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail in this section. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The 119-Ball BGA Boundary Scan Order on page 18 and 165-Ball FBGA Boundary Scan Order on page 19 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 16. Document #: 38-05541 Rev. *G Page 13 of 32 [+] Feedback CY7C1361C/CY7C1363C The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK ) t TM SS 2 3 4 5 6 t TH t TM SH t TL t CY C T est M ode Select (TM S) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE UNDEFINED Document #: 38-05541 Rev. *G Page 14 of 32 [+] Feedback CY7C1361C/CY7C1363C TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH Time TCK Clock LOW Time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 0 5 5 5 20 20 10 50 20 ns MHz ns ns ns ns ns ns ns Parameter Min Max Unit Output Times Set-up Times Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05541 Rev. *G Page 15 of 32 [+] Feedback CY7C1361C/CY7C1363C 3.3V TAP AC Test Conditions Input pulse levels.................................................VSS to 3.3V Input rise and fall times....................................................1 ns Input timing reference levels........................................... 1.5V Output reference levels .................................................. 1.5V Test load termination supply voltage .............................. 1.5V 2.5V TAP AC Test Conditions Input pulse levels................................................. VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50 Ω T DO Z O= 50 Ω 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50 Ω TDO Z O= 50 Ω 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Description IOH = –4.0 mA IOH = –1.0 mA IOH = –100 µA IOL = 8.0 mA IOL = 8.0 mA IOL = 100 µA Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 –0.5 –0.3 –5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.7 5 Max Unit V V V V V V V V V V V V µA Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[12] Device Width (23:18) 119-BGA Device Width (23:18) 165-FBGA Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1361C (256K x36) 000 01011 101001 000001 100110 00000110100 1 CY7C1363C (512K x18) 000 01011 101001 000001 010110 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Notes 11. All voltages referenced to VSS (GND). 12. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05541 Rev. *G Page 16 of 32 [+] Feedback CY7C1361C/CY7C1363C Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball FBGA package) Bit Size (x 36) 3 1 32 71 71 Bit Size (x 18) 3 1 32 71 71 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05541 Rev. *G Page 17 of 32 [+] Feedback CY7C1361C/CY7C1363C 119-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) Bit # ball ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 K4 H4 M4 F4 B4 A4 G4 C3 B3 D6 H7 G6 E6 D7 E7 F6 G7 H6 T7 K7 L6 N6 P7 N7 M6 L7 K6 P6 T4 A3 C5 B5 A5 C6 A6 B6 Signal Name CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB DQB DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA DQA DQA DQA DQPA A A A A A A A A Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ball ID P4 N4 R6 T5 T3 R2 R3 P2 P1 L2 K1 N2 N1 M2 L1 K2 Internal H1 G2 E2 D1 H2 G1 F2 E1 D2 C2 A2 E4 B2 L3 G3 G5 L5 Internal Signal Name A0 A1 A A A A MODE DQPD DQD DQD DQD DQD DQD DQD DQD DQD Internal DQC DQC DQC DQC DQC DQC DQC DQC DQPC A A CE1 CE2 BWD BWC BWB BWA Internal Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ball ID K4 H4 M4 F4 B4 A4 G4 C3 B3 T2 Internal Internal Internal D6 E7 F6 G7 H6 T7 K7 L6 N6 P7 Internal Internal Internal Internal Internal T6 A3 C5 B5 A5 C6 A6 B6 CY7C1363C (512K x 18) Signal Name CLK GW BWE OE ADSC ADSP ADV A A A Internal Internal Internal DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA Internal Internal Internal Internal Internal A A A A A A A A Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ball ID P4 N4 R6 T5 T3 R2 R3 Internal Internal Internal Internal P2 N1 M2 L1 K2 Internal H1 G2 E2 D1 Internal Internal Internal Internal Internal C2 A2 E4 B2 Internal Internal G3 L5 Internal Signal Name A0 A1 A A A A MODE Internal Internal Internal Internal DQPB DQB DQB DQB DQB Internal DQB DQB DQB DQB Internal Internal Internal Internal Internal A A CE1 CE2 Internal Internal BWB BWA Internal Document #: 38-05541 Rev. *G Page 18 of 32 [+] Feedback CY7C1361C/CY7C1363C 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ball ID B6 B7 A7 B8 A8 B9 A9 B10 A10 C11 E10 F10 G10 D10 D11 E11 F11 G11 H11 J10 K10 L10 M10 J11 K11 L11 M11 N11 R11 R10 P10 R9 P9 R8 P8 P11 Signal Name CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB DQB DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA DQA DQA DQA DQPA A A A A A A A A Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ball ID R6 P6 R4 P4 R3 P3 R1 N1 L2 K2 J2 M2 M1 L1 K1 J1 Internal G2 F2 E2 D2 G1 F1 E1 D1 C1 B2 A2 A3 B3 B4 A4 A5 B5 A6 Signal Name A0 A1 A A A A MODE DQPD DQD DQD DQD DQD DQD DQD DQD DQD Internal DQC DQC DQC DQC DQC DQC DQC DQC DQPC A A CE1 CE2 BWD BWC BWB BWA CE3 Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ball ID B6 B7 A7 B8 A8 B9 A9 B10 A10 A11 Internal Internal Internal C11 D11 E11 F11 G11 H11 J10 K10 L10 M10 Internal Internal Internal Internal Internal R11 R10 P10 R9 P9 R8 P8 P11 CY7C1363C (512K x 18) Signal Name CLK GW BWE OE ADSC ADSP ADV A A A Internal Internal Internal DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA Internal Internal Internal Internal Internal A A A A A A A A Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ball ID R6 P6 R4 P4 R3 P3 R1 Internal Internal Internal Internal N1 M1 L1 K1 J1 Internal G2 F2 E2 D2 Internal Internal Internal Internal Internal B2 A2 A3 B3 Internal Internal A4 B5 A6 Signal Name A0 A1 A A A A MODE Internal Internal Internal Internal DQPB DQB DQB DQB DQB Internal DQB DQB DQB DQB Internal Internal Internal Internal Internal A A CE1 CE2 Internal Internal BWB BWA CE3 Document #: 38-05541 Rev. *G Page 19 of 32 [+] Feedback CY7C1361C/CY7C1363C Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage on VDD Relative to GND .......–0.5V to + 4.6V Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD DC Voltage Applied to Outputs in tri-state.............................................–0.5V to VDDQ + 0.5V DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch up Current..................................................... >200 mA Neutron Soft Error Immunity Parameter LSBU Description Logical Single-Bit Upsets Logical Multi-Bit Upsets Single Event Latch up Test Conditions 25°C Typ 361 Max* 394 Unit FIT/ Mb FIT/ Mb FIT/ Dev LMBU 25°C 0 0.01 SEL 85°C 0 0.1 * No LMBU or SEL events occurred during testing; this column represents a statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Operating Range Ambient VDD VDDQ Temperature Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Automotive –40°C to +125°C Range Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[13] Input LOW Voltage[13] Input Leakage Current except ZZ and MODE Input Current of MODE [13, 14] Test Conditions for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH = −4.0 mA for 2.5V I/O, IOH = −1.0 mA for 3.3V I/O, IOL= 8.0 mA for 2.5V I/O, IOL= 1.0 mA for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND ≤ VI ≤ VDDQ Min 3.135 3.135 2.375 2.4 2.0 2.0 1.7 –0.3 –0.3 –5 –30 Unit V V V V V 0.4 V 0.4 V VDD + 0.3V V VDD + 0.3V V 0.8 V 0.7 V 5 μA μA μA μA μA μA Max 3.6 VDD 2.625 IOZ Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD Output Leakage Current GND < VI < VDDQ, Output Disabled 5 –5 –5 30 5 Notes 13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 14. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05541 Rev. *G Page 20 of 32 [+] Feedback CY7C1361C/CY7C1363C Electrical Characteristics Over the Operating Range Parameter Description IDD VDD Operating Supply Current ISB1 Automatic CE Power-down Current—TTL Inputs Automatic CE Power-down Current—CMOS Inputs Automatic CE Power-down Current—CMOS Inputs Automatic CE Power-down Current—TTL Inputs (continued)[13, 14] Min Max 250 180 110 150 40 Unit mA mA mA mA Test Conditions VDD = Max., IOUT = 0 mA, 7.5 ns cycle,133 MHz f = fMAX = 1/tCYC 10 ns cycle,100 MHz Max. VDD, Device Deselected, VIN> VIH or VIN < VIL, f = fMAX, inputs switching Max. VDD, Device Deselected, VIN > VDD – 0.3V or VIN < 0.3V, f = 0, inputs static All speeds (Comm/Ind’l) 10 ns cycle,100 MHz (Automotive) All speeds ISB2 ISB3 ISB4 Max. VDD, Device Deselected, All speeds (Comm/Ind’l) VIN > VDDQ – 0.3V or VIN < 0.3V, 10 ns cycle,100 MHz f = fMAX, inputs switching (Automotive) Max. VDD, Device Deselected, All speeds (Comm/Ind’l) VIN > VIH or VIN < VIL 10 ns cycle,100 MHz f = 0, inputs static (Automotive) 100 120 40 60 mA mA mA mA Capacitance[15] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max. 5 5 5 119 BGA 165 FBGA Max. Max. 5 5 5 5 7 7 Unit pF pF pF Thermal Resistance[15] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51 ΘJA ΘJC 100 TQFP Package 29.41 6.31 119 BGA 165 FBGA Package Package 34.1 16.8 14.0 3.0 Unit °C/W °C/W Figure 5. AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω R = 317Ω VDDQ 5 pF GND R = 351Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1 ns VT = 1.5V (a) 2.5V I/O Test Load OUTPUT Z0 = 50Ω INCLUDING JIG AND SCOPE 2.5V ≤ 1 ns (b) R = 1667Ω VDDQ (c) ALL INPUT PULSES 10% 90% 90% 10% ≤ 1 ns OUTPUT RL = 50Ω VT = 1.25V 5 pF GND R = 1538Ω (a) INCLUDING JIG AND SCOPE ≤ 1 ns (b) (c) Note 15. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05541 Rev. *G Page 21 of 32 [+] Feedback CY7C1361C/CY7C1363C Switching Characteristics Over the Operating Range[20, 21] Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW, BWE, BW[A:D] Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSP, ADSC Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BW[A:D] Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Clock to Low-Z[17, 18, 19] High-Z[17, 18, 19] Low-Z[17, 18, 19] High-Z[17, 18, 19] 0 3.5 2.0 0 3.5 3.5 0 3.5 6.5 2.0 0 3.5 3.5 8.5 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 3.0 3.0 10 4.0 4.0 ns ns ns Description VDD(Typical) to the first Access[16] –133 Min 1 Max Min 1 –100 Max Unit ms OE LOW to Output Valid OE LOW to Output OE HIGH to Output Notes 16. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 18. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 19. This parameter is sampled and not 100% tested. 20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 21. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05541 Rev. *G Page 22 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams Figure 6. Read Cycle Timing[22] tCYC CLK t CH t CL t ADS tADH ADSP t ADS tADH ADSC t AS tAH ADDRESS A1 t WES t WEH A2 G W, BWE,BW X t CES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t CLZ t OEHZ t OELZ t CDV t DOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ DON’T CARE BURST READ UNDEFINED Note 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05541 Rev. *G Page 23 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 7. Write Cycle Timing[22, 23] t CYC CLK t CH t CL t ADS tADH ADSP t ADS tADH ADSC extends burst t ADS tADH ADSC t AS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t D(A1) OEHZ D ata Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Note 23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05541 Rev. *G Page 24 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 8. Read/Write Cycle Timing[22, 24, 25] tCYC CLK t CH t CL t ADS tADH ADSP ADSC t AS tAH ADDRESS A1 A2 A3 t WES t WEH A4 A5 A6 BWE, BW X t CES tCEH CE ADV OE t DS tDH t OELZ Data In (D) D ata Out (Q) High-Z t OEHZ D(A3) t CDV D(A5) D(A6) Q(A1) Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) BURST READ UNDEFINED Q(A4+2) Q(A4+3) Back-to-Back WRITEs Back-to-Back READs Notes 24. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 25. GW is HIGH. Document #: 38-05541 Rev. *G Page 25 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 9. ZZ Mode Timing[26, 27] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only A LL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05541 Rev. *G Page 26 of 32 [+] Feedback CY7C1361C/CY7C1363C Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Table 3. Ordering Information Speed (MHz) 133 Ordering Code CY7C1361C-133AXC CY7C1363C-133AXC CY7C1361C-133AJXC CY7C1363C-133AJXC CY7C1361C-133AXI CY7C1363C-133AJXI 100 CY7C1361C-100AXC CY7C1361C-100BGC 100 CY7C1361C-100AXE Package Diagram Part and Package Type Operating Range Commercial 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial Commercial Automotive Document #: 38-05541 Rev. *G Page 27 of 32 [+] Feedback CY7C1361C/CY7C1363C Package Diagrams (continued) Figure 10. 100-Pin TQFP (14X20X1.4 mm) 16.00±0.20 14.00±0.10 100 1 81 80 1.40±0.05 0.30±0.08 22.00±0.20 20.00±0.10 0.65 TYP. 30 31 50 51 12°±1° (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. 0° MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX. NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL 51-85050-*B A Document #: 38-05541 Rev. *G 0.10 R 0.08 MIN. 0.20 MAX. Page 28 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 11. 119-Ball BGA (14X22X2.4 mm) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 A B C 1.27 D E F G 22.00±0.20 H 19.50 J K L M N P R T U 10.16 20.32 2 34 5 6 7 7 6 5 4321 A B C D E F G H J K L M N P R T U 1.27 0.70 REF. A 3.81 12.00 B 2.40 MAX. 7.62 14.00±0.20 0.90±0.05 0.25 C 30° TYP. 0.15(4X) 0.15 C 51-85115-*B SEATING PLANE 0.56 C 0.60±0.10 Document #: 38-05541 Rev. *G Page 29 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 12. 165-Ball FBGA (13X15X1.4 mm) TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER Ø0.08 M C 1 A B 11 C A D B E F G 10 9 8 7 6 5 2 3 4 5 6 7 8 9 10 11 Ø0.25 M C A B Ø0.50 -0.06 (165X) +0.14 4 3 2 1 1.00 C D E 15.00±0.10 H J F G 15.00±0.10 K L M N P R 14.00 H J K 7.00 L M N A P R A 5.00 B 13.00±0.10 10.00 1.00 1.40 MAX. 0.53±0.05 0.25 C B 0.15 C 0.15(4X) 13.00±0.10 SEATING PLANE 0.36 C 0.35±0.06 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AC 51-85180-*B Document #: 38-05541 Rev. *G Page 30 of 32 [+] Feedback CY7C1361C/CY7C1363C Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Document Number: 38-05541 REV. ** *A *B ECN NO. 241690 278969 332059 Submission Date See ECN See ECN See ECN Orig. of Change RKF RKF PCI New data sheet Changed Boundary Scan order to match the B rev of these devices. Removed 117-MHz Speed Bin Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Changed Device Width (23:18) for 119-BGA from 000001 to 101001 Added separate row for 165 -FBGA Device Width (23:18) Changed IDDZZ from 35 mA to 50 mA Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA, respectively Modified VOL, VOH test conditions Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH or VIN ≤ VIL) in the Electrical Characteristics table Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and 6.13 °C/W respectively Changed ΘJA and ΘJc for BGA Package from 25 and 6°C/W to 34.1 and 14.0 °C/W respectively Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0 °C/W respectively Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA packages Updated Ordering Information Table Changed ISB2 from 30 to 40 mA Modified test condition in note# 14 from VIH < VDD to VIH < VDD Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed tri state to tri-state. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the ordering information. Included Automotive range. Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Description of Change *C *D 377095 408298 See ECN See ECN PCI RXU *E *F 433033 501793 See ECN See ECN NXR VKN *G 2756340 08/26/2009 VKN/AESA Updated template Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Document #: 38-05541 Rev. *G Page 31 of 32 [+] Feedback CY7C1361C/CY7C1363C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05541 Rev. *G Revised August 26, 2009 Page 32 of 32 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback