CY7C1360A
CY7C1362A
256K x 36/512K x 18 Synchronous
Pipelined Burst SRAM
Features
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Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
Fast clock speed: 225, 200, 166, and 150 MHz
Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V-tolerant inputs except I/Os
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for A package version and two chip
enables for BG and AJ package versions
Address pipeline capability
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down feature available using ZZ
mode or CE deselect
JTAG boundary scan for BG and AJ package version
Low-profile 119-bump, 14-mm × 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144
× 36 and 524,288 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE2 and CE3), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE3 chip enable
input is only available for the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the BGA and TQFP AJ package versions, four pins are
used to implement JTAG test capabilities: Test Mode Select
(TMS), Test Data-In (TDI), Test Clock (TCK), and Test
Data-Out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation. The
TA package version does not offer the JTAG capability.
The CY7C1360A and CY7C1362A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
Selection Guide
7C1360A-225
7C1362A-225
7C1360A-200
7C1362A-200
7C1360A-166
7C1362A-166
7C1360A-150
7C1362A-150
Unit
Maximum Access Time
2.5
3.0
3.5
3.5
ns
Maximum Operating Current
650
600
520
460
mA
Maximum CMOS Standby Current
10
10
10
10
mA
Cypress Semiconductor Corporation
Document #: 38-05258 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1360A
CY7C1362A
Functional Block Diagram—256K × 36[1]
BYTE a WRITE
BWa
BWa
BWE
BWE
CLK
CLK
D
Q
BYTE b WRITE
BW
BWb
b
D
Q
GW
GW
BYTE c WRITE
BW
BWc
c
D
Q
BYTE d WRITE
D
ENABLE
Q
D
Q
byte b write
byte a write
CECE
1
CECE2
2
[2] CE
CE2
3
Q
byte c write
D
byte d write
BWd
BW
d
OE
OE
Power Down Logic
Input
Register
ADSP
ADSP
A
A
16
Address
Register
CLR
ADV
ADV
A0-A1
A1-A0
OUTPUT
REGISTER
256K x 9 x 4
SRAM Array
ADSC
ADSC
D
Output Buffers
ZZ ZZ
DQa, DQb, DQa,DQb
DQc, DQd DQc,DQd
Q
Binary
Counter
& Logic
MODE
MODE
Functional Block Diagram—512K × 18[1]
BYTE b
WRITE
BWbBWb
BWEBWE
D
Q
CLK
BYTE a
WRITE
BWaBWa
D
Q
ZZ
ZZ
ENABLE
D
Q
D
Q
byte b write
CE1 CE
CE2 CE2
[2]
CE3CE2
byte a write
GW GW
Power Down Logic
OE OE
ADSP
ADSP
17
Address
Register
ADSC
ADSC
CLR
ADV
ADV
A1-A0
A0-A1
MODE
MODE
Binary
Counter
& Logic
OUTPUT
REGISTER
D
Q
Output Buffers
A
512K x 9 x 2
SRAM Array
A
Input
Register
DQa, DQb, DQa,DQb
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE3 is for A version only.
Document #: 38-05258 Rev. *C
Page 2 of 28
CY7C1360A
CY7C1362A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE3
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
CY7C1360A
256K × 36 100-pin TQFP
Top View
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
AJ Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
A
A
CE
CE2
NC
NC
BWb
BWa
CE3
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
A Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Document #: 38-05258 Rev. *C
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A Version
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
100-pin TQFP
AJ Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100-pin TQFP
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1362A
512K × 18 100-pin TQFP
Top View
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
NC
NC
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
Page 3 of 28
CY7C1360A
CY7C1362A
Pin Configurations (continued)
CY7C1360A 256K × 36 119-ball BGA Top View
1
2
3
4
5
6
7
A
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1362A 512K × 18 119-ball BGA Top View
A
1
2
3
4
5
6
7
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
CE3
NC
C
NC
A
A
VCC
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQa
NC
E
NC
DQb
VSS
CE
VSS
NC
DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
ADV
VSS
NC
DQa
H
DQb
NC
VSS
GW
VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
BWE
VSS
NC
VCCQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05258 Rev. *C
Page 4 of 28
CY7C1360A
CY7C1362A
256K × 36 Pin Descriptions
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B, 5B,
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
X36 PBGA Pins
37
A0
36
A1
35, 34, 33, 32, 100, A
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (AJ Version)
43 (A Version)
X36 QFP Pins
Name
InputSynchronous
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write: A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
2B
97
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable
the device.
–
(not available for
PBGA)
92
CE3
(for A version only)
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
4F
86
OE
4G
83
4A
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
ADV
InputSynchronous
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
7T
64
ZZ
Document #: 38-05258 Rev. *C
InputSleep: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal operation,
this input has to be either LOW or NC (No Connect).
Page 5 of 28
CY7C1360A
CY7C1362A
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
(a) 6P, 7P, 7N, 6N, 6M,
6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G, 6F,
6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E, 2F,
1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L, 2M,
1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9,
12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
2U
3U
4U
Name
Type
Description
DQa
DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
38
39
43
for BG and AJ
version
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not
available for A package version.
5U
42
for BG and AJ
version
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not
available for A package version.
4C, 2J, 4J, 6J, 4R
15, 41, 65, 91
VCC
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26, VSS
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,
5M, 3N, 5N, 3P, 5P
76, 90
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,
1M, 7M, 1U, 7U
61, 70, 77
VCCQ
1B, 7B, 1C, 7C, 4D, 3J, 14, 16, 66
5J, 4L, 1R, 5R, 7R, 1T, 38, 39, 42 for A
2T, 6T, 6U
version
NC
Power Supply Core power supply: +3.3V –5% and +10%
Ground
I/O Power
Supply
-
Ground: GND.
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
512K × 18 Pin Descriptions
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T, 5T,
6T
X18 PBGA Pins
37
A0
36
A1
35, 34, 33, 32, 100, A
99, 82, 81, 80, 48,
47, 46, 45, 44, 49,
50
92 (AJ Version)
43 (A Version)
X18 QFP Pins
InputSynchronous
Addresses: These inputs are registered and must meet
the set up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
5L
3G
93
94
BWa
BWb
InputSynchronous
Byte Write Enables: A byte Write enable is LOW for a
Write cycle and HIGH for a Read cycle. BWa controls DQa.
BWb controls DQb. Data I/O are high impedance if either
of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 18-bit
Write to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip
enables, Write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
2B
97
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable the
device.
Document #: 38-05258 Rev. *C
Name
Page 6 of 28
CY7C1360A
CY7C1362A
512K × 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins
Name
–
(not available for
PBGA)
92
CE3
(for A Version only)
4F
86
OE
4G
83
4A
Type
Description
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
ADV
InputSynchronous
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to be
registered and a Read cycle is initiated using the new
address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input
causes device to be deselected or selected along with new
external address to be registered. A Read or Write cycle
is initiated depending upon Write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. An NC or HIGH on this pin
selects Interleaved Burst.
7T
64
ZZ
(a) 6D, 7E, 6F, 7G, 6H,
7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
(a) 58, 59, 62, 63, DQa
68, 69, 72, 73, 74 DQb
(b) 8, 9, 12, 13, 18,
19, 22, 23, 24
2U
3U
4U
38
39
43
for BG and AJ
versions
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not
available for A package version.
5U
42
for BG and AJ
version
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not
available for A package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Core power supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F,
5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N,
5N, 3P, 5P
5, 10, 17, 21, 26, VSS
40, 55, 60, 67, 71,
76, 90
Ground
Ground: GND.
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,
1M, 7M, 1U, 7U
61, 70, 77
1B, 7B, 1C, 7C, 2D,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H, 3J,
5J, 1K, 6K, 2L, 4L, 7L,
6M, 2N, 7N, 1P, 6P,
1R, 5R, 7R, 1T, 4T, 6U
VCCQ
1–3, 6, 7, 14, 16, NC
25, 28–30, 51–53,
56, 57, 66, 75, 78,
79, 80, 95, 96
38, 39, 42 for A
Version
Document #: 38-05258 Rev. *C
InputSleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this
input has to be either LOW or NC (No Connect).
Input/
Output
I/O Power
Supply
–
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set up and hold times around the
rising edge of CLK.
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
Page 7 of 28
CY7C1360A
CY7C1362A
Introduction
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
Functional Overview
ADSP triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BWx
signals. The CY7C1360A/CY7C1362A provides byte Write
capability that is described in the Write cycle description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1360A and BWa,b for
CY7C1362A) input will selectively write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.8 ns
(133-MHz device).
The CY7C1360A/CY7C1362A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1360A and BWa,b
for 1362A) inputs. A Global Write Enable (GW) overrides all
byte Write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed Write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within preliminary ns (200-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Document #: 38-05258 Rev. *C
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the Write inputs (GW, BWE,
and BWx) are asserted active to conduct a Write to the desired
byte(s). ADSC triggered Write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global Write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte Write is conducted,
only the selected bytes are written. Bytes not selected during
a byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a Write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1360A/CY7C1362A provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel® Pentium® applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Page 8 of 28
CY7C1360A
CY7C1362A
Burst Address Table (MODE = NC/VCC)
First
Address (external)
Second
Address
(internal)
Third
Address
(internal)
Burst Address Table (MODE = GND)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Next Cycle
Address Used ZZ
CE3
CE2
CE1 ADSP ADSC ADV
OE
DQ
DQ
Unselected
None
O
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
O
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
O
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
O
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
O
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
O
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
O
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
O
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
O
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
O
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
O
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
O
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
O
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
O
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
O
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
O
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
O
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
O
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
O
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
O
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
O
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
O
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a Write operation following a Read operation, OE must be HIGH before the input-data-required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05258 Rev. *C
Page 9 of 28
CY7C1360A
CY7C1362A
Partial Truth Table for Read/Write[10]
Function (1360A)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
0
Write Byte 1 – DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1362A)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 – DQ[7:0] and DP0
1
0
1
0
Write Byte 1 – DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
Min.
2tCYC
Max.
Unit
10
mA
2tCYC
ns
ns
Note:
10. For the X18 product, there are only BWa and BWb.
Document #: 38-05258 Rev. *C
Page 10 of 28
CY7C1360A
CY7C1362A
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port
TCK–Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS–Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI–Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1, TAP Controller State Diagram). It is
allowable to leave this pin unconnected if it is not used in an
application. The pin is pulled up internally, resulting in a logic
HIGH level. TDI is connected to the Most Significant Bit (MSB)
of any register (see Figure 2.).
TDO–Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Significant Bit (LSB) of any register (see Figure 2.).
Document #: 38-05258 Rev. *C
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TAP Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two LSBs of the serial instruction
register are loaded with a binary “01” pattern to allow for fault
isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for the x36 device and
51 bits for the x18 device. The boundary scan register, under
the control of the TAP controller, is loaded with the contents of
the device I/O ring when the controller is in Capture-DR state
and then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Page 11 of 28
CY7C1360A
CY7C1362A
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in IEEE Standard
1149.1-1990; the standard (public) instructions and device
specific (private) instructions. Some public instructions are
mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows IEEE 1149.1
conventions, it is not IEEE 1149.1-compliant because some of
the mandatory instructions are not fully implemented. The TAP
on this device may be used to monitor all input and I/O pads,
but can not be used to load address, data, or control signals
into the device or to preload the I/O buffers. In other words, the
device will not perform IEEE 1149.1 EXTEST, INTEST, or the
preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
Document #: 38-05258 Rev. *C
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
Page 12 of 28
CY7C1360A
CY7C1362A
1
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05258 Rev. *C
Page 13 of 28
CY7C1360A
CY7C1362A
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register [12]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Min.
Max.
Unit
VIH
Input High (Logic 1)
Voltage[13, 14]
2.0
VCC + 0.3
V
VIl
Input Low (Logic 0) Voltage[13, 14]
–0.3
0.8
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[13, 15]
IOLC = 100 µA
0.2
V
VOHC
Voltage[13, 15]
IOHC = 100 µA
LVCMOS Output High
Test Conditions
VOLT
LVTTL Output Low
Voltage[13]
IOLT = 8.0 mA
VOHT
LVTTL Output High Voltage[13]
IOHT = 8.0 mA
VCC – 0.2
V
0.4
2.4
V
V
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All voltage referenced to VSS (GND).
14. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) < – 0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for
t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than
tKHKL (min.).
15. This parameter is sampled.
Document #: 38-05258 Rev. *C
Page 14 of 28
CY7C1360A
CY7C1362A
TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter
Description
Min.
Max.
Unit
Clock
tTHTH
Clock Cycle Time
20
ns
fTF
Clock Frequency
tTHTL
Clock HIGH Time
8
ns
tTLTH
Clock LOW Time
8
ns
tTLQX
TCK LOW to TDO Unknown
0
ns
tTLQV
TCK LOW to TDO Valid
tDVTH
TDI Valid to TCK HIGH
5
ns
tTHDX
TCK HIGH to TDI Invalid
5
ns
tMVTH
TMS Set-up
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up
5
ns
tTHMX
TMS Hold
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold
5
ns
50
MHz
Output Times
10
ns
Set-up Times
Hold Times
Notes:
16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC test conditions.
TAP Timing and Test Conditions
ALL INPUT PULSES
TDO
Z0 = 50Ω
50Ω
50
Ω
50Ω
3.0V
20 pF
1.5V
VSS
Vt = 1.5V
1.5 ns
1.5 ns
(b)
(a)
t
tTHTH
THTL
t
TLTH
TEST CLOCK
(TCK)
tMVTH
tTHMX
tDVTH
tTHDX
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
t
t
TLQV
TLQX
TEST DATA OUT
(TDO)
Document #: 38-05258 Rev. *C
Page 15 of 28
CY7C1360A
CY7C1362A
Identification Register Definitions
Instruction Field
256K × 36
512K × 18
Revision Number (31:28)
XXXX
XXXX
Reserved for revision number.
Device Depth (27:23)
00110
00111
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Device Width (22:18)
Reserved (17:12)
Cypress JEDEC ID Code (11:1)
00100
00011
XXXXXX
XXXXXX
00011100100
00011100100
1
1
ID Register Presence Indicator (0)
Description
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan
70
51
Instruction Codes
Code
Description
EXTEST
Instruction
000
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all device outputs to High-Z state. This instruction is
not IEEE 1149.1-compliant.
IDCODE
001
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
010
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all device outputs to High-Z state.
RESERVED
011
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. This instruction does not affect device operations. This
instruction does not implement IEEE 1149.1 PRELOAD function and is
therefore not 1149.1-compliant.
RESERVED
101
Do not use these instructions; they are reserved for future use.
RESERVED
110
Do not use these instructions; they are reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This instruction does
not affect device operations.
Document #: 38-05258 Rev. *C
Page 16 of 28
CY7C1360A
CY7C1362A
Boundary Scan Order (256K × 36) (continued)
Boundary Scan Order (256K × 36)
Bit#
Signal Name
TQFP
Bump ID
Bit#
1
A
44
2R
36
Signal Name
TQFP
Bump ID
A
92
6B
BWa
93
5L
2
A
45
3T
37
3
A
46
4T
38
BWb
94
5G
BWc
95
3G
4
A
47
5T
39
5
A
48
6R
40
BWd
96
3L
CE2
97
2B
6
A
49
3B
41
7
A
50
5B
42
CE
98
4E
A
99
3A
8
DQa
51
6P
43
9
DQa
52
7N
44
A
100
2A
DQc
1
2D
10
DQa
53
6M
45
11
DQa
56
7L
46
DQc
2
1E
DQc
3
2F
12
DQa
57
6K
47
13
DQa
58
7P
48
DQc
6
1G
DQc
7
2H
14
DQa
59
6N
49
15
DQa
62
6L
50
DQc
8
1D
DQc
9
2E
16
DQa
63
7K
51
17
ZZ
64
7T
52
DQc
12
2G
DQc
13
1H
18
DQb
68
6H
53
19
DQb
69
7G
54
NC
14
5R
DQd
18
2K
20
DQb
72
6F
55
21
DQb
73
7E
56
DQd
19
1L
DQd
22
2M
22
DQb
74
6D
57
23
DQb
75
7H
58
DQd
23
1N
DQd
24
2P
24
DQb
78
6G
59
25
DQb
79
6E
60
DQd
25
1K
DQd
28
2L
26
DQb
80
7D
61
27
A
81
6A
62
DQd
29
2N
DQd
30
1P
28
A
82
5A
63
29
ADV
83
4G
64
MODE
31
3R
A
32
2C
30
ADSP
84
4A
65
31
ADSC
85
4B
66
A
33
3C
A
34
5C
32
OE
86
4F
67
33
BWE
87
4M
68
A
35
6C
A1
36
4N
A0
37
4P
34
GW
88
4H
69
35
CLK
89
4K
70
Document #: 38-05258 Rev. *C
Page 17 of 28
CY7C1360A
CY7C1362A
Boundary Scan Order (512K × 18) (continued)
Boundary Scan Order (512K × 18)
Bit#
Signal Name
TQFP
Bump ID
Bit#
Signal Name
TQFP
Bump ID
1
A
44
2R
27
CLK
89
4K
A
92
6B
2
A
45
2T
28
3
A
46
3T
29
BWa
93
5L
BWb
94
3G
4
A
47
5T
30
5
A
48
6R
31
CE2
97
2B
CE
98
4E
6
A
49
3B
32
7
A
50
5B
33
A
99
3A
A
100
2A
8
DQa
58
7P
34
9
DQa
59
6N
35
DQb
8
1D
DQb
9
2E
10
DQa
62
6L
36
11
DQa
63
7K
37
DQb
12
2G
DQb
13
1H
12
ZZ
64
7T
38
13
DQa
68
6H
39
NC
14
5R
DQb
18
2K
14
DQa
69
7G
40
15
DQa
72
6F
41
DQb
19
1L
DQb
22
2M
16
DQa
73
7E
42
17
DQa
74
6D
43
DQb
23
1N
DQb
24
2P
18
A
80
6T
44
19
A
81
6A
45
MODE
31
3R
A
32
2C
20
A
82
5A
46
21
ADV
83
4G
47
A
33
3C
A
34
5C
22
ADSP
84
4A
48
23
ADSC
85
4B
49
A
35
6C
A1
36
4N
A0
37
4P
24
OE
86
4F
50
25
BWE
87
4M
51
26
GW
88
4H
Document #: 38-05258 Rev. *C
Page 18 of 28
CY7C1360A
CY7C1362A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Voltage on VCC Supply Relative to VSS[19] .... –0.5V to +4.6V
VIN ................................................................... –0.5V to 5.5V
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
Power Dissipation .........................................................1.0W
Short Circuit Output Current ........................................ 50 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature[18]
0°C to +70°C
–40°C to +85°C
VCC[19,20,21]
VCCQ
3.3V
−5/+10%
2.5V – 5/
3.3V + 10%
Electrical Characteristics Over the Operating Range
Parameter
VIHD
VIH
VIL
ILI
ILI
ILO
VOH
VOL
VCC[19]
VCCQ
Description
Input High (Logic 1) Voltage[13, 22]
Test Conditions
All other inputs
3.3V I/O
2.5V I/O
3.3V I/O
Input Low (Logic 0) Voltage[13, 22]
2.5V I/O
Input Leakage Current
0V < VIN < VCC
MODE and ZZ Input Leakage Current[23] 0V < VIN < VCC
Output Leakage Current
Output(s) disabled, 0V < VOUT < VCC
Output High Voltage[13]
IOH = –5.0 mA for 3.3V I/O
IOH = –1.0 mA for 2.5V I/O
Output Low Voltage[13]
IOL = 8.0 mA for 3.3V I/O
IOL = 1.0 mA for 2.5V I/O
Supply Voltage[13]
I/O Supply Voltage[13]
3.3V I/O
2.5V I/O
Parameter
Description
ICC
VCC Operating Supply[24, 25, 26]
ISB1
Automatic CE Power-down
Current—TTL Inputs[25, 26]
ISB2
Automatic CE Power-down
Current—CMOS Inputs[25, 26]
ISB3
Automatic CE Power-down
Current—
CMOS Inputs
Automatic CS Power-down
Current—TTL Inputs[25, 26]
ISB4
Min.
2.0
2.0
1.7
–0.3
–0.3
2.4
2.0
3.135
3.135
2.375
225
Conditions
Typ. MHz
Device selected; all inputs < VILor > VIH; 150 650
VCC = Max.;
outputs open, f = f MAX = 1/tcyc.
150 250
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
f = f MAX = 1/tcyc.
5
30
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or > VCC – 0.2;
all inputs static; CLK frequency = 0
Max. VDD Device Deselected, or V IN < 90 260
0.3V or VIN > VDDQ — 0.3V
f = f MAX = 1/t CYC
15
30
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = Max. CLK frequency = 0
Max.
VCC + 0.3
0.8
0.7
5
30
5
0.4
0.4
3.63
3.63
2.9
Unit
V
V
V
V
V
µA
µA
µA
V
V
V
V
V
V
V
Max.
200 166
MHz MHz
600 520
150
MHz Unit
460 mA
230
220
190
mA
30
30
30
mA
230
200
180
mA
30
30
30
mA
Capacitance[15]
Parameter
CI
CI/O
Description
Test Conditions
Input Capacitance
TA = 25°C, f = 1 MHz,
Input/Output Capacitance (DQ) VCC = 3.3V
Typ.
5
7
Max.
7
8
Unit
pF
pF
Notes:
18. TA is the case temperature.
19. The ground level at the start of “power on” on the VCC pins should be no greater than 200mV.
20. Please refer to waveform (d).
21. Power supply ramp up should be monotonic.
22. Overshoot: VIH < + 6.0V for t < tKC /2; undershoot:VIL < –2.0V for t < tKC /2.
23. Output loading is specified with CL=5 pF as in AC Test Loads.
24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
25. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
Document #: 38-05258 Rev. *C
Page 19 of 28
CY7C1360A
CY7C1362A
Thermal Resistance[15]
Parameter
Description
ΘJA
Test Conditions
TQFP Typ.
Unit
25
°C/W
9
°C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
4-layer PCB
Thermal Resistance (Junction to Case)
ΘJC
AC Test Loads and Waveforms
tPU = 200us
OUTPUT
R = 317Ω
VCCQ
Z0 = 50Ω
RL = 50ΩOUTPUT
ALL INPUT PULSES
VCCQ
10%
GND
5 pF
R = 351Ω
VTH = 1.5V
Vcctyp
Vccmin
For proper RESET
bring Vcc down to 0V
≤ 1 V/ns
≤ 1 V/ns
(c)
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
(d)
(b)
Switching Characteristics Over the Operating Range[27]
225 MHz
Parameter
Description
Min.
Max.
200 MHz
Min.
Max.
166 MHz
Min.
Max.
150 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
4.4
5.0
6.0
6.7
ns
tKH
Clock HIGH Time
1.8
2.0
2.4
2.6
ns
tKL
Clock LOW Time
1.8
2.0
2.4
2.6
ns
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
2.8
3.1
3.5
3.5
ns
VCCQ = 2.5V
2.8
3.1
4.0
4.5
ns
tKQX
Clock to Output Invalid
tKQLZ
Clock to Output in Low-Z[15, 22, 28]
tKQHZ
High-Z[15, 22, 28]
Clock to Output in
Valid[29]
tOEQ
OE to Output
tOELZ
OE to Output in Low-Z[15, 22, 28]
tOEHZ
High-Z[15, 22, 28]
1.25
1.25
1.25
1.25
ns
0
0
0
0
ns
1.25
VCCQ = 3.3V
1.25
2.8
VCCQ = 2.5V
OE to Output in
3.0
1.0
3.0
2.8
0
2.6
2.8
1.25
3.5
3.0
0
2.8
4.0
0
3.0
4.0
ns
3.5
ns
4.5
ns
0
3.5
ns
3.5
ns
Set-up Times
tS
Address, Controls, and Data In[30]
1.4
1.4
1.5
2.0
ns
Address, Controls, and Data In[30]
0.4
0.4
0.5
0.5
ns
Hold Times
tH
Notes:
26. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
29. OE is a “Don’t Care” when a byte Write enable is sampled LOW.
30. This is a synchronous device. All synchronous inputs must meet specified set up and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05258 Rev. *C
Page 20 of 28
CY7C1360A
CY7C1362A
Switching Waveforms
Read Timing[31, 32]
tKC
tKL
CLK
CLK
tS
tKH
ADSP
ADSP
tH
ADSC
ADSC
tS
A
ADDRESS
A1
Wa, BW
b,
BWx
BWc, BW
d
BWE
BWE,GW
GW
A2
tH
tS
CE
CE
tS
ADV
ADV
tH
OE
OE
tKQ
DQx
DQ
tKQLZ
tOELZ
Q(A1)
SINGLE READ
tOEQ
tKQ
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
BURST READ
Notes:
31. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
32. For the X18 product, there are only BWa and BWb for byte Write control.
Document #: 38-05258 Rev. *C
Page 21 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
Write Timing[31, 32]
CLK
CLK
tS
ADSP
ADSP
tH
ADSC
ADSC
tS
A
ADDRESS
A1
A2
A3
tH
BWa, BWb,
BWd,
BWc, BW
x
BWE
BWE
Chan
GW
GW
CECE
tS
ADV
ADV
tH
OE
OE
tOEHZ
tKQX
DQx
DQ
Q
D(A1)
SINGLE WRITE
Document #: 38-05258 Rev. *C
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
BURST WRITE
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
BURST WRITE
Page 22 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
Read/Write Timing[31, 32]
CLK
CLK
tS
ADSP
ADSP
tH
ADSC
ADSC
tS
A
ADDRESS
A1
A2
BWa, BW
BWxb,
BWc,BWE
BWd,
GW
BWE, GW
A3
A4
A5
tH
CE
CE
ADV
ADV
OEOE
DQx
DQ
Q(A1)
Single Reads
Document #: 38-05258 Rev. *C
Q(A2)
D(A3)
Single Write
Q(A4)
Q(A4+1)
Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Page 23 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
ZZ Mode Timing[33, 34]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Notes:
33. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
34. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05258 Rev. *C
Page 24 of 28
CY7C1360A
CY7C1362A
Ordering Information
Speed
(MHz)
225
Ordering Code
CY7C1360A-225AJC
CY7C1360A-225AC
200
166
225
166
150
166
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1360A-200BGC
BG119
CY7C1360A-166AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-166BGC
BG119
CY7C1360A-150AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-150AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1360A-150BGC
BG119
CY7C1362A-225AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-225BGC
BG119
CY7C1362A-200AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-200AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1362A-166AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-166BGC
BG119
CY7C1362A-150AJC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-150AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-200AJI
BG119
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-200BGI
BG119
CY7C1360A-166AJI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-166AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1360A-150AJI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-150BGI
BG119
CY7C1362A-200AJI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-200AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1362A-200BGI
BG119
CY7C1362A-166AJI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1362A-150AJI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1362A-150AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Document #: 38-05258 Rev. *C
Industrial
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1362A-166BGI
BG119
Industrial
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1360A-166BGI
CY7C1362A-150BGI
Commercial
119-Lead BGA (14 x 22 x 2.4 mm)
CY7C1362A-200BGC
CY7C1362A-166AI
150
A101
A101
CY7C1360A-150AI
200
Commercial
A101
CY7C1360A-200AI
166
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1360A-200AC
CY7C1362A-150BGC
200
A101
CY7C1360A-200AJC
CY7C1362A-166AC
150
Operating
Range
BG119
CY7C1362A-225AC
200
Package Type
CY7C1360A-225BGC
CY7C1360A-166AC
150
Package
Name
119-Lead BGA (14 x 22 x 2.4 mm)
119-Lead BGA (14 x 22 x 2.4 mm)
Page 25 of 28
CY7C1360A
CY7C1362A
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05258 Rev. *C
Page 26 of 28
CY7C1360A
CY7C1362A
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-05258 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1360A
CY7C1362A
Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
Document Number: 38-05258
REV
ECN No.
Issue
Date
Orig. of
Change
Description of Change
**
113846
05/22/02
GLC
Change from Spec.: 38-00990 to 38-05258
*A
116062
05/28/02
BRI
Removed GVT part numbers from title and body of data sheet
Added note 19 (pg. 19) regarding VCC on “Power On”
*B
116765
09/09/02
BRI
Updated package type names on page 3
ICC, ISB3, and ISB4 values corrected on page 19
*C
123144
01/18/03
RBI
Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.
Document #: 38-05258 Rev. *C
Page 28 of 28
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