CY7C1361A
CY7C1363A
256K x 36/512K x 18 Synchronous
Flow-Thru Burst SRAM
Features
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Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
Fast clock speed: 150, 133, 117, and 100 MHz
Fast OE access times: 3.5 ns and 4.0 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion: A package
version and two chip enables for BGA and AJ package
versions
Address pipeline capability
Address, data, and control registers
Internally self-timed Write cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down feature available using ZZ
mode or CE deselect.
JTAG boundary scan for BG and AJ package version
Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1361A and CY7C1363A SRAMs integrate 262,144
× 36 and 524,288 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE2 and CE2), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE2 chip enable
input is only available for the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the TQFP AJ and the BGA package versions, four pins are
used to implement JTAG test capabilities: Test Mode Select
(TMS), Test Data-In (TDI), Test Clock (TCK), and Test
Data-Out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation. The
TA package version does not offer the JTAG capability.
The CY7C1361A and CY7C1363A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
Selection Guide
7C1361A-150
7C1363A-150
7C1361A-133
7C1363A-133
7C1361A-117
7C1363A-117
7C1361A-100
7C1363A-100
Unit
Maximum Access Time
6.0
6.5
7.0
8.0
ns
Maximum Operating Current
480
360
320
270
mA
Maximum CMOS Standby Current
10
10
10
10
mA
Cypress Semiconductor Corporation
Document #: 38-05259 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1361A
CY7C1363A
Functional Block Diagram–256K × 36[1]
BYTE a WRITE
BWa
BWE
D
Q
CLK
BYTE b WRITE
BWb
D
Q
GW
BYTE c WRITE
BWc
D
Q
BYTE d WRITE
ENABLE
D
CE2
Q
D
Q
byte b write
byte a write
CE
Q
byte c write
D
byte d write
BWd
[2] CE2
OE
Power Down Logic
Input
Register
ADSP
A
16
Address
Register
CLR
ADV
OUTPUT
REGISTER
256K x 9 x 4
SRAM Array
ADSC
D
Output Buffers
ZZ
Q
Binary
Counter
& Logic
A1-A0
DQa,DQb
DQc,DQd
MODE
Functional Block Diagram—512K × 18[1]
BYTE b
WRITE
BWb
BWE
D
Q
BYTE a
WRITE
BWa
D
Q
ENABLE
D
CE2
Q
D
Q
[2]CE2
ZZ
byte b write
CE
byte a write
GW
Power Down Logic
OE
ADSP
Input
Register
17
ADSC
CLR
ADV
A1-A0
Binary
Counter
& Logic
OUTPUT
REGISTER
D
Q
Output Buffers
Address
Register
512K x 9 x 2
SRAM Array
A
DQa,DQb
MODE
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2. CE2 is for A version only.
Document #: 38-05259 Rev. *C
Page 2 of 27
CY7C1361A
CY7C1363A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100-pin TQFP
AJ Version
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100-pin TQFP
A Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
CY7C1361A
256K × 36 100-pin TQFP
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
100-pin TQFP
A Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VCC
NC
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Document #: 38-05259 Rev. *C
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
VCC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
AJ Version
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VCCQ
VSS
NC
DPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
CE2
NC
NC
BWb
BWa
A
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
CY7C1363A
512Kx18 100-Pin TQFP
Page 3 of 27
CY7C1361A
CY7C1363A
Pin Configurations (continued)
CY7C1361A
256K × 36 119-ball BGA
Top View
1
2
3
4
5
6
7
A
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1363A 512K × 18 119-ball BGA Top View
A
1
2
3
4
5
6
7
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
CE2
NC
C
NC
A
A
VCC
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQa
NC
E
NC
DQb
VSS
CE
VSS
NC
DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
ADV
VSS
NC
DQa
H
DQb
NC
VSS
GW
VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
BWE
VSS
NC
VCCQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05259 Rev. *C
Page 4 of 27
CY7C1361A
CY7C1363A
256K × 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 5B, 35, 34, 33, 32, 100,
6B, 2C, 3C, 5C, 6C, 99, 82, 81, 44, 45,
2R, 6R, 3T, 4T, 5T
46, 47, 48, 49, 50
92 (AJ Version)
43 (A Version)
Pin
Name
Type
Pin Description
A0
A1
A
InputSynchronous
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write: A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
2B
97
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable
the device.
–
(not available for
PBGA)
92
(for A version only)
CE2
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
4G
83
ADV
InputSynchronous
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
4A
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
7T
64
ZZ
Document #: 38-05259 Rev. *C
InputSleep: This active HIGH input puts the device in
Asynchronous low-power consumption standby mode. For normal
operation, this input has to be either LOW or NC (No
Connect).
Page 5 of 27
CY7C1361A
CY7C1363A
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
(a) 6P, 7P, 7N, 6N, 6M,
6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G, 6F,
6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E, 2F,
1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L, 2M,
1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9,
12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
2U
3U
4U
Pin
Name
Type
Pin Description
DQa
DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
38
39
43
for BG and AJ
version
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not
available for A package version.
5U
42
for BG and AJ
version
TDO
Output
IEEE 1149.1 Test Output: LVTTL-level output. Not
available for A package version.
4C, 2J, 4J, 6J, 4R
15, 41, 65, 91
VCC
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26,
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,
5M, 3N, 5N, 3P, 5P
76, 90
Power Supply Core Power Supply: +3.3V – 5% and +10%
VSS
Ground
1A, 7A, 1F, 7F, 1J, 7J,
1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
VCCQ
I/O Power
Supply
1B, 7B, 1C, 7C, 4D, 3J,
5J, 4L, 1R, 5R, 7R, 1T,
2T, 6T, 6U
14, 16, 66
38, 39, 42 for A
version
NC
–
Ground: GND.
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
512K × 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32, 100,
5B, 6B, 2C, 3C, 5C, 99, 82, 81, 80, 48,
6C, 2R, 6R, 2T, 3T, 5T, 47, 46, 45, 44, 49,
6T
50
92 (AJ Version)
43 (A Version)
Pin
Name
Type
Pin Description
A0
A1
A
InputSynchronous
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
5L
3G
93
94
BWa
BWb
InputSynchronous
Byte Write Enables: A byte Write enable is LOW for a
Write cycle and HIGH for a Read cycle. BWa controls DQa.
BWb controls DQb. Data I/O are high impedance if either
of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 18-bit
Write to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip
enables, Write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Document #: 38-05259 Rev. *C
Page 6 of 27
CY7C1361A
CY7C1363A
512K × 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins
Pin
Name
2B
97
–
(not available for
PBGA)
Type
Pin Description
CE2
InputSynchronous
Chip Enable: This active HIGH input is used to enable the
device.
92
(for A Version only)
CE2
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
4G
83
ADV
InputSynchronous
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
4A
84
ADSP
InputSynchronous
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to be
registered and a Read cycle is initiated using the new
address.
4B
85
ADSC
InputSynchronous
Address Status Controller: This active LOW input
causes device to be deselected or selected along with new
external address to be registered. A Read or Write cycle
is initiated depending upon Write control inputs.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. An NC or HIGH on this pin
selects Interleaved Burst.
7T
64
ZZ
(a) 6D, 7E, 6F, 7G, 6H, (a) 58, 59, 62, 63,
7K, 6L, 6N, 7P
68, 69, 72, 73, 74
(b) 1D, 2E, 2G, 1H, (b) 8, 9, 12, 13, 18,
2K, 1L, 2M, 1N, 2P
19, 22, 23, 24
InputSleep: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this
input has to be either LOW or NC (No Connect).
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set-up and hold times around the
rising edge of CLK.
2U
3U
4U
38
39
43
for BG and AJ
version
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not
available for A package version.
5U
42
for BG and AJ
version
TDO
Output
IEEE 1149.1 Test Output: LVTTL-level output. Not
available for A package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Core Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F,
5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N,
5N, 3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
VSS
Ground
Ground: GND.
1A, 7A, 1F, 7F, 1J, 7J,
1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
VCCQ
I/O Power
Supply
1B, 7B, 1C, 7C, 2D, 1–3, 6, 7, 14, 16,
4D, 7D, 1E, 6E, 2F, 25, 28–30, 51–53,
1G, 6G, 2H, 7H, 3J, 56, 57, 66, 75, 78,
5J, 1K, 6K, 2L, 4L, 7L,
79, 80, 95, 96
6M, 2N, 7N, 1P, 6P,
38, 39, 42 for A
1R, 5R, 7R, 1T, 4T, 6U
Version
NC
–
Document #: 38-05259 Rev. *C
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
Page 7 of 27
CY7C1361A
CY7C1363A
Burst Address Table (MODE = NC/VCC)
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A11
A...A00
A...A01
A...A10
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE CE2 CE2 ADSP ADSC ADV
Write
OE
CLK
DQ
Deselected Cycle, Power-down None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down None
L
H
X
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.l
7. For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05259 Rev. *C
Page 8 of 27
CY7C1361A
CY7C1363A
Partial Truth Table for Read/Write[10]
GW
BWE
BWa
BWb
BWc
BWd
Read
Function
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write one byte
H
L
L
H
H
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
Min.
2tCYC
Max.
Unit
10
mA
2tCYC
ns
ns
Note:
10. For the X18 product, there are only BWa and BWb.
Document #: 38-05259 Rev. *C
Page 9 of 27
CY7C1361A
CY7C1363A
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan test access
port (TAP). This port is designed to operate in a manner
consistent with IEEE Standard 1149.1-1990 (commonly
referred to as JTAG), but does not implement all of the
functions required for IEEE 1149.1 compliance. Certain
functions have been modified or eliminated because their
implementation places extra delays in the critical speed path
of the device. Nevertheless, the device supports the standard
TAP controller architecture (the TAP controller is the state
machine that controls the TAPs operation) and can be
expected to function in a manner that does not conflict with the
operation of devices with IEEE Standard 1149.1 compliant
TAPs. The TAP operates using LVTTL/ LVCMOS logic level
signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port
TCK—Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS—Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI—Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1, TAP Controller State Diagram). It is
allowable to leave this pin unconnected if it is not used in an
application. The pin is pulled up internally, resulting in a logic
HIGH level. TDI is connected to the Most Significant Bit (MSB)
of any register (see Figure 2).
TDO—Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Significant Bit (LSB) of any register (see Figure 2).
Document #: 38-05259 Rev. *C
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TAP Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for the x36 device and
51 bits for the x18 device. The boundary scan register, under
the control of the TAP controller, is loaded with the contents of
the device I/O ring when the controller is in Capture-DR state
and then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Page 10 of 27
CY7C1361A
CY7C1363A
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1-compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Document #: 38-05259 Rev. *C
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set-up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
Page 11 of 27
CY7C1361A
CY7C1363A
1
0
TEST-LOGIC
RESET
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05259 Rev. *C
Page 12 of 27
CY7C1361A
CY7C1363A
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register[12]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Min.
Max.
Unit
VIH
Input High (Logic 1)
Voltage[13, 14]
Test Conditions
2.0
VCC + 0.3
V
VIl
Input Low (Logic 0) Voltage[13, 14]
–0.3
0.8
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[13, 15]
IOLC = 100 µA
0.2
V
VOHC
LVCMOS Output High Voltage[13, 15]
IOHC = 100 µA
VOLT
LVTTL Output Low
Voltage[13]
IOLT = 8.0 mA
VOHT
LVTTL Output High Voltage[13]
IOHT = 8.0 mA
VCC – 0.2
V
0.4
2.4
V
V
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All Voltage referenced to VSS (GND).
14. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) < – 0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for
t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD) may not have pulse widths less than tKHKL (min.).
15. This parameter is sampled.
Document #: 38-05259 Rev. *C
Page 13 of 27
CY7C1361A
CY7C1363A
TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter
Description
Min.
Max.
Unit
Clock
tTHTH
Clock Cycle Time
20
ns
fTF
Clock Frequency
tTHTL
Clock HIGH Time
8
ns
tTLTH
Clock LOW Time
8
ns
tTLQX
TCK LOW to TDO Unknown
0
tTLQV
TCK LOW to TDO Valid
tDVTH
TDI Valid to TCK HIGH
5
ns
tTHDX
TCK HIGH to TDI Invalid
5
ns
tMVTH
TMS Set-up
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up
5
ns
tTHMX
TMS Hold
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold
5
ns
50
MHz
Output Times
ns
10
ns
Set-up Times
Hold Times
TAP Timing and Test Conditions
ALL INPUT PULSES
TDO
Z0 = 50 Ω
50 Ω
3.0V
20 pF
1.5V
VSS
Vt = 1.5V
1.5 ns
1.5 ns
(b)
(a)
t
tTHTH
THTL
t
TLTH
TEST CLOCK
(TCK)
tMVTH
tTHMX
tDVTH
tTHDX
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
tTLQV
tTLQX
TEST DATA OUT
(TDO)
Notes:
16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC test conditions.
Document #: 38-05259 Rev. *C
Page 14 of 27
CY7C1361A
CY7C1363A
Identification Register Definitions
Instruction Field
256K x 36
512K x 18
Revision Number (31:28)
XXXX
XXXX
Reserved for revision number.
Device Depth (27:23)
00110
00111
Defines depth of 256K or 512K words.
00100
00011
Defines width of x36 or x18 bits.
XXXXXX
XXXXXX
Device Width (22:18)
Reserved (17:12)
Cypress Jedec ID Code (11:1)
00011100100
ID Register Presence Indicator (0)
1
Description
Reserved for future use.
00011100100 Allows unique identification of device vendor.
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan
70
51
Instruction Codes
Code
Description
EXTEST
Instruction
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
010
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
101
Do not use these instructions; they are reserved for future use.
RESERVED
110
Do not use these instructions; they are reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This instruction does
not affect device operations.
Document #: 38-05259 Rev. *C
Page 15 of 27
CY7C1361A
CY7C1363A
Boundary Scan Order (256K × 36) (continued)
Boundary Scan Order (256K × 36)
Bit#
Signal Name
TQFP
Bump ID
Bit#
Signal Name
TQFP
Bump ID
A
92
6B
1
A
44
2R
36
2
A
45
3T
37
BWa
93
5L
BWb
94
5G
3
A
46
4T
38
4
A
47
5T
39
BWc
95
3G
BWd
96
3L
5
A
48
6R
40
6
A
49
3B
41
CE2
97
2B
CE
98
4E
7
A
50
5B
42
8
DQa
51
6P
43
A
99
3A
A
100
2A
9
DQa
52
7N
44
10
DQa
53
6M
45
DQc
1
2D
DQc
2
1E
11
DQa
56
7L
46
12
DQa
57
6K
47
DQc
3
2F
DQc
6
1G
13
DQa
58
7P
48
14
DQa
59
6N
49
DQc
7
2H
DQc
8
1D
15
DQa
62
6L
50
16
DQa
63
7K
51
DQc
9
2E
DQc
12
2G
17
ZZ
64
7T
52
18
DQb
68
6H
53
DQc
13
1H
NC
14
5R
19
DQb
69
7G
54
20
DQb
72
6F
55
DQd
18
2K
DQd
19
1L
21
DQb
73
7E
56
22
DQb
74
6D
57
DQd
22
2M
DQd
23
1N
23
DQb
75
7H
58
24
DQb
78
6G
59
DQd
24
2P
DQd
25
1K
25
DQb
79
6E
60
26
DQb
80
7D
61
DQd
28
2L
DQd
29
2N
27
A
81
6A
62
28
A
82
5A
63
DQd
30
1P
MODE
31
3R
29
ADV
83
4G
64
30
ADSP
84
4A
65
A
32
2C
A
33
3C
31
ADSC
85
4B
66
32
OE
86
4F
67
A
34
5C
A
35
6C
33
BWE
87
4M
68
34
GW
88
4H
69
A1
36
4N
4K
70
A0
37
4P
35
CLK
Document #: 38-05259 Rev. *C
89
Page 16 of 27
CY7C1361A
CY7C1363A
Boundary Scan Order (512K × 18) (continued)
Boundary Scan Order (512K × 18)
Bit#
Signal Name
TQFP
Bump ID
Bit#
Signal Name
TQFP
Bump ID
CLK
89
4K
1
A
44
2R
27
2
A
45
2T
28
A
92
6B
BWa
93
5L
3
A
46
3T
29
4
A
47
5T
30
BWb
94
3G
CE2
97
2B
5
A
48
6R
31
6
A
49
3B
32
CE
98
4E
A
99
3A
7
A
50
5B
33
8
DQa
58
7P
34
A
100
2A
DQb
8
1D
9
DQa
59
6N
35
10
DQa
62
6L
36
DQb
9
2E
DQb
12
2G
11
DQa
63
7K
37
12
ZZ
64
7T
38
DQb
13
1H
NC
14
5R
13
DQa
68
6H
39
14
DQa
69
7G
40
DQb
18
2K
DQb
19
1L
15
DQa
72
6F
41
16
DQa
73
7E
42
DQb
22
2M
DQb
23
1N
17
DQa
74
6D
43
18
A
80
6T
44
DQb
24
2P
MODE
31
3R
19
A
81
6A
45
20
A
82
5A
46
A
32
2C
A
33
3C
21
ADV
83
4G
47
22
ADSP
84
4A
48
A
34
5C
A
35
6C
23
ADSC
85
4B
49
24
OE
86
4F
50
A1
36
4N
51
A0
37
4P
25
BWE
87
4M
26
GW
88
4H
Document #: 38-05259 Rev. *C
Page 17 of 27
CY7C1361A
CY7C1363A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Voltage on VCC Supply Relative to VSS[19] .... –0.5V to +4.6V
VIN ......................................................... –0.5V to VCC + 0.5V
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
Power Dissipation .........................................................1.0W
Short Circuit Output Current ........................................ 50 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range
Temperature[18]
Commercial 0°C to +70°C
Industrial
–40°C to +85°C
VCC[19,20,21]
VCCQ
3.3V–5/
+10%
2.5V–5/
3.3V+10%
Electrical Characteristics Over the Operating Range
Parameter
VIHD
Description
Input High (Logic 1) Voltage[13, 21]
VIH
VIL
Input Low (Logic 0)
Voltage[13, 21]
Min.
Max.
Unit
All other inputs
Test Conditions
2.0
VCC5 + 0.5
V
3.3V I/O
2.0
V
2.5V I/O
1.7
V
3.3V I/O
–0.3
0.8
V
2.5V I/O
–0.3
0.7
V
5
µA
–
30
µA
–
5
µA
ILI
Input Leakage Current
ILI
MODE and ZZ Input Leakage Current[23] 0V < VIN < VCC
0V < VIN < VCC
ILO
Output Leakage Current
Output(s) disabled, 0V < VOUT < VCC
VOH
Output High Voltage[13]
IOH = –5.0 mA for 3.3V I/O
2.4
IOH = –1.0 mA for 2.5V I/O
2.0
VOL
Output Low Voltage[13]
VCC[19]
Supply Voltage[13]
V
V
IOL = 8.0 mA for 3.3V I/O
IOL = 1.0 mA for 2.5V I/O
VCCQ
[13]
I/O Supply Voltage
0.4
V
0.4
V
3.135
3.63
V
3.3V I/O
3.135
3.63
V
2.5V I/O
2.375
2.9
V
Max.
150 133 117 100
Parameter
Description
Conditions
Typ. MHz MHz MHz MHz Unit
ICC
VCC Operating Supply[24, 25, 26] Device selected; all inputs < VILor > VIH; cycle 150 480 440 410 380 mA
time > tKC min.; VCC = Max.; outputs open
150 250 235 220 210 mA
Automatic CE
Device deselected;
ISB1
Power-down
all inputs < VIL or > VIH; VCC = Max.;
Current—TTL Inputs[25, 26]
CLK cycle time > tKC Min.
ISB2
5
10
10
10
10 mA
Automatic CE
Device deselected; VCC = Max.;
Power-down
all inputs < VSS + 0.2 or > VCC – 0.2;
Current—CMOS Inputs[25, 26] all inputs static; CLK frequency = 0
Automatic CE
Max. VDD Device Deselected, or V IN <
90 160 145 130 115 mA
ISB3
Power-down Current—
0.3V or VIN > VDDQ – 0.3V f = f MAX = 1/t CYC
CMOS Inputs
15
30
30
30
30 mA
Automatic CS
Device deselected; all inputs < VIL
ISB4
Power-down
or > VIH; all inputs static;
Current—TTL Inputs[25, 26]
VCC = Max. CLK frequency = 0
Capacitance[15]
Parameter
CI
CI/O
Description
Input Capacitance
Input/Output Capacitance (DQ)
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Typ.
5
7
Max.
7
8
Unit
pF
pF
Notes:
18. TA is the case temperature.
19. The ground level at the start of “power on” on the VCC pins should be no greater than 200 mV.
20. Please refer to waveform (d).
21. Power supply ramp up should be monotonic.
22. Overshoot: VIH < + 6.0V for t < tKC /2; undershoot: VIL < – 2.0V for t < tKC /2.
23. Output loading is specified with CL=5 pF as in AC Test Loads.
24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
25. “Device Deselected” means the device is in power-down mode as defined in the truth table. “Device Selected” means the device is active.
Document #: 38-05259 Rev. *C
Page 18 of 27
CY7C1361A
CY7C1363A
Thermal Resistance[15]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance (Junction to Ambient)
ΘJC
Thermal Resistance (Junction to Case)
TQFP Typ.
Unit
25
°C/W
9
°C/W
Still Air, soldered on a 4.25 × 1.125 inch,
4-layer PCB
AC Test Loads and Waveforms
t PU
OUTPUT
VCCQ
Z0 = 50Ω
RL = 50Ω
ALL INPUT PULSES
R = 317Ω
VCC
OUTPUT
10%
90%
10%
90%
GND
5 pF
VTH = 1.5V
R = 351Ω
INCLUDING
JIG AND
SCOPE
(a)
= 200us
Vcctyp
Vccmin
For proper RESET
bring Vcc down to 0V
≤ 1 V/ns
≤ 1 V/ns
(c)
(d)
(b)
Switching Characteristics Over the Operating Range[26]
150 MHz
Parameter
Description
Min.
Max.
133 MHz
Min.
Max.
117 MHz
Min.
Max.
100 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
6.7
7.5
8.5
10
ns
tKH
Clock HIGH Time
2.5
2.5
3.0
3.5
ns
tKL
Clock LOW Time
2.5
2.5
3.0
3.5
ns
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
6.0
6.5
7.0
8.0
ns
VCCQ = 2.5V
6.5
7.0
7.5
9.0
ns
tKQX
Clock to Output Invalid
2
2
2
2
ns
tKQLZ
Clock to Output in Low-Z[15, 23, 28]
0
0
0
0
ns
tKQHZ
Clock to Output in
High-Z[15, 23, 28]
2
tOEQ
OE to Output Valid[29]
tOELZ
OE to Output in Low-Z[15, 23, 28]
tOEHZ
High-Z[15, 23, 28]
VCCQ = 3.3V
2
3.5
VCCQ = 2.5V
OE to Output in
3.5
2
3.5
4.5
0
3.5
3.5
2
3.5
4.5
0
3.5
4.5
0
3.5
3.5
ns
4.0
ns
5.0
ns
0
3.5
ns
3.5
ns
Set-up Times
tS
Address, Controls, and Data In[30]
1.5
1.5
1.8
2.0
ns
Address, Controls, and Data In[30]
0.5
0.5
0.5
0.5
ns
Hold Times
tH
Notes:
26. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
29. OE is a “Don’t Care” when a byte Write enable is sampled LOW.
30. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05259 Rev. *C
Page 19 of 27
CY7C1361A
CY7C1363A
Switching Waveforms
Read Timing[31, 32]
tKC
tKL
CLK
tS
tKH
ADSP
tH
ADSC
tS
A1
ADDRESS
tH
BWa, BWb,
[29]
BWc, BWd, [31]
BWE, GW
CE
A2
[32]
[30]
tS
ADV
tH
OE
tKQ
DQ
tKQLZ
tOELZ
Q(A1)
SINGLE READ
tKQ
tOEQ
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2
BURST READ
Notes:
31. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for A package version.
32. For the X18 product, there are only BWa and BWb for byte Write control.
Document #: 38-05259 Rev. *C
Page 20 of 27
CY7C1361A
CY7C1363A
Switching Waveforms (continued)
Write Timing[31, 32]
CLK
tS
ADSP
tH
ADSC
tS
A1
ADDRESS
A2
A3
tH
BWa, BWb,
[29]
BWc, BWd, [31]
BWE
GW
[30]
CE [32]
tS
ADV
tH
OE
tKQX
DQ
Q
tOEHZ
D(A1)
SINGLE WRITE
Document #: 38-05259 Rev. *C
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
BURST WRITE
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
BURST WRITE
Page 21 of 27
CY7C1361A
CY7C1363A
Switching Waveforms (continued)
Read/Write Timing[31, 32]
CLK
tS
ADSP
tH
ADSC
tS
ADDRESS
A1
BWa, BWb,
[29]
BWc, BWd, [31]
BWE, GW
A2
A3
A4
A5
tH
[30]
CE [32]
ADV
OE
DQ
Q(A1)
Q(A2)
Single Reads
Document #: 38-05259 Rev. *C
D(A3)
Single Write
Q(A4)
Q(A4+1)
Q(A4+2)
Burst Read
Q(A4+3)
D(A5)
D(A5+1)
Burst Write
Page 22 of 27
CY7C1361A
CY7C1363A
Switching Waveforms (continued)
ZZ Mode Timing [33, 34]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Notes:
33. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
34. I/Os are in three-state when exiting ZZ sleep mode.
Ordering Information
Speed
(MHz)
150
Ordering Code
CY7C1361A-150AJC
CY7C1361A-150AC
133
117
Package Type
Operating
Range
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-150BGC
BG119
CY7C1361A-133AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-133AC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1361A-133BGC
BG119
CY7C1361A-117AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-117AC
100
Package
Name
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1361A-117BGC
BG119
CY7C1361A-100AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-100AC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-100BGC
Document #: 38-05259 Rev. *C
BG119
119-ball BGA (14 x 22 x 2.4 mm)
119-ball BGA (14 x 22 x 2.4 mm)
Page 23 of 27
CY7C1361A
CY7C1363A
Ordering Information (continued)
Speed
(MHz)
150
133
Package
Name
Package Type
Operating
Range
CY7C1363A-150AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1363A-150AC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Ordering Code
CY7C1363A-150BGC
BG119
CY7C1363A-133AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-133AC
117
100
CY7C1363A-133BGC
BG119
CY7C1363A-117AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-117AC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1363A-100AJC
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-100BGC
117
133
100
119-ball BGA (14 x 22 x 2.4 mm)
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-133AI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-133BGI
BG119
CY7C1361A-117AJI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1361A-100AJI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1361A-100AI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1361A-100BGI
BG119
CY7C1363A-133AJI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-133BGI
BG119
CY7C1363A-117AJI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-117AI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
BG119
CY7C1363A-100AJI
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1363A-100BGI
Document #: 38-05259 Rev. *C
BG119
Industrial temp
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1363A-117BGI
CY7C1363A-100AI
Industrial temp
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1361A-117BGI
CY7C1363A-133AI
117
BG119
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1361A-133AJI
CY7C1361A-117AI
100
119-ball BGA (14 x 22 x 2.4 mm)
CY7C1363A-117BGC
CY7C1363A-100AC
133
119-ball BGA (14 x 22 x 2.4 mm)
119-ball BGA (14 x 22 x 2.4 mm)
119-ball BGA (14 x 22 x 2.4 mm)
Page 24 of 27
CY7C1361A
CY7C1363A
Package Diagrams
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05259 Rev. *C
Page 25 of 27
CY7C1361A
CY7C1363A
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05259 Rev. *C
Page 26 of 27
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1361A
CY7C1363A
Document Title:CY7C1361A/CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
Document Number: 38-05259
REV
ECN No.
Issue
Date
Orig. of
Change
**
113847
05/17/02
GLC
New Data Sheet
*A
116225
06/20/02
BRI
Removed GVT part numbers from title and body of data sheet
Corrected CY part numbers in body of data sheet
Corrected the read and write timing diagrams
Added note 19 (pg. 19) regarding VCC on “Power On”
*B
117836
09/12/02
HGK
Changed B and T versions have JTAG to AJ and BGA versions on page 1
*C
123145
01/18/03
RBI
Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.
Document #: 38-05259 Rev. *C
Description of Change
Page 27 of 27
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