CY7C1370S
CY7C1372S
18-Mbit (512K × 36/1M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 200-MHz bus operations with zero wait states
❐ Available speed grades are 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
3.3 V core power supply (VDD)
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 3.0 ns (for 200-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Available in JEDEC-standard Pb-free 100-pin TQFP
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
The CY7C1370S and CY7C1372S are 3.3 V, 512K × 36 and
1M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370S and CY7C1372S are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370S and CY7C1372S are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370S and BWa–BWb for CY7C1372S)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Logic Block Diagram – CY7C1370S
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
MEMORY
ARRAY
WRITE
DRIVERS
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 001-43824 Rev. *H
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 23, 2016
CY7C1370S
CY7C1372S
Logic Block Diagram – CY7C1372S
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document Number: 001-43824 Rev. *H
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 2 of 19
CY7C1370S
CY7C1372S
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Write Cycle Description ....................................... 9
Partial Write Cycle Description ....................................... 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Document Number: 001-43824 Rev. *H
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 3 of 19
CY7C1370S
CY7C1372S
Selection Guide
Description
200 MHz
167 MHz
Unit
3.0
300
70
3.4
275
70
ns
mA
mA
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1372S
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(36)
NC(72)
A
A
A
A
A
A
A
NC(72)
NC(36)
VSS
VDD
NC(288)
NC(144)
MODE
A
A
A
A
A1
A0
Document Number: 001-43824 Rev. *H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VDD
(512K × 36)
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
V
DDQ
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC(288)
NC(144)
CY7C1370S
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 19
CY7C1370S
CY7C1372S
Pin Definitions
Pin Name
A0, A1, A
I/O Type
Pin Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous
BWa, BWb,
InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE defaults HIGH, to an interleaved burst order.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
VSS
NC
I/O power
supply
Ground
–
Power supply for the I/O circuitry.
Ground for the device. Must be connected to ground of the system.
No connects. This pin is not connected to the die.
Document Number: 001-43824 Rev. *H
Page 5 of 19
CY7C1370S
CY7C1372S
Pin Definitions (continued)
Pin Name
I/O Type
NC/(36M,
72M,
144M,
288M,
576M, 1G)
–
ZZ
Pin Description
These pins are not connected. They are used for expansion to the 36M, 72M, 144M, 288M, 576M,
and 1G densities.
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ
pin has an internal pull down.
Functional Overview
The CY7C1370S and CY7C1372S are synchronous-pipelined
burst NoBL SRAMs designed specifically to eliminate wait states
during write/read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the clock enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 3.0 ns (200-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0 ns (200-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output tri-states following the next clock rise.
Document Number: 001-43824 Rev. *H
Burst Read Accesses
The CY7C1370S and CY7C1372S have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370S and DQa,b/DQPa,b for
CY7C1372S). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370S and DQa,b/DQPa,b for
CY7C1372S) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370S and BWa,b for CY7C1372S) signals.
The CY7C1370S/CY7C1372S provides byte write capability that
is described in the Write Cycle Description table. Asserting the
write enable input (WE) with the selected byte write select (BW)
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
Page 6 of 19
CY7C1370S
CY7C1372S
sequences, which can be reduced to simple byte write
operations.
Interleaved Burst Address Table
Because the CY7C1370S and CY7C1372S are common I/O
devices, data must not be driven into the device while the outputs
are active. The output enable (OE) can be deasserted HIGH
before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d
for CY7C1370S and DQa,b/DQPa,b for CY7C1372S) inputs.
Doing so tri-states the output drivers. As a safety precaution, DQ
and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370S and
DQa,b/DQPa,b for CY7C1372S) are automatically tri-stated
during the data portion of a write cycle, regardless of the state of
OE.
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Burst Write Accesses
The CY7C1370S/CY7C1372S has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the section Single Write Accesses on
page 6. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BWa,b,c,d for CY7C1370S and BWa,b for CY7C1372S) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
Linear Burst Address Table
(MODE = GND)
Sleep Mode
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ VDD 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ VDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-43824 Rev. *H
Page 7 of 19
CY7C1370S
CY7C1372S
Truth Table
The truth table CY7C1370S and CY7C1372S follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
H
L
L
X
X
X
L
L–H
Tri-state
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Tri-state
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H Data out (Q)
Read cycle (continue burst)
Next
X
L
H
X
X
L
L
L–H Data out (Q)
NOP/dummy read (begin burst)
External
L
L
L
H
X
H
L
L–H
Tri-state
Dummy read (continue burst)
Next
X
L
H
X
X
H
L
L–H
Tri-state
Write cycle (begin burst)
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/write abort (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
Write abort (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Ignore clock edge (stall)
Current
X
L
X
X
X
X
H
L–H
–
Sleep mode
None
X
H
X
X
X
X
X
X
Tri-state
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = three-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active
Document Number: 001-43824 Rev. *H
Page 8 of 19
CY7C1370S
CY7C1372S
Partial Write Cycle Description
The Partial Write Cycle Description table for CY7C1370S follows. [8, 9, 10, 11]
Function (CY7C1370S)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write byte a – (DQa and DQPa)
L
H
H
H
L
Write byte b – (DQb and DQPb)
L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c – (DQc and DQPc)
L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
L
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d – (DQd and DQPd)
L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
L
L
L
L
L
Partial Write Cycle Description
The Partial Write Cycle Description table for CY7C1372S follows. [8, 9, 10, 11]
Function (CY7C1372S)
WE
BWb
BWa
Read
H
X
X
Write – no bytes written
L
H
H
Write byte a – (DQa and DQPa)
L
H
L
Write byte b – (DQb and DQPb)
L
L
H
Write both bytes
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active.
Document Number: 001-43824 Rev. *H
Page 9 of 19
CY7C1370S
CY7C1372S
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
Ambient
Temperature
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V – 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH
voltage[12]
Input LOW
voltage[12]
IDD
[14]
ISB1
ISB2
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
µA
Input current of MODE
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input current of ZZ
IOZ
Test Conditions
Input = VDD
–
30
µA
Output leakage current
GND VI VDDQ, output disabled
–5
5
µA
VDD operating supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–
300
mA
6-ns cycle,
167 MHz
–
275
mA
5-ns cycle,
200 MHz
–
150
mA
6-ns cycle,
167 MHz
–
140
mA
–
70
mA
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
Max. VDD, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Max. VDD, device deselected,
All speed
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f=0
Notes
12. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
13. TPower-up: Assumes a linear ramp from 0 V to VDD (min) within 200 ms. During this time VIH < VDD and VDDQ VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
6-ns cycle,
167 MHz
–
130
mA
–
125
mA
Max. VDD, device deselected,
VIN VIH or VIN VIL, f = 0
–
80
mA
All speed
grades
Capacitance
Parameter [15]
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
28.66
C/W
4.08
C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
Thermal Resistance
Parameter [15]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-43824 Rev. *H
Page 11 of 19
CY7C1370S
CY7C1372S
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
-200
-167
Unit
Min
Max
Min
Max
VCC(typical) to the first access read or write
1
–
1
–
ms
tCYC
Clock cycle time
5
–
6
–
ns
FMAX
Maximum operating frequency
–
200
–
167
MHz
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
–
3.0
–
3.4
ns
tPower[18]
Clock
Output Times
tCO
Data output valid after CLK rise
tEOV
OE LOW to output valid
tDOH
Data output hold after CLK rise
tCHZ
tCLZ
Clock to high
Clock to low
Z[19, 20, 21]
Z[19, 20, 21]
Z[19, 20, 21]
tEOHZ
OE HIGH to output high
tEOLZ
OE LOW to output low Z[19, 20, 21]
–
3.0
–
3.4
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.4
–
1.5
–
ns
tWES
WE, BWx setup before CLK rise
1.4
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.4
–
1.5
–
ns
tCES
Chip select setup
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
ns
tDH
Data input Hold after CLK rise
0.4
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.4
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.4
–
0.5
–
ns
Hold Times
Notes
16. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
18. This part has a voltage regulator internally; tPower is the time power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
20. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high
Z prior to low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 001-43824 Rev. *H
Page 12 of 19
CY7C1370S
CY7C1372S
Switching Waveforms
Figure 2. Read/Write/Timing [22, 23, 24]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-43824 Rev. *H
Page 13 of 19
CY7C1370S
CY7C1372S
Switching Waveforms (continued)
Figure 3. NOP,STALL and DESELECT Cycles [25, 26, 27]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 4. ZZ Mode Timing [28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. The ignore clock edge or stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. IOs are in high Z when exiting ZZ sleep mode.
Document Number: 001-43824 Rev. *H
Page 14 of 19
CY7C1370S
CY7C1372S
Ordering Information
The following table contains only the list of parts that are currently available. If you do not see what you are looking for, contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Package
Diagram
Ordering Code
CY7C1370S-167AXC
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1372S-167AXC
200
CY7C1370S-200AXC
Ordering Code Definitions
CY
7
C 13XX
S - XXX
A
X
C
Temperature range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: XXX = 167 MHz or 200 MHz
Die Revision
Part Identifier: 13XX = 1370 or 1372
1370 = PL, 512Kb × 36 (18Mb)
1372 = PL, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-43824 Rev. *H
Page 15 of 19
CY7C1370S
CY7C1372S
Package Diagrams
Figure 5. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-43824 Rev. *H
Page 16 of 19
CY7C1370S
CY7C1372S
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
NoBL
No Bus Latency
MHz
megahertz
OE
Output Enable
µA
microampere
SRAM
Static Random Access Memory
mA
milliampere
TTL
Transistor-Transistor Logic
mm
millimeter
TQFP
Thin Quad Flat Pack
ms
millisecond
WE
Write Enable
Document Number: 001-43824 Rev. *H
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 17 of 19
CY7C1370S
CY7C1372S
Document History Page
Document Title: CY7C1370S/CY7C1372S, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-43824
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1897927
See ECN
VKN /
AESA
New data sheet.
*A
2082246
See ECN
JASM
Changed status from Preliminary to Final.
*B
2896565
03/20/2010
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagrams.
*C
2906548
04/07/2010
NJY
Updated Ordering Information (Removed inactive parts).
*D
3050813
10/07/2010
AJU
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*E
3196490
03/15/2011
NJY
Updated Package Diagrams.
*F
3572553
04/04/2012
PRIT
Updated Features (Removed 250 MHz frequency related information, removed
119-ball BGA package and 165-ball FBGA package related information).
Updated Selection Guide (Removed 250 MHz frequency related information).
Updated Pin Configurations (Removed 119-ball BGA package and 165-ball
FBGA package related information).
Updated Pin Definitions (Removed JTAG related information).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Order.
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information).
Updated Capacitance (Removed 119-ball BGA package and 165-ball FBGA
package related information).
Updated Thermal Resistance (Removed 119-ball BGA package and 165-ball
FBGA package related information).
Updated Switching Characteristics (Removed 250 MHz frequency related
information).
Updated Package Diagrams (Removed 119-ball BGA package and 165-ball
FBGA package related information).
Replaced all instances of IO with I/O across the document.
*G
3978217
04/22/2013
PRIT
No technical updates.
Completing Sunset Review.
*H
5187232
03/23/2016
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-43824 Rev. *H
Description of Change
Page 18 of 19
CY7C1370S
CY7C1372S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43824 Rev. *H
Revised March 23, 2016
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
Page 19 of 19
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