THIS SPEC IS OBSOLETE
Spec No: 38-05556
Spec Title: CY7C1371D/CY7C1373D, 18-MBIT (512K X
36/1M X 18) FLOW-THROUGH SRAM WITH
NOBL(TM) ARCHITECTURE
Replaced by: NONE
CY7C1371D
CY7C1373D
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■
Supports up to 133-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin-compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte write capability
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock enable (CEN) pin to enable clock and suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA, and 165-ball FBGA packages
■
Three chip enables for simple depth expansion
■
Automatic power-down feature available using ZZ mode or CE
deselect
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability – linear or interleaved burst order
■
Low standby power
The CY7C1371D/CY7C1373D is a 3.3 V, 512K × 36/1M × 18
synchronous flow through burst SRAM designed specifically to
support unlimited true back-to-back read/write operations with
no wait state insertion. The CY7C1371D/CY7C1373D is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum access time
6.5
8.5
ns
Maximum operating current
210
175
mA
Maximum CMOS standby current
70
70
mA
Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05556 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 3, 2016
CY7C1371D
CY7C1373D
Logic Block Diagram – CY7C1371D
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
BW C
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05556 Rev. *S
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 41
CY7C1371D
CY7C1373D
Logic Block Diagram – CY7C1373D
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05556 Rev. *S
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
E
E
READ LOGIC
SLEEP
CONTROL
Page 3 of 41
CY7C1371D
CY7C1373D
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 9
Functional Overview ...................................................... 11
Single Read Accesses .............................................. 11
Burst Read Accesses ................................................ 11
Single Write Accesses ............................................... 11
Burst Write Accesses ................................................ 11
Sleep Mode ............................................................... 11
Interleaved Burst Address Table ............................... 12
Linear Burst Address Table ....................................... 12
ZZ Mode Electrical Characteristics ............................ 12
Truth Table ...................................................................... 13
Partial Truth Table for Read/Write ................................ 14
Partial Truth Table for Read/Write ................................ 14
IEEE 1149.1 Serial Boundary Scan (JTAG [19]) ........... 15
Disabling the JTAG Feature ...................................... 15
Test Access Port (TAP) ............................................. 15
PERFORMING A TAP RESET .................................. 15
TAP REGISTERS ...................................................... 15
TAP Instruction Set ................................................... 16
TAP Controller State Diagram ....................................... 17
TAP Controller Block Diagram ...................................... 18
TAP Timing ...................................................................... 18
TAP AC Switching Characteristics ............................... 19
3.3 V TAP AC Test Conditions ....................................... 20
3.3 V TAP AC Output Load Equivalent ......................... 20
2.5 V TAP AC Test Conditions ....................................... 20
2.5 V TAP AC Output Load Equivalent ......................... 20
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 20
Identification Register Definitions ................................ 21
Document Number: 38-05556 Rev. *S
Scan Register Sizes ....................................................... 21
Identification Codes ....................................................... 21
Boundary Scan Order .................................................... 22
Boundary Scan Order .................................................... 23
Maximum Ratings ........................................................... 24
Operating Range ............................................................. 24
Electrical Characteristics ............................................... 24
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
AC Test Loads and Waveforms ..................................... 26
Switching Characteristics .............................................. 27
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 31
Ordering Code Definitions ......................................... 31
Package Diagrams .......................................................... 32
Acronyms ........................................................................ 35
Document Conventions ................................................. 35
Units of Measure ....................................................... 35
Errata ............................................................................... 36
Part Numbers Affected .............................................. 36
Product Status ........................................................... 36
Ram9 NoBL ZZ Pin
& JTAG Issues Errata Summary ...................................... 36
Document History Page ................................................. 38
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41
Page 4 of 41
CY7C1371D
CY7C1373D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
A
81
A
82
A
83
A
84
ADV/LD
85
VSS
90
OE
VDD
91
86
CE3
92
CEN
BWA
93
87
BWB
94
WE
BWC
95
88
BWD
96
CLK
CE2
97
89
CE1
98
A
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
A0
40
37
A1
VSS
36
A
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
BYTE D
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
CY7C1371D
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 36.
Document Number: 38-05556 Rev. *S
Page 5 of 41
CY7C1371D
CY7C1373D
Pin Configurations (continued)
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [2]
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
CEN
87
90
WE
VSS
91
88
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
CE2
97
96
CE1
98
A
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
VDD
37
A0
40
36
A1
VSS
35
A
39
34
A
NC/144M
33
A
38
32
A
NC/288M
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
CY7C1373D
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 36.
Document Number: 38-05556 Rev. *S
Page 6 of 41
CY7C1371D
CY7C1373D
Pin Configurations (continued)
Figure 3. 119-ball BGA (14 × 22 × 2.4 mm) pinout [3, 4]
CY7C1371D (512K × 36)
A
1
VDDQ
2
A
3
A
4
A
5
A
6
A
7
VDDQ
B
C
NC/576M
NC/1G
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
L
DQD
DQD
DQA
VDDQ
DQD
BWA
VSS
DQA
M
BWD
VSS
DQA
VDDQ
N
DQD
DQD
VSS
VSS
DQA
DQA
CE1
OE
A
WE
VDD
CLK
NC
CEN
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC/144M
A
MODE
VDD
NC
A
NC/288M
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
Notes
3. Errata: The ZZ pin (Ball T7) needs to be externally connected to ground. For more information, see “Errata” on page 36.
4. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see Errata
on page 36.
Document Number: 38-05556 Rev. *S
Page 7 of 41
CY7C1371D
CY7C1373D
Pin Configurations (continued)
Figure 4. 165-ball FBGA (13 × 15 × 1.4 mm) pinout [5, 6]
CY7C1373D (1M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWB
NC
CE3
CEN
ADV/LD
A
A
A
R
MODE
NC/1G
A
CE2
NC
BWA
CLK
WE
OE
A
A
NC
NC
NC
DQB
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
NC
NC
DQPA
DQA
NC
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQA
DQA
ZZ
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC/144M NC/72M
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC/288M
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
NC
NC
DQB
DQB
NC
NC
DQB
DQB
DQB
DQPB
Notes
5. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 36.
6. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see Errata on
page 36.
Document Number: 38-05556 Rev. *S
Page 8 of 41
CY7C1371D
CY7C1373D
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous A[1:0] are fed to the two-bit burst counter.
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ [7]
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Note
7. Errata: The ZZ pin needs to be externally connected to ground. For more information, see Errata on page 36.
Document Number: 38-05556 Rev. *S
Page 9 of 41
CY7C1371D
CY7C1373D
Pin Definitions (continued)
Name
I/O
Description
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tristate condition.The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs.
synchronous
MODE
Input strap pin Mode input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
VSS
I/O power
supply
Ground
Power supply for the I/O circuitry.
Ground for the device.
TDO [8]
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not being used, this pin must be left unconnected. This pin is not available on TQFP packages.
output
synchronous
TDI [8]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available
synchronous on TQFP packages.
TMS [8]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TCK [8]
NC
JTAGclock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
–
No connects. Not internally connected to the die. NC/(36M, 72M, 144M, 288M, 576M, 1G)are address
expansion pins and are not internally connected to the die.
Note
8. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see Errata
on page 36.
Document Number: 38-05556 Rev. *S
Page 10 of 41
CY7C1371D
CY7C1373D
Functional Overview
The CY7C1371D/CY7C1373D is a synchronous flow through
burst SRAM designed specifically to eliminate wait states during
write-read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. Maximum access delay from the clock rise (tCDV) is
6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are all asserted active
■
The write enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tristated immediately.
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1371D/CY7C1373D provides byte write
capability that is described in the truth table. Asserting the write
enable input (WE) with the selected byte write select input
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remains unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included to
greatly simplify read/modify/write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common I/O device,
data must not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQPX inputs. Doing so tristates
the output drivers. As a safety precaution, DQs and DQPX are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW to load the initial address,
as described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, to write the correct bytes
of data.
Burst Read Accesses
Sleep Mode
The CY7C1371D/CY7C1373D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Accesses section above. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps around
when incremented sufficiently. A HIGH input on ADV/LD
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Document Number: 38-05556 Rev. *S
Page 11 of 41
CY7C1371D
CY7C1373D
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05556 Rev. *S
Page 12 of 41
CY7C1371D
CY7C1373D
Truth Table
The truth table for CY7C1371D, and CY7C1373D are as follows. [9, 10, 11, 12, 13, 14, 15]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tristate
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tristate
Read cycle (begin burst)
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tristate
Next
X
X
X
L
H
X
X
H
L
L->H
Tristate
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
Write cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/write abort (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tristate
Write abort (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tristate
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Notes
9. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see truth table for details.
10. Write is defined by BWX, and WE. See truth table for read/write.
11. When a write cycle is detected, all I/Os are tristated, even during byte writes.
12. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
13. CEN = H, inserts wait states.
14. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
15. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tristate when OE is inactive
or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 38-05556 Rev. *S
Page 13 of 41
CY7C1371D
CY7C1373D
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1371D follows. [16, 17, 18]
Function (CY7C1371D)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write no bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1373D follows. [16, 17, 18]
Function (CY7C1373D)
WE
BWA
BWB
Read
H
X
X
Write - no bytes written
L
H
H
Write byte A – (DQA and DQPA)
L
L
H
Write byte B – (DQB and DQPB)
L
H
L
Write all bytes
L
L
L
Notes
16. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see truth table for details.
17. Write is defined by BWX, and WE. See truth table for read/write.
18. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active.
Document Number: 38-05556 Rev. *S
Page 14 of 41
CY7C1371D
CY7C1373D
IEEE 1149.1 Serial Boundary Scan (JTAG [19])
The CY7C1371D/CY7C1373D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
The CY7C1371D/CY7C1373D contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power-up, the device is up in a
reset state which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 17. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 21).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 18. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 22 and Boundary Scan Order
on page 23 show the order in which the bits are connected. Each
bit corresponds to one of the bumps on the SRAM package. The
MSB of the register is connected to TDI and the LSB is
connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 21.
Note
19. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see Errata on
page 36.
Document Number: 38-05556 Rev. *S
Page 15 of 41
CY7C1371D
CY7C1373D
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Identification Codes on page 21. Three of these instructions are
listed as RESERVED and must not be used. The other five
instructions are described in detail below.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
EXTEST
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is supplied a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
Document Number: 38-05556 Rev. *S
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tristate
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package) or bit #89 (for 165-ball FBGA
package). When this scan cell, called the “extest output bus
tristate,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 16 of 41
CY7C1371D
CY7C1373D
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05556 Rev. *S
Page 17 of 41
CY7C1371D
CY7C1373D
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TMS
TAP Timing
Figure 5. TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05556 Rev. *S
UNDEFINED
Page 18 of 41
CY7C1371D
CY7C1373D
TAP AC Switching Characteristics
Over the Operating Range
Parameter [20, 21]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS Hold after TCK clock rise
5
–
ns
tTDIH
TDI Hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
20. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
21. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05556 Rev. *S
Page 19 of 41
CY7C1371D
CY7C1373D
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse level ................................................. VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ...................................... .1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [22]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Description
Min
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Input HIGH voltage
Input LOW voltage
Input load current
Conditions
GND < VIN < VDDQ
Note
22. All voltages referenced to VSS (GND).
Document Number: 38-05556 Rev. *S
Page 20 of 41
CY7C1371D
CY7C1373D
Identification Register Definitions
CY7C1371D
(512K × 36)
Instruction Field
Revision number (31:29)
Device depth (28:24)
CY7C1373D
(1M × 18)
000
000
01011
01011
Description
Describes the version number
Reserved for internal use
Device width (23:18)
001001
001001
Defines memory type and architecture
Cypress device ID (17:12)
100101
010101
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
ID register presence indicator (0)
1
1
Allows unique identification of SRAM
vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
–
Boundary Scan Order (165-ball FBGA package)
–
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 38-05556 Rev. *S
Page 21 of 41
CY7C1371D
CY7C1373D
Boundary Scan Order
119-ball BGA [23, 24]
Bit #
Ball ID
Bit #
1
H4
T4
23
2
24
3
T5
25
4
T6
26
5
R5
6
L5
7
8
Ball ID
Bit #
Ball ID
Bit #
Ball ID
F6
45
G4
67
L1
E7
46
A4
68
M2
D7
47
G3
69
N1
H7
48
C3
70
P1
27
G6
49
B2
71
K1
28
E6
50
B3
72
L2
R6
29
D6
51
A3
73
U6
30
C7
52
C2
74
N2
P2
9
R7
31
B7
53
A2
75
R3
10
T7
32
C6
54
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes
23. Balls which are NC (No Connect) are pre-set LOW.
24. Bit# 85 is pre-set HIGH.
Document Number: 38-05556 Rev. *S
Page 22 of 41
CY7C1371D
CY7C1373D
Boundary Scan Order
165-ball BGA [25, 26]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Note
25. Balls which are NC (No Connect) are pre-set LOW.
26. Bit# 89 is pre-set HIGH.
Document Number: 38-05556 Rev. *S
Page 23 of 41
CY7C1371D
CY7C1373D
Maximum Ratings
Current into outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
Commercial
0 °C to +70 °C
Industrial
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter [27, 28]
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Description
ISB2
Max
Unit
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
3.6
VDD
2.625
–
–
0.4
0.4
VDD + 0.3
VDD + 0.3
0.8
0.7
5
V
V
V
V
V
V
V
V
V
V
V
A
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
7.5 ns cycle,
133 MHz
–
210
mA
10 ns cycle,
100 MHz
–
175
mA
7.5 ns cycle,
133 MHz
–
140
mA
10 ns cycle,
100 MHz
–
120
mA
–
70
mA
For 3.3 V I/O
For 2.5 V I/O
Output HIGH voltage
For 3.3 V I/O, IOH = –4.0 mA
For 2.5 V I/O, IOH = –1.0 mA
Output LOW voltage
For 3.3 V I/O, IOL = 8.0 mA
For 2.5 V I/O, IOL = 1.0 mA
Input HIGH voltage [27]
For 3.3 V I/O
For 2.5 V I/O
Input LOW voltage [27]
For 3.3 V I/O
For 2.5 V I/O
Input leakage current except ZZ GND VI VDDQ
and MODE
Input current of ZZ
ISB1
Min
Power supply voltage
I/O supply voltage
Input current of MODE
IDD
Test Conditions
VDD operating supply current
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX, inputs switching
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDD – 0.3 V,
f = 0, inputs static
Notes
27. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
28. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05556 Rev. *S
Page 24 of 41
CY7C1371D
CY7C1373D
Electrical Characteristics (continued)
Over the Operating Range
Parameter [27, 28]
ISB3
Description
Automatic CE power-down
current – CMOS inputs
ISB4
Automatic CE power-down
current – TTL inputs
Test Conditions
Min
Max
Unit
VDD = Max, device deselected, 7.5 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX, inputs switching
10 ns cycle,
100 MHz
–
130
mA
–
110
mA
VDD = Max, device deselected, All Speeds
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
–
80
mA
Capacitance
Parameter [29]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 119-ball BGA 165-ball FBGA Unit
Package
Package
Package
5
8
9
pF
5
8
9
pF
5
8
9
pF
Thermal Resistance
Parameter [29]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test
conditions
follow
standard test methods and
procedures for measuring
thermal
impedance,
according to EIA/JESD51.
100-pin TQFP 119-ball BGA 165-ball FBGA Unit
Package
Package
Package
28.66
23.8
20.7
C/W
4.08
6.2
4.0
C/W
Note
29. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05556 Rev. *S
Page 25 of 41
CY7C1371D
CY7C1373D
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1ns
1ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
Document Number: 38-05556 Rev. *S
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1ns
1ns
(c)
Page 26 of 41
CY7C1371D
CY7C1373D
Switching Characteristics
Over the Operating Range
Parameter [30, 31]
tPOWER
Description
VDD(typical) to the first access [32]
133 MHz
100 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
2.1
–
2.5
–
ns
tCL
Clock LOW
2.1
–
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
8.5
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
2.0
–
2.0
–
ns
–
4.0
–
5.0
ns
–
3.2
–
3.8
ns
0
–
0
–
ns
–
4.0
–
5.0
ns
[33, 34, 35]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [33, 34, 35]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[33, 34, 35]
OE HIGH to output high Z
[33, 34, 35]
Setup Times
tAS
Address setup before CLK rise
1.5
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.5
–
1.5
–
ns
tWES
WE, BWX setup before CLK rise
1.5
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
30. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
31. Test conditions shown in (a) of Figure 6 on page 26 unless otherwise noted.
32. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
33. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 6 on page 26. Transition is measured ±200 mV from steady-state voltage.
34. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
35. This parameter is sampled and not 100% tested.
Document Number: 38-05556 Rev. *S
Page 27 of 41
CY7C1371D
CY7C1373D
Switching Waveforms
Figure 7. Read/Write Waveforms [36, 37, 38]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
36. For this waveform ZZ is tied LOW.
37. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
38. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05556 Rev. *S
Page 28 of 41
CY7C1371D
CY7C1373D
Switching Waveforms (continued)
Figure 8. NOP, STALL AND DESELECT Cycles [39, 40, 41]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
39. For this waveform ZZ is tied LOW.
40. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
41. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05556 Rev. *S
Page 29 of 41
CY7C1371D
CY7C1373D
Switching Waveforms (continued)
Figure 9. ZZ Mode Timing [42, 43]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
42. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
43. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05556 Rev. *S
Page 30 of 41
CY7C1371D
CY7C1373D
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
Package
Diagram
Operating
Range
Part and Package Type
CY7C1371D-133BGC
51-85115 119-ball BGA (14 × 22 × 2.4 mm)
Commercial
CY7C1371D-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1373D-133AXI
100
CY7C1371D-100AXC
lndustrial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
lndustrial
CY7C1373D-100AXC
CY7C1371D-100AXI
Ordering Code Definitions
CY 7
C 137X
D - XXX XX X X
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
X = Pb-free; X Absent = Leaded
Package Type: XX = BG or BZ or A
BG = 119-ball BGA
BZ = 165-ball FPBGA
A = 100-pin TQFP
Speed Grade: XXX = 133 MHz or 100 MHz
Process Technology: D 90 nm
Part Identifier: 137X = 1371 or 1373
1371 = FT, 512Kb × 36 (18Mb)
1373 = FT, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05556 Rev. *S
Page 31 of 41
CY7C1371D
CY7C1373D
Package Diagrams
Figure 10. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05556 Rev. *S
Page 32 of 41
CY7C1371D
CY7C1373D
Package Diagrams (continued)
Figure 11. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05556 Rev. *S
Page 33 of 41
CY7C1371D
CY7C1373D
Package Diagrams (continued)
Figure 12. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05556 Rev. *S
Page 34 of 41
CY7C1371D
CY7C1373D
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
Symbol
Unit of Measure
CE
Chip Enable
MHz
megahertz
CEN
Clock Enable
µA
microampere
EIA
Electronic Industries Alliance
mA
milliampere
FBGA
Fine-Pitch Ball Grid Array
mm
millimeter
I/O
Input/Output
ms
millisecond
JEDEC
Joint Electron Devices Engineering Council
mV
millivolt
JTAG
Joint Test Action Group
LSB
Least Significant Bit
MSB
Most Significant Bit
NoBL
No Bus Latency
OE
Output Enable
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data Input
TMS
Test Mode Select
TDO
Test Data Output
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05556 Rev. *S
nm
nanometer
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 35 of 41
CY7C1371D
CY7C1373D
Errata
This section describes the Ram9 NoBL ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
18Mb-Ram9 NoBL SRAMs: CY7C137*D
100-pin TQFP
Commercial/
Industrial
119-ball BGA (14 × 22 × 2.4 mm)
Commercial
165-ball FBGA (13 × 15 × 1.4 mm)
Industrial
Product Status
All of the devices in the Ram9 18Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin & JTAG Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb NoBL family devices.
Item
Issues
Description
Device
Fix Status
1.
ZZ Pin
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2.
JTAG
Functionality
During JTAG test mode, the Boundary scan
circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
18M-Ram9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Document Number: 38-05556 Rev. *S
Page 36 of 41
CY7C1371D
CY7C1373D
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue.
2. JTAG Functionality
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■
TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■
SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■
WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
■
FIX STATUS
This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability
Document Number: 38-05556 Rev. *S
Page 37 of 41
CY7C1371D
CY7C1373D
Document History Page
Document Title: CY7C1371D/CY7C1373D, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05556
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
254513
See ECN
RKF
New data sheet.
*A
288531
See ECN
SYT
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [19]) (Edited description
for non-compliance with 1149.1).
Updated Electrical Characteristics (Removed 117 MHz frequency related
information).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (Added Pb-free
information for 100-pin TQFP, 119-ball BGA and 165-ball FBGA Packages),
added comment of ‘Pb-free BG packages availability’ below the Ordering
Information).
*B
326078
See ECN
PCI
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified according to JEDEC standard).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [19]) (Updated TAP
Instruction Set (Updated OVERVIEW (Updated description), updated EXTEST
(Updated description), Added EXTEST Output Bus Tristate)).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters).
Updated Thermal Resistance (Changed value of JA and JC parameters for
100-pin TQFP Package from 31 C/W and 6 C/W to 28.66 C/W and
4.08 C/W respectively, changed value of JA and JC parameters for 119-ball
BGA Package from 45 C/W and 7 C/W to 23.8 C/W and 6.2 C/W
respectively, changed value of JA and JC parameters for 165-ball FBGA
Package from 46 C/W and 3 C/W to 20.7 C/W and 4.0 C/W respectively).
Updated Ordering Information (Updated part numbers, removed comment of
‘Pb-free BG packages availability’ below the Ordering Information).
*C
345117
See ECN
PCI
Changed status from Preliminary to Final.
Updated Ordering Information (Updated part numbers).
*D
416321
See ECN
NXR
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Partial Truth Table for Read/Write (BWA of Write Byte A – (DQA and
DQPA) and BWB of Write Byte B – (DQB and DQPB) has been changed from
H to L).
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE” in the description
of IX parameter, changed the minimum value of IX parameter corresponding to
Input Current of MODE (Input = VSS) from –5 A to –30 A, changed the
maximum value of IX parameter corresponding to Input Current of MODE
(Input = VDD) from 30 A to 5 A, changed the minimum value of IX parameter
corresponding to Input Current of ZZ (Input = VSS) from –30 A to –5 A,
changed the maximum value of IX parameter corresponding to Input Current
of ZZ (Input = VDD) from 5 A to 30 A, updated Note 28 (Changed VIH < VDD
to VIH < VDD)).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Document Number: 38-05556 Rev. *S
Description of Change
Page 38 of 41
CY7C1371D
CY7C1373D
Document History Page (continued)
Document Title: CY7C1371D/CY7C1373D, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05556
Rev.
ECN No.
Submission
Date
Orig. of
Change
*E
475677
See ECN
VKN
*F
1274734
See ECN
VKN /
AESA
*G
2897120
03/22/2010
NJY
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*H
3033272
09/19/2010
NJY
Added Ordering Code Definitions under Ordering Information.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Description of Change
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
and tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
Updated Switching Waveforms (Updated Figure 8 (Corrected typo in the
waveform)).
*I
3067448
10/21/2010
NJY
Updated Ordering Information (Updated part numbers).
*J
3353119
08/24/2011
PRIT
Updated Functional Description (Updated Note as “For best practice
recommendations, refer to SRAM System Guidelines.”).
Updated Package Diagrams (spec 51-85050 (changed revision from *C to *D)).
*K
3613540
05/10/2012
PRIT
Updated Functional Description (Removed the Note “For best practice
recommendations, refer to SRAM System Guidelines.” and its reference).
Updated Pin Configurations (Updated Figure 3 (Removed CY7C1373D related
information), updated Figure 4 (Removed CY7C1371D related information)).
Updated Package Diagrams (spec 51-85180 (changed revision from *C to *E)).
*L
3767562
10/05/2012
PRIT
Updated Package Diagrams (spec 51-85115 (changed revision from *C to *D),
spec 51-85180 (changed revision from *E to *F)).
*M
3981545
04/25/2013
PRIT
Added Errata.
*N
4070450
07/20/2013
PRIT
Added Errata footnotes (Note 1, 2, 3, 4, 5, 6, 7, 8, 19).
Updated Pin Configurations:
Added Note 1 and referred the same note in Figure 1.
Added Note 2 and referred the same note in Figure 2.
Added Note 3, 4 and referred the same note in Figure 3.
Added Note 5, 6 and referred the same note in Figure 4.
Updated Pin Definitions:
Added Note 7 and referred the same note in ZZ pin.
Added Note 8 and referred the same note in TDO, TDI, TMS, TCK pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [19]):
Added Note 19 and referred the same note in JTAG in the heading.
Updated to new template.
*O
4151890
10/09/2013
PRIT
Updated Errata.
*P
4541859
10/17/2014
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*Q
4571917
11/18/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed pruned part CY7C1373D-133BZI.
*R
4974208
10/19/2015
PRIT
Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05556 Rev. *S
Page 39 of 41
CY7C1371D
CY7C1373D
Document History Page (continued)
Document Title: CY7C1371D/CY7C1373D, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05556
Rev.
ECN No.
Submission
Date
Orig. of
Change
*S
5508335
11/03/2016
PRIT
Document Number: 38-05556 Rev. *S
Description of Change
Obsolete document.
Completing Sunset Review.
Page 40 of 41
CY7C1371D
CY7C1373D
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05556 Rev. *S
Revised November 3, 2016
Page 41 of 41
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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