CY7C1373B-83BZC

CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Registered inputs for flow-thru operation • Byte Write capability • Common I/O architecture • Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) • • • • • • • • — 10.0ns (for 83-MHz device) Single 3.3V –5% and +10% power supply VDD Separate VDDQ for 3.3V or 2.5V I/O Clock enable (CEN) pin to suspend operation Synchronous self-timed writes Available in 100 TQFP and 119 BGA packages Burst capability – linear or interleaved burst order JTAG boundary scan for BGA packaging version Automatic power down available using ZZ mode or CE deselect Logic Block Diagram The CY7C1371B/CY7C1373B is 3.3V, 512K x 36 and 1M x 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions.The CY7C1371B/CY7C1373B is pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). Write operations are controlled by the byte Write Selects (BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and a Write enable (WE) input. All writes are conducted with on-chip synchronous self-timed Write circuitry. ZZ may be tied to LOW if it is not used. Synchronous Chip enables (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) and an asynchronous Output enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a Write sequence. D REG. CE Data-In Q CLK ADV/LD Ax CY7C1373 CEN CE1 CE2 CE3 WE BWSx X = 19:0 Mode AX CY7C1371 X = 18:0 DQX X= a, b, c, d X = a, b DPX X = a, b, c, d X = a, b BWSX X = a, b, c, d X = a, b Control and Write Logic 256K X 36/ 512K X 18 Memory Array DQx DPx OE Selection Guide 117 MHz 7.5 250 20 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05198 Rev. *C • 3901 North First Street 100 MHz 8.5 225 20 • 83 MHz 10.0 185 20 Unit ns mA mA San Jose, CA 95134 • 408-943-2600 Revised January 18, 2003 CY7C1371B CY7C1373B Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1373B (1M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A VSS VDD DNU DNU A A A A A A DDQ DQb DQb DQb DQb VSS NC VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DPb DQa NC VSS VSS VDDQ VDDQ DQa NC DQa NC NC DPa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DNU DNU A DNU DNU A A A A A A MODE A A A A A1 A0 DNU DNU VSS VDD Document #: 38-05198 Rev. *C NC DPb NC DQb DQb NC VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ V 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C1371B (512K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ A A A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Packages Page 2 of 26 CY7C1371B CY7C1373B Pin Configurations (continued) 119-ball BGA CY7C1371B (512K × 36) – 7 × 17 BGA A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC CE2 A ADV/LD A CE3 NC NC A A VDD A A NC DQc DPc VSS NC VSS DPb DQb DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS OE VSS DQb VDDQ DQc DQc VDDQ DQc DQc VDD BWSc VSS NC A WE VDD BWSb VSS NC DQb DQb VDD DQb DQb VDDQ DQd DQd VSS CLK VSS DQa DQa DQd DQd BWSd NC BWSa DQa DQa VDDQ DQd DQd DQd VSS VSS CEN A1 VSS VSS DQa DQa VDDQ DQa DQd DPd VSS A0 VSS DPa DQa NC A MODE VDD NC A NC NC 64M A A A 32M ZZ VDDQ TMS TDI TCK TDO NC VDDQ CY7C1373B (1M × 18) – 7 × 17 BGA 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M NC CE2 A ADV/LD A CE3 NC NC A A VDD A A DQb NC NC VSS VSS DPa NC NC NC DQa VSS DQa VDDQ VSS VSS NC NC DQa VDD DQa NC VDDQ NC DQb VSS VSS VDDQ NC VSS NC DQb DQb NC WE VDD CE1 OE A VDDQ VDD BWSb VSS NC NC DQb NC VSS CLK VSS NC DQa VSS NC VDDQ DQb VSS CEN BWSa VSS DQa NC NC VDDQ N P DQb NC VSS A1 VSS DQa NC NC DPb VSS A0 VSS NC DQa R T U NC A MODE VDD NC A NC 64M A A A VDDQ TMS TDI 32M TCK A TDO NC ZZ VDDQ Document #: 38-05198 Rev. *C DQb Page 3 of 26 CY7C1371B CY7C1373B Pin Configurations (continued) 165-ball Bump FBGA CY7C1371B (512K × 36) – 11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWSc BWSb CE3 CEN ADV/LD A A NC B C D E F G H J K L M N P NC DPc A NC CE2 VDDQ BWSd VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC 128M DPb R DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb NC DQd VDD DQd NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ DQa DQd DQd DQd DQd VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DPd NC VDDQ VSS NC NC NC VSS VDDQ NC DPa NC 64M A A TDI A1 TDO A A A NC MODE 32M A A TMS A0 TCK A A A A CY7C1373B (1M × 18) – 11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWSb NC CE3 CEN ADV/LD A A A B C D E F G H J K L M N P NC NC A NC CE2 VDDQ NC VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC 128M DPa R NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDD NC NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ NC DQb DQb NC NC VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa NC NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC NC 64M A A TDI A1 TDO A A A NC MODE 32M A A TMS A0 TCK A A A A Document #: 38-05198 Rev. *C Page 4 of 26 CY7C1371B CY7C1373B Pin Definitions Name I/O Type Description A0 A1 A InputSynchronous Address inputs used to select one of the 532,288/1,048,576 address locations. Sampled at the rising edge of the CLK. BWSa BWSb BWSc BWSd InputSynchronous Byte Write Select inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd. WE InputSynchronous Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a Write sequence. ADV/LD InputSynchronous Advance/Load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-Clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a Write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[X] during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa – DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a Write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQ a, b, c and d are eight-bits wide. DPa DPb DPc DPd I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During Write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. DP a, b, c and d are one-bit wide. ZZ InputAsynchronous ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. MODE Input Pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. VDD Power Supply Power supply inputs to the core of the device. VDDQ I/O Power Supply Power supply for the I/O circuitry. VSS Ground Ground for the device. Should be connected to ground of the system. TDO JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). TDI JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). Document #: 38-05198 Rev. *C Page 5 of 26 CY7C1371B CY7C1373B Pin Definitions Name I/O Type Description TMS Test Mode Select Synchronous This pin controls the Test Access Port (TAP) state machine. Sampled on the rising edge of TCK (BGA only) TCK JTAG serial clock Serial clock to the JTAG circuit (BGA only) 32M 64M 128M – No connects. Reserved for address expansion. Pins are not internally connected. NC – No connects. Pins are not internally connected. DNU – Do not use pins. Functional Overview The CY7C1371B/CY7C1373B is a synchronous flow-thru burst NoBL SRAM specifically designed to eliminate wait states during Write–Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 7.5 ns (117-MHz device). Accesses can be initiated by asserting chip enable(s) (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising edge of the clock. If the clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can be either a Read or Write operation, depending on the status of the Write enable (WE). Byte Write Selects can be used to conduct byte Write operations. Write operations are qualified by the WE. All Writes are simplified with on-chip, synchronous, self-timed Write circuitry. A synchronous chip enable (CE1, CE2, and CE3 on the TQFP, CE1 on the BGA) and an asynchronous OE simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Access A Read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address register and presented to the memory core and control logic. The control logic determines that a Read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Document #: 38-05198 Rev. *C Burst Read Access The CY7C1371B/CY7C1373B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Access Write access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) chip enable(s) asserted active, and (3) WE is asserted LOW. The address presented is loaded into the Address register. The Write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DP. On the next clock rise the data presented to DQ and DP (or a subset for byte Write operation) inputs is latched into the device and the Write is complete (see Write Cycle Description table for details). Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by byte Write Select signals. The CY7C1371B/CY7C1373B provides byte Write capability that is described in the Write Cycle Description table. Asserting the WE input with the selected byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte Write operations. Because the CY7C1371B/CY7C1373B are common I/O devices, data should not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and Page 6 of 26 CY7C1371B CY7C1373B DP are automatically three-stated during the data portion of a Write cycle, regardless of the state of OE. Burst Write Access The CY7C1371B/CY7C1373B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWSa,b,c,d/BWSa,b inputs must be driven in each cycle of the burst Write in order to write the correct bytes of data. Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address Used Operation CE CEN ADV/ LD WE BWSX CLK Comments Deselected External 1 0 0 X X L–H I/Os three-state following next recognized clock. Suspend – X 1 X X X L–H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L–H Address latched. Begin Write External 0 0 0 0 Valid L–H Address latched, data presented two valid clocks later. Burst Read Operation Internal X 0 1 X X L–H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write Operation Internal X 0 1 X Valid L–H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWSa,b,c,d/BWSa,b. Interleaved Burst Sequence First Address Second Address Linear Burst Sequence Third Address Fourth Address First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 ZZ-Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC Description Test Conditions Snooze mode standby current Min. Max. Unit ZZ > VDD − 0.2V 20 mA Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns ZZ recovery time ZZ < 0.2V 2tCYC ns Notes: 1. X = “Don’t Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL chip enables. CE = 0 stands for ALL chip enables active. 2. Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte Write selects are asserted. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN = 1 inserts wait states. 5. Device will power-up deselected and I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05198 Rev. *C Page 7 of 26 CY7C1371B CY7C1373B Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Write Cycle Descriptions[1, 2] Function (CY7C1371B) WE BWSd BWSc BWSb BWSa Read 1 X X X X Write ∠ No Bytes Written 0 1 1 1 1 Write Byte 0 − (DQa and DPa) 0 1 1 1 0 Write Byte 1 − (DQb and DPb) 0 1 1 0 1 Write Bytes 1, 0 0 1 1 0 0 Write Byte 2 − (DQc and DPc) 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Byte 3 − (DQb and DPd) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0 Function (CY7C1373B) WE BWSb BWSa Read 1 x x Write − No Bytes Written 0 1 1 Write Byte 0 − (DQa and DPa) 0 1 0 Write Byte 1 − (DQb and DPc) 0 0 1 Write Both Bytes 0 0 0 Document #: 38-05198 Rev. *C Page 8 of 26 CY7C1371B CY7C1373B IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371B/CY7C1373B incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port – Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most-significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (See TAP Controller State diagram). The output changes on the falling edge of TCK. TDO is connected to the least-significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through Document #: 38-05198 Rev. *C the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the I/O pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The ×36 configuration has a 70-bit-long register, and the ×18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state. It is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM, and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or Page 9 of 26 CY7C1371B CY7C1373B INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO (during this state, instructions are shifted through the instruction register through the TDI and TDO pins). To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction that is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant with the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions: unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the I/O pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (TCS and TCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. SAMPLE Z Bypass The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1-mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. Document #: 38-05198 Rev. *C Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 10 of 26 CY7C1371B CY7C1373B TAP Controller State Diagram 1[7] TEST-LOGIC RESET 1 0 TEST-LOGIC/ 1 1 SELECT IDLE SELECT DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 SHIFT-DR SHIFT-IR 0 1 0 1 1 EXIT1-DR EXIT1-IR 1 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 UPDATE-IR 1 0 0 Note: 7. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05198 Rev. *C Page 11 of 26 CY7C1371B CY7C1373B TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register x . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[8, 9] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V VOH2 Output HIGH Voltage IOH = −100 µA VDD − 0.2 V VOL1 Output LOW Voltage IOL = 8.0 mA 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage 1.7 VDD + 0.3 V VIL Input LOW Voltage −0.5 0.7 V Input Load Current GND ≤ VI ≤ VDDQ −5 5 µA Notes: 8. All voltage referenced to Ground. 9. Overshoot: VIH (AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL (AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. IX Document #: 38-05198 Rev. *C Page 12 of 26 CY7C1371B CY7C1373B TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 100 ns tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns 10 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock HIGH to TDO Invalid 20 0 ns ns Notes: 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO 3.3V Z0 = 50Ω (a) 1.50V CL = 20 pF 0V (b) GND tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05198 Rev. *C tTDOX Page 13 of 26 CY7C1371B CY7C1373B Identification Register Definitions Instruction Field 512K x 36 1M x 18 Description Revision Number (31:28) 0000 0000 Reserved for version number. Device Depth (27:23) 00111 01000 Defines depth of SRAM. 512K or 1M Defines with of the SRAM. x36 or x18 Device Width (22:18) 00100 00011 Cypress Device ID (17:12) 000000 000000 Cypress JEDEC ID (11:1) 00011100100 00011100100 ID Register Presence (0) 1 1 Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70 Identification Codes Instruction Code Description EXTEST 000 Captures the I/O ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the I/O contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05198 Rev. *C Page 14 of 26 CY7C1371B CY7C1373B Boundary Scan Order CY7C1371B (512K × 36) Bit # Signal Name Bump ID Signal Name Bit # CY7C1373B (1M × 18) Bump ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID 1 A 2R 36 CE3 6B 1 A 2R 36 DQb 2E 2 A 3T 37 BWSa 5L 2 A 2T 37 DQb 2G 3 A 4T 38 BWSb 5G 3 A 3T 38 DQb 1H 4 A 5T 39 BWSc 3G 4 A 5T 39 SN 5R 5 A 6R 40 BWSd 3L 5 A 6R 40 DQb 2K 6 A 3B 41 CE2 2B 6 A 3B 41 DQb 1L 7 A 5B 42 CE1 4E 7 A 5B 42 DQb 2M 8 DPa 6P 43 A 3A 8 DQa 7P 43 DQb 1N 9 DQa 7N 44 A 2A 9 DQa 6N 44 DPb 2P 10 DQa 6M 45 DPc 2D 10 DQa 6L 45 MODE 3R 11 DQa 7L 46 DQc 1E 11 DQa 7K 46 A 2C 12 DQa 6K 47 DQc 2F 12 NC 7T 47 A 3C 13 DQa 7P 48 DQc 1G 13 DQa 6H 48 A 5C 14 DQa 6N 49 DQc 2H 14 DQa 7G 49 A 6C 15 DQa 6L 50 DQc 1D 15 DQa 6F 50 A1 4N 16 DQa 7K 51 DQc 2E 16 DQa 7E 51 A0 4P 17 NC 7T 52 DQc 2G 17 DPa 6D 18 DQb 6H 53 DQc 1H 18 A 6T 19 DQb 7G 54 SN 5R 19 A 6A 20 DQb 6F 55 DQd 2K 20 A 5A 21 DQb 7E 56 DQd 1L 21 A 4G 22 DQb 6D 57 DQd 2M 22 A 4A 23 DQb 7H 58 DQd 1N 23 ADV/LD 4B 24 DQb 6G 59 DQd 2P 24 OE 4F 25 DQb 6E 60 DQd 1K 25 CEN 4M 26 DPb 7D 61 DQd 2L 26 WE 4H 27 A 6A 62 DQd 2N 27 CLK 4K 28 A 5A 63 DPd 1P 28 CE3 6B 29 A 4G 64 MODE 3R 29 BWSa 5L 30 A 4A 65 A 2C 30 BWSb 3G 31 ADV/LD 4B 66 A 3C 31 CE2 2B 32 OE 4F 67 A 5C 32 CE1 4E 33 CEN 4M 68 A 6C 33 A 3A 34 WE 4H 69 A1 4N 34 A 2A 35 CLK 4K 70 A0 4P 35 DQb 1D Document #: 38-05198 Rev. *C Page 15 of 26 CY7C1371B CY7C1373B Current into Outputs (LOW)......................................... 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 1500V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −55°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V Range Ambient Temperature[12] DC Voltage Applied to Outputs in High-Z State[13] ....................................−0.5V to VDDQ + 0.5V Commercial 0°C to +70°C DC Input Voltage[13] ................................−0.5V to VDDQ + 0.5V Industrial −40°C to +85°C VDD[15] VDDQ[15] 3.3V − 5%/ +10% 2.5V − 5% 3.3V + 10% Electrical Characteristics Over the Operating Range[14] Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.63 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VOL VIH VIL IX Output LOW Voltage VDD = Min., IOH = −1.0 mA VDDQ = 2.5V 2.0 V VDD = Min., IOH = −4.0 mA VDDQ = 3.3V 2.4 V VDD = Min., IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDD = Min., IOL = 8.0 mA VDDQ = 3.3V 0.4 V Input HIGH Voltage Input LOW Voltage Input Load Current VDDQ = 3.3V 2 V VDDQ = 2.5V 1.7 V VDDQ = 3.3V −0.3 0.8 V VDDQ = 2.5V −0.3 0.7 V 5 µA −30 30 µA −30 30 µA 5 µA 8.5-ns cycle, 117 MHz 250 mA 10-ns cycle, 100 MHz 225 mA GND < VI < VDDQ Input Current of MODE Input Current of ZZ Input = VSS IOZ Output Leakage Current GND < VI < VDDQ, Output Disabled IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 12-ns cycle, 83 MHz 185 mA Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 8.5-ns cycle, 117 MHz 100 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN < 0.3V or VIN > VDDQ ∠ 0.3V, f=0 ISB3 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, or 8.5-ns cycle, 117 MHz VIN < 0.3V or VIN > VDDQ ∠ 0.3V 10-ns cycle, 100 MHz f = fMAX = 1/tCYC 12-ns cycle, 83 MHz Automatic CS Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL, f = 0 ISB1 ISB4 10-ns cycle, 100 MHz 90 mA 12-ns cycle, 83 MHz 75 mA All speed grades 20 mA 90 mA All speeds 75 mA 60 mA 50 mA Notes: 12. TA is the case temperature. 13. Minimum voltage equals −2.0V for pulse durations of less than 20 ns. 14. The load used for VOH and VOL testing is shown in figure (b) of AC Test Loads. 15. Power Supply ramp up should be monotonic. Document #: 38-05198 Rev. *C Page 16 of 26 CY7C1371B CY7C1373B Capacitance[16] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O I/O Capacitance Test Conditions Max. Unit 3 pF 3 pF 3 pF TA = 25°C, f = 1 MHz, VDD = VDDQ = 2.5V AC Test Loads and Waveforms R = 317Ω VDDQ OUTPUT ALL INPUT PULSES OUTPUT Z0 = 50Ω RL = 50Ω VL = 1.5V (a) VDD 10% 5 pF INCLUDING JIG AND SCOPE R = 351Ω [17] 90% 10% 90% GND = 1 V/ns = 1 V/ns (c) (b) Thermal Resistance[16] Description 119 BGA 165 FBGA 100-pin TQFP Test Conditions Still Air, soldered on a 114.3 × 101.6 × 1.57 mm3, two-layer board Still Air, soldered on a 4.25 × 1.125 inch, four-layer printed circuit board ΘJA (Junction to Ambient) ΘJC (Junction to Case) Unit 41.54 6.33 °C/W 44.51 2.38 °C/W 25 9 °C/W Notes: 16. Tested initially and after any design or process change that may affect these parameters. 17. Input waveform should have a slew rate of 1 V/ns. Document #: 38-05198 Rev. *C Page 17 of 26 CY7C1371B CY7C1373B Switching Characteristics Over the Operating Range[18] -117 Parameter Description Min. -100 Max. Min. -83 Max. Min. Max. Unit Clock tCYC Clock Cycle Time 8.5 10.0 12.0 ns tCH Clock HIGH 2.3 2.5 3.0 ns tCL Clock LOW 2.3 2.5 3.0 ns Output Times tCO Data Output Valid After CLK Rise tEOV OE LOW to Output tDOH Data Output Hold After CLK Rise tCHZ tCLZ 7.5 Valid[16, 19, 21] Clock to High-Z[16, 18, 19, 20, 21] Clock to Low-Z[16, 18, 19, 20, 21] 3.4 1.3 OE HIGH to Output tEOLZ OE LOW to Output Low-Z[18, 19, 21] 3.8 1.3 3.0 1.3 High-Z[18, 19, 21] tEOHZ 8.5 ns 4.2 ns 1.3 3.0 1.3 4.0 10.0 ns 3.0 1.3 4.0 ns ns 4.0 ns 0 0 0 ns Set-Up Times tAS Address Set-Up Before CLK Rise 1.5 1.5 1.5 ns tDS Data Input Set-Up Before CLK Rise 1.5 1.5 1.5 ns tCENS CEN Set-Up Before CLK Rise 1.5 1.5 1.5 ns tWES WE, BWSx Set-Up Before CLK Rise 1.5 1.5 1.5 ns tALS ADV/LD Set-Up Before CLK Rise 1.5 1.5 1.5 ns tCES Chip Select Set-Up 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 ns tWEH WE, BWXHold After CLK Rise 0.5 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 ns tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns Hold Times Notes: 18. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads. 19. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document #: 38-05198 Rev. *C Page 18 of 26 CY7C1371B CY7C1373B DESELECT DESELECT Suspend Read Read Write Read Read Read Write Read/Write/Deselect Sequence DESELECT Switching Waveforms CLK tCENH tCENS tCH tCL tCENH tCENS tCYC CEN tAS WA2 RA1 ADDRESS RA3 RA4 WA5 RA6 RA7 tAH WE and BWSx tWES tCES tWEH tCEH CE tCLZ Data In/Out Q1 Out Device originally deselected tCHZ tDOH tCHZ D2 In Q3 Out Q4 Out D5 In tCDV Q6 Out Q7 Out tDOH The combination of WE and BWSx (x = a, b, c, d) to define a Write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = Don’t Care Document #: 38-05198 Rev. *C = Undefined Page 19 of 26 CY7C1371B CY7C1373B Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Read Burst Read Burst Sequences Begin Read Switching Waveforms (continued) CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWEH tWES tWS tWH BWSx tCES tCEH CE tCLZ Data In/Out tCHZ tDOH Q11a Out Q1+1 Out Q1+2 Out tCDV tCDV Device originally deselected tCLZ tDH Q1+3 Out D2 In D2+1 In D2+2 In D2+3 In Q3 Out Q3+1 Out tDS The combination of WE and BWSx (x = a, b, c, d) define a Write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = Don’t Care Document #: 38-05198 Rev. *C = Undefined Page 20 of 26 CY7C1371B CY7C1373B Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/Os tEOLZ ZZ Mode Timing[22, 23] CLK CE1 CE2 LOW HIGH CE3 ZZ tZZS IDD IDD(active) tZZREC IDDZZ I/Os Three-state Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 23. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05198 Rev. *C Page 21 of 26 CY7C1371B CY7C1373B Ordering Information Speed (MHz) 117 100 Ordering Code CY7C1371B-117AC CY7C1373B-117AC Package Name A101 Package Type 100-lead Thin Quad Flat Pack CY7C1371B-117BGC CY7C1373B-117BGC BG119 119 PBGA CY7C1371B-117BZC CY7C1373B-117BZC BB165A 165 FBGA CY7C1371B-100AC CY7C1373B-100AC A101 Operating Range Commercial 100-lead Thin Quad Flat Pack CY7C1371B-100BGC CY7C1373B-100BGC BG119 119 PBGA CY7C1371B-100BZC CY7C1373B-100BZC BB165A 165 FBGA 83 CY7C1371B-83AC A101 100-lead Thin Quad Flat Pack 100 CY7C1371B-100AI CY7C1373B-100AI A101 100-lead Thin Quad Flat Pack CY7C1371B-100BGI CY7C1373B-100BGI BG119 119 PBGA CY7C1371B-100BZI CY7C1373B-100BZI BB165A 165 FBGA Industrial Shaded areas contain advance information. Document #: 38-05198 Rev. *C Page 22 of 26 CY7C1371B CY7C1373B Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05198 Rev. *C Page 23 of 26 CY7C1371B CY7C1373B Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05198 Rev. *C Page 24 of 26 CY7C1371B CY7C1373B Package Diagrams (continued) 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*C ZBT is a registered trademark of IDT. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05198 Rev. *C Page 25 of 26 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1371B CY7C1373B Document History Page Document Title: CY7C1371B/CY7C1373B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Document Number: 38-05198 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE ** 112250 03/01/02 DSG Change from Spec number: 38-01071 to 38-05198 *A 115733 06/20/02 CJM 1) Updated Boundary Scan Order 2) Changed tDOH from 1.5 to 1.3 ns all speeds 3) Updated Ordering Information *B 121533 11/19/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev. *C *C 123128 01/18/03 RBI Add power up requirements to operating range information Document #: 38-05198 Rev. *C Page 26 of 26