CY7C1373D-100BGXC

CY7C1371D CY7C1373D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte Write capability • 3.3V/2.5V IO power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA package. • Three chip enables for simple depth expansion • Automatic Power down feature available using ZZ mode or CE deselect • IEEE 1149.1 JTAG-Compatible Boundary Scan • Burst Capability — linear or interleaved burst order • Low standby power Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 210 70 100 MHz 8.5 175 70 Unit ns mA mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05556 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 09, 2007 CY7C1371D CY7C1373D Logic Block Diagram – CY7C1371D (512K x 36) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 BURST LOGIC Q1 A1' A0' Q0 ADV/LD BW A BW B BW C BW D WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQP A DQP B DQP C DQP D OE CE1 CE2 CE3 ZZ INPUT REGISTER READ LOGIC E SLEEP CONTROL Logic Block Diagram – CY7C1373D (1M x 18) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 BURST LOGIC Q1 A1' A0' Q0 ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQP A DQP B WE OE CE1 CE2 CE3 ZZ INPUT REGISTER READ LOGIC E SLEEP CONTROL Document #: 38-05556 Rev. *F Page 2 of 29 CY7C1371D CY7C1373D Pin Configurations 100-Pin TQFP Pinout ADV/LD BWD BWC BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK WE OE A 82 A 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 A BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 81 A CY7C1371D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A 39 40 41 42 A1 A0 VSS MODE VDD A A A A 43 A A A NC/144M NC/288M Document #: 38-05556 Rev. *F NC/36M NC/72M A A A A Page 3 of 29 CY7C1371D CY7C1373D Pin Configurations (continued) 100-Pin TQFP Pinout ADV/LD BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK WE OE NC NC A 82 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 A 83 A NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC BYTE B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 81 A CY7C1373D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A 38 39 40 41 VDD A1 A0 MODE VSS A A A A 42 A A A NC/144M NC/288M Document #: 38-05556 Rev. *F NC/36M NC/72M A A A A Page 4 of 29 CY7C1371D CY7C1373D Pin Configurations (continued) 119-Ball BGA Pinout CY7C1371D (512K x 36) A B C D E F G H J K L M N P R T U 1 VDDQ NC/576M NC/1G DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC/144M NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M TMS 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI 4 A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC/288M ZZ VDDQ CY7C1373D (1Mx 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC/576M NC/1G DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC/144M NC/72M VDDQ 2 A CE2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS NC VSS VSS VSS MODE A TDI 4 A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD NC/36M TCK 5 A A A VSS VSS VSS NC VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A CE3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC/288M ZZ VDDQ Document #: 38-05556 Rev. *F Page 5 of 29 CY7C1371D CY7C1373D Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1371D (512K x 36) 1 A B C D E F G H J K L M N P R NC/576M NC/1G DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC/36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE 8 ADV/LD OE 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A 11 NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC/288M A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A NC/144M NC/72M A A CY7C1373D (1M x 18) 1 A B C D E F G H J K L M N P R NC/576M NC/1G NC NC NC NC NC NC DQB DQB DQB DQB DQPB MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC/36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE 8 ADV/LD OE 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A 11 A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC/288M A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A NC/144M NC/72M A A Document #: 38-05556 Rev. *F Page 6 of 29 CY7C1371D CY7C1373D Pin Definitions Name A0, A1, A BWA, BWB BWC, BWD WE ADV/LD IO Description InputAddress Inputs used to select one of the address locations. Sampled at the rising edge of the Synchronous CLK. A[1:0] are fed to the two-bit burst counter. InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on Synchronous the rising edge of CLK. InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous signal must be asserted LOW to initiate a write sequence. InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CLK CE1 CE2 CE3 OE InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, Active LOW. Combined with the synchronous logic block Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. InputClock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the Synchronous SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the device, use CEN to extend the previous cycle when required. InputZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. IOBidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. IOBidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. Synchronous Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Power supply inputs to the core of the device. IO Power Supply Ground Power supply for the IO circuitry. Ground for the device. CEN ZZ DQs DQPX MODE VDD VDDQ VSS Document #: 38-05556 Rev. *F Page 7 of 29 CY7C1371D CY7C1373D Pin Definitions (continued) Name TDO IO Description JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin must be left unconnected. This pin is not available on TQFP output Synchronous packages. JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is input Synchronous not available on TQFP packages. JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not input being used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP Synchronous packages. JTAGClock – Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288M, 576M, 1G)are address expansion pins and are not internally connected to the die. TDI TMS TCK NC Functional Overview The CY7C1371D/CY7C1373D is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD must be driven LOW after the device has been deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when these conditions are satisfied at clock rise: • CEN is asserted LOW • CE1, CE2, and CE3 are ALL asserted active • The Write Enable input signal WE is deasserted HIGH • ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access Document #: 38-05556 Rev. *F is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. Burst Read Accesses The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for byte write operations, see truth table for Page 8 of 29 CY7C1371D CY7C1373D details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWX signals. The CY7C1371D/CY7C1373D provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1371D/CY7C1373D is a common IO device, data must not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 80 2tCYC Unit mA ns ns ns ns Document #: 38-05556 Rev. *F Page 9 of 29 CY7C1371D CY7C1373D Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address Used CE1 CE2 CE3 None None None None External Next Next External Next None Next Current None H X X X L X L X L X L X X X X X L X H X H X H X H X X X X H X X L X L X L X L X X X ZZ L L L L L L L L L L L L L H ADV/LD L L L H L H L H L H L H X X WE BWX X X X X H X H X L X L X X X X X X X X X X X L L H H X X OE X X X X L L H H X X X X X X CEN CLK L L L L L L L L L L L L H X L->H L->H L->H L->H DQ Tri-State Tri-State Tri-State Tri-State L->H Data Out (Q) L->H Data Out (Q) L->H L->H Tri-State Tri-State NOP/Dummy Read (Begin Burst) External L->H Data In (D) L->H Data In (D) L->H L->H L->H X Tri-State Tri-State – Tri-State Partial Truth Table for Read/Write[2, 3, 9] Function (CY7C1371D) Read Write No bytes written Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Byte C – (DQC and DQPC) Write Byte D – (DQD and DQPD) Write All Bytes WE H L L L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L Partial Truth Table for Read/Write[2, 3, 9] Function (CY7C1373D) Read Write - No bytes written Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write All Bytes WE H L L L L BWA X H L H L BWB X H H L L Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3. Write is defined by BWX, and WE. See truth table for Read/Write. 4. When a write cycle is detected, all IOs are tri-stated, even during byte writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active. Document #: 38-05556 Rev. *F Page 10 of 29 CY7C1371D CY7C1373D IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1371D/CY7C1373D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device is up in a reset state which does not interfere with the operation of the device. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TAP Controller Block Diagram 0 Bypass Register 210 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE Page 11 of 29 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Document #: 38-05556 Rev. *F CY7C1371D CY7C1373D instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the Document #: 38-05556 Rev. *F Page 12 of 29 CY7C1371D CY7C1373D boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK) t TMSS 2 3 4 5 6 t TH t TMSH t TL t CYC T est Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED Document #: 38-05556 Rev. *F Page 13 of 29 CY7C1371D CY7C1373D TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 20 20 50 20 ns MHz ns ns Description Min Max Unit Notes: 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05556 Rev. *F Page 14 of 29 CY7C1371D CY7C1373D 3.3V TAP AC Test Conditions Input pulse levels ............................................... .VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V 2.5V TAP AC Test Conditions Input pulse level................................................... VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ .1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50 Ω TDO Z O= 50 Ω 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50 Ω TDO Z O= 50 Ω 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Description IOH = –4.0 mA IOH = –1.0 mA Output HIGH Voltage IOH = –100 µA IOL = 8.0 mA IOL = 1.0 mA Output LOW Voltage IOL = 100 µA Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Output LOW Voltage VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input HIGH Voltage VDDQ = 3.3V VDDQ = 2.5V Input LOW Voltage VDDQ = 3.3V VDDQ = 2.5V Input Load Current GND < VIN < VDDQ 2.0 1.7 –0.5 –0.3 –5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.7 5 Max Unit V V V V V V V V V V V V µA Note: 12. All voltages referenced to VSS (GND). Document #: 38-05556 Rev. *F Page 15 of 29 CY7C1371D CY7C1373D Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1371D (512K X 36) 000 01011 001001 100101 00000110100 1 CY7C1373D (1M X 18) 000 01011 001001 010101 00000110100 1 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order (119-Ball BGA package) Boundary Scan Order (165-Ball FBGA package) Bit Size (x36) 3 1 32 85 89 Bit Size (x18) 3 1 32 85 89 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05556 Rev. *F Page 16 of 29 CY7C1371D CY7C1373D 119-Ball BGA Boundary Scan Order [13, 14] Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 Bit # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Ball ID F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 B6 D4 B4 F4 M4 A5 K4 E4 Bit # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Ball ID G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 2K Bit # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID L1 M2 N1 P1 K1 L2 N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal Notes: 13. Balls which are NC (No Connect) are pre-set LOW. 14. Bit# 85 is pre-set HIGH. Document #: 38-05556 Rev. *F Page 17 of 29 CY7C1371D CY7C1373D 165-Ball BGA Boundary Scan Order [13, 15] Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Ball ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 Bit # 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Ball ID D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Note: 15. Bit# 89 is pre-set HIGH. Document #: 38-05556 Rev. *F Page 18 of 29 CY7C1371D CY7C1373D Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Ambient Range Temperature VDD VDDQ Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Electrical Characteristics Over the Operating Range[16, 17] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[16] Input LOW Voltage[16] Input Leakage Current except ZZ and MODE Test Conditions for 3.3V IO for 2.5V IO for 3.3V IO, IOH = –4.0 mA for 2.5V IO, IOH = –1.0 mA for 3.3V IO, IOL = 8.0 mA for 2.5V IO, IOL = 1.0 mA for 3.3V IO for 2.5V IO for 3.3V IO for 2.5V IO GND ≤ VI ≤ VDDQ Min 3.135 3.135 2.375 2.4 2.0 Max 3.6 VDD 2.625 Unit V V V V V V V V V V V µA µA 5 –5 30 7.5 ns cycle, 133 MHz 10 ns cycle, 100 MHz 7.5 ns cycle, 133 MHz 10 ns cycle, 100 MHz All speeds 210 175 140 120 70 µA µA µA mA mA mA mA mA 2.0 1.7 –0.3 –0.3 –5 –30 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IDD ISB1 VDD Operating Supply Current Automatic CE Power down Current—TTL Inputs Input = VSS Input = VDD VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX, inputs switching ISB2 Automatic CE VDD = Max, Device Deselected, Power down VIN ≤ 0.3V or VIN > VDD – 0.3V, Current—CMOS Inputs f = 0, inputs static ISB3 Automatic CE VDD = Max, Device Deselected, or 7.5 ns cycle, 133 MHz Power down VIN ≤ 0.3V or VIN > VDDQ – 0.3V 10 ns cycle, 100 MHz Current—CMOS Inputs f = fMAX, inputs switching Automatic CE Power down Current—TTL Inputs VDD = Max, Device Deselected, All Speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 130 110 80 mA mA mA ISB4 Notes: 16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05556 Rev. *F Page 19 of 29 CY7C1371D CY7C1373D Capacitance[18] Parameter CIN CCLK CIO Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Package 5 5 5 119 BGA Package 8 8 8 165 FBGA Package 9 9 9 Unit pF pF pF Thermal Resistance[18] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. 100 TQFP Package 28.66 4.08 119 BGA Package 23.8 6.2 165 FBGA Package 20.7 4.0 Unit °C/W °C/W AC Test Loads and Waveforms 3.3V IO Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω R = 317Ω VDDQ 5 pF GND R = 351Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1ns VT = 1.5V ≤ 1ns (a) 2.5V IO Test Load OUTPUT Z0 = 50Ω 2.5V INCLUDING JIG AND SCOPE (b) (c) R = 1667Ω VDDQ 5 pF GND R = 1538Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1ns OUTPUT RL = 50Ω VT = 1.25V ≤ 1ns (a) INCLUDING JIG AND SCOPE (b) (c) Note: 18. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05556 Rev. *F Page 20 of 29 CY7C1371D CY7C1373D Switching Characteristics Over the Operating Range[23, 24] 133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold After CLK Rise WE, BWX Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADV/LD Setup Before CLK Rise WE, BWX Setup Before CLK Rise CEN Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z [20, 21, 22] [19] 100 MHz Min 1 10 2.5 2.5 Max Unit ms ns ns ns 8.5 2.0 2.0 ns ns ns 5.0 3.8 0 5.0 ns ns ns ns Description Min 1 Max Clock Cycle Time Clock HIGH Clock LOW 7.5 2.1 2.1 6.5 2.0 2.0 4.0 3.2 0 4.0 Clock to High-Z[20, 21, 22] OE LOW to Output Valid OE LOW to Output OE HIGH to Output Low-Z[20, 21, 22] High-Z[20, 21, 22] Notes: 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 21. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 22. This parameter is sampled and not 100% tested. 23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 24. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05556 Rev. *F Page 21 of 29 CY7C1371D CY7C1373D Switching Waveforms Read/Write Waveforms[25, 26, 27] 1 CLK t CENS t CENH 2 t CYC 3 4 5 6 7 8 9 10 t CH t CL CEN t CES t CEH CE ADV/LD WE BW X ADDRESS t AS A1 t AH A2 A3 t CDV t CLZ A4 t DOH Q(A3) Q(A4) t OEHZ t OEV A5 t CHZ Q(A4+1) A6 A7 DQ t DS D(A1) t DH D(A2) D(A2+1) D(A5) Q(A6) D(A7) OE COM M AND W RITE D(A1) W RITE D(A2) BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) t OELZ t DOH W RITE D(A5) READ Q(A6) W RITE D(A7) DESELECT DON’T CARE UNDEFINED Notes: 25. For this waveform ZZ is tied LOW. 26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05556 Rev. *F Page 22 of 29 CY7C1371D CY7C1373D Switching Waveforms (continued) NOP, STALL AND DESELECT Cycles[25, 26, 28] 1 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS DQ COMMAND WRITE D(A1) 2 3 4 5 6 7 8 9 10 A1 A2 D(A1) READ Q(A2) STALL A3 Q(A2) READ Q(A3) A4 Q(A3) WRITE D(A4) STALL A5 t CHZ D(A4) t DOH NOP READ Q(A5) Q(A5) DESELECT CONTINUE DESELECT DON’T CARE UNDEFINED Note: 28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05556 Rev. *F Page 23 of 29 CY7C1371D CY7C1373D Switching Waveforms (continued) ZZ Mode Timing[29, 30] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 30. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05556 Rev. *F Page 24 of 29 CY7C1371D CY7C1373D Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1371D-133AXC CY7C1373D-133AXC CY7C1371D-133BGC CY7C1373D-133BGC CY7C1371D-133BGXC CY7C1373D-133BGXC CY7C1371D-133BZC CY7C1373D-133BZC CY7C1371D-133BZXC CY7C1373D-133BZXC CY7C1371D-133AXI CY7C1373D-133AXI CY7C1371D-133BGI CY7C1373D-133BGI CY7C1371D-133BGXI CY7C1373D-133BGXI CY7C1371D-133BZI CY7C1373D-133BZI CY7C1371D-133BZXI CY7C1373D-133BZXI 100 CY7C1371D-100AXC CY7C1373D-100AXC CY7C1371D-100BGC CY7C1373D-100BGC CY7C1371D-100BGXC CY7C1373D-100BGXC CY7C1371D-100BZC CY7C1373D-100BZC CY7C1371D-100BZXC CY7C1373D-100BZXC CY7C1371D-100AXI CY7C1373D-100AXI CY7C1371D-100BGI CY7C1373D-100BGI CY7C1371D-100BGXI CY7C1373D-100BGXI CY7C1371D-100BZI CY7C1373D-100BZI CY7C1371D-100BZXI CY7C1373D-100BZXI 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Package Diagram Part and Package Type Operating Range Commercial 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Document #: 38-05556 Rev. *F Page 25 of 29 CY7C1371D CY7C1373D Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 14.00±0.10 100 1 81 80 1.40±0.05 0.30±0.08 22.00±0.20 20.00±0.10 0.65 TYP. 30 31 50 51 12°±1° (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. 0° MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX. NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL 51-85050-*B A Document #: 38-05556 Rev. *F 0.10 R 0.08 MIN. 0.20 MAX. Page 26 of 29 CY7C1371D CY7C1373D Package Diagrams (continued) Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 A B C 1.27 D E F G 22.00±0.20 H 19.50 J K L M 10.16 N P R T U 20.32 2 34 5 6 7 7 6 5 4321 A B C D E F G H J K L M N P R T U 1.27 0.70 REF. A 3.81 12.00 B 2.40 MAX. 7.62 14.00±0.20 0.90±0.05 0.25 C 30° TYP. 0.15(4X) 0.15 C SEATING PLANE 0.56 C 0.60±0.10 51-85115-*B Document #: 38-05556 Rev. *F Page 27 of 29 CY7C1371D CY7C1373D Package Diagrams (continued) Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.50 -0.06 (165X) +0.14 4 1 A B 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 3 2 1 A B D E F G 1.00 C C D E F G 15.00±0.10 15.00±0.10 H J K 14.00 H J K M N P R 7.00 L L M N P R A A 5.00 10.00 B 13.00±0.10 B 0.15(4X) 13.00±0.10 1.00 1.40 MAX. NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC 0.53±0.05 0.25 C SEATING PLANE 0.36 C 0.35±0.06 0.15 C 51-85180-*A NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05556 Rev. *F Page 28 of 29 © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1371D CY7C1373D Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Architecture Document Number: 38-05556 REV. ** *A ECN NO. 254513 288531 Issue Date See ECN See ECN Orig. of Change RKF SYT New data sheet Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.1 Removed 117 Mhz Speed Bin Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information Address expansion pins/balls in the pinouts for all packages are modified according to JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08 °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information Updated Ordering Information Table Updated Ordering Information Table Changed from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” In the Partial Truth Table for Read/Write on page # 10, the BWA of Write Byte A – (DQA and DQPA) and BWB of Write Byte B – (DQB and DQPB) has been changed from H to L Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Changed the Ix current values of MODE on page # 20 from -5 µA and 30 µA to -30 µA and 5 µA Changed the Ix current values of ZZ on page # 20 from -30 µA and 5 µA to -5 µA and 30 µA Changed VIH < VDD to VIH < VDDon page # 20 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Description of Change *B 326078 See ECN PCI *C *D 345117 416321 See ECN See ECN PCI NXR *E 475677 See ECN VKN *F 1274734 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform Document #: 38-05556 Rev. *F Page 29 of 29