CY7C138-25JXC

CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description ■ True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 4K x 8 organization (CY7C138) ■ 0.65-micron complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ High speed access: 25 ns ■ Low operating power: ICC = 160 mA (max.) Fully asynchronous operation ■ Automatic power-down ■ ■ Transistor transistor logic (TTL) compatible Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Available in 68-pin plastic leaded chip carrier (PLCC) ■ Pb-free packages available ■ The CY7C138 is a high speed CMOS 4K x 8 dual-port static RAM. Various arbitration schemes are included on the CY7C138 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138 can be used as a standalone 8-bit dual-port static RAM or multiple devices can be combined to function as a 16-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. Logic Block Diagram R/WL R/WR CEL OEL CER OER I/O7L I/O CONTROL I/O0L I/O7R I/O CONTROL I/O0R [1, 2] BUSYR BUSY L[1, 2] A11L ADDRESS DECODER A0L CEL OE L MEMORY ARRAY INTERRUPT SEMAPHORE ARBITRATION A0R CE R OER R/WR R/WL SEML INTL[2] A11R ADDRESS DECODER M/S SEMR INTR[2] Notes 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor. Cypress Semiconductor Corporation Document #: 38-06037 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 2, 2010 [+] Feedback CY7C138 Contents Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ....................................................................... 5 Switching Characteristics................................................. 5 Architecture .................................................................... 14 Functional Description ................................................... 14 Write Operation ......................................................... 14 Read Operation ......................................................... 14 Interrupts ................................................................... 14 Busy .......................................................................... 14 Master/Slave ............................................................. 14 Semaphore Operation ............................................... 14 Ordering Information ...................................................... 17 4K x8 Dual-Port SRAM .............................................. 17 Ordering Code Definition ........................................... 17 Package Diagram ............................................................ 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC Solutions ......................................................... 21 \ Document #: 38-06037 Rev. *G Page 2 of 21 [+] Feedback CY7C138 Pin Configurations 9 8 7 6 A6L A8L A7L 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C138 52 51 50 49 48 47 46 45 44 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A7R A6R A 9R A8R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 R/W R SEM R CER NC NC GND NC A 11R A10R 21 22 23 24 25 26 I/O7R I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 NC OER I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC NC NC VCC NC A 11L A 10L A9L NC OE L R/W L SEM L CEL I/O 1L I/O 0L Figure 1. 68-Pin PLCC (Top View) Table 1. Pin Definitions Left Port I/O0L–7L A0L–11L CEL OEL R/WL SEML Right Port I/O0R–7R A0R–11R CER OER R/WR SEMR INTL INTR BUSYL M/S VCC GND BUSYR Description Data bus input/output Address lines Chip enable Output enable Read/Write enable Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt flag. INTL is set when right port writes location FFE and is cleared when left port reads location FFE. INTR is set when left port writes location FFF and is cleared when right port reads location FFF. Busy flag Master or slave select Power Ground Table 2. Selection Guide Description Maximum access time (ns) Maximum operating current Maximum standby current for ISB1 Document #: 38-06037 Rev. *G Commercial Commercial 7C138-25 25 180 40 Unit ns mA mA Page 3 of 21 [+] Feedback CY7C138 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[3] Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Storage temperature ................................ –65 C to +150C Latch-up current ..................................................... >200 mA Ambient temperature with power applied ........................................... –55C to +125C Operating Range Supply voltage to ground potential ...............–0.5 V to +7.0 V Range DC voltage applied to outputs in High Z state ..............................................–0.5 V to +7.0 V Commercial DC input voltage[4] ........................................–0.5 V to +7.0 V Industrial Ambient Temperature VCC 0 C to +70 C 5 V ± 10% –40 C to +85 C 5 V ± 10% Output current into outputs (LOW) .............................. 20 mA Electrical Characteristics Over the Operating Range Parameter Description 7C138-25 Test Conditions VOH Output HIGH voltage VCC = Min., IOH = –4.0 mA VOL Output LOW voltage VCC = Min., IOL = 4.0 mA VIH Unit Min Max 2.4 – V – 0.4 V 2.2 – V – 0.8 V –10 +10 A VIL Input LOW voltage IIX Input leakage current GND < VI < VCC IOZ Output leakage current Output disabled, GND < VO < VCC –10 +10 A ICC Operating current VCC = Max., IOUT = 0 mA, Outputs disabled Commercial – 180 mA Industrial – 190 Standby current (Both ports TTL levels) CEL and CER > VIH, f = fMAX[5] Commercial – 40 Industrial – 50 ISB2 Standby current (One port TTL level) CEL and CER > VIH, f = fMAX[5] Commercial – 110 Industrial – 120 ISB3 Standby current (Both ports CMOS levels) Both ports CE and CER > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0[5] Commercial – 15 Industrial – 30 Standby current (One port CMOS level) One port CEL or CER > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, Active Port outputs, f = fMAX[5] Commercial – 100 Industrial – 115 ISB1 ISB4 mA mA mA mA Notes 3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 4. Pulse width < 20 ns. 5. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3 Document #: 38-06037 Rev. *G Page 4 of 21 [+] Feedback CY7C138 Capacitance[6] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions Max TA = 25 C, f = 1 MHz, VCC = 5.0 V Unit 10 pF 15 pF Figure 2. AC Test Loads and Waveforms 5V 5V R1 = 893  C = 30 pF R1 = 893  RTH = 250  Output Output Output C = 5 pF C = 30pF R2 = 347  R2 = 347  VTH = 1.4 V (b) Thévenin Equivalent(Load 1) (a) Normal Load (Load 1) (c) Three-State Delay (Load 3) All Input Pulses Output 3.0 V C = 30 pF GND 10% 90% < 3 ns 90% 10% < 3 ns Load (Load 2) Switching Characteristics Over the Operating Range[7] Parameter Description 7C138-25 Min Max Unit READ CYCLE tRC Read cycle time 25 – ns tAA Address to data valid – 25 ns tOHA Output hold from address change 3 – ns tACE CE LOW to data valid – 25 ns tDOE OE LOW to data valid – 15 ns tLZOE[8,9,10] OE Low to Low Z 3 – ns tHZOE[8,9,10] tLZCE[8,9,10] tHZCE[8,9,10] tPU[10] tPD[10] OE HIGH to High Z – 15 ns CE LOW to Low Z 3 – ns CE HIGH to High Z – 15 ns CE LOW to Power-up 0 – ns CE HIGH to Power-down – 25 ns tWC Write cycle time 25 – ns tSCE CE LOW to write end 20 – ns WRITE CYCLE Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 8. At any temperature and voltage condition for any device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 9. Test conditions used are Load 3 10. This parameter is guaranteed but not tested. Document #: 38-06037 Rev. *G Page 5 of 21 [+] Feedback CY7C138 Switching Characteristics Over the Operating Range[7] (continued) Parameter Description 7C138-25 Min Max Unit tAW Address setup to write end 20 – ns tHA Address hold from write end 2 – ns tSA Address setup to write start 0 – ns tPWE Write pulse width 20 – ns tSD Data setup to write end 15 – ns tHD Data hold from write end 0 – ns tHZWE[11,12] R/W LOW to High Z – 15 ns tLZWE[11,12] tWDD[13] tDDD[13] R/W HIGH to Low Z 3 – ns Write pulse to data delay – 50 ns Write data valid to read data valid – 30 ns tBLA BUSY LOW from address match – 20 ns tBHA BUSY HIGH from address mismatch – 20 ns tBLC BUSY LOW from CE LOW – 20 ns tBHC BUSY HIGH from CE HIGH – 20 ns tPS Port setup for priority 5 – ns tWB R/W LOW after BUSY LOW 0 – ns tWH R/W HIGH after BUSY HIGH 20 – ns tBDD[15] BUSY HIGH to data valid – Note 15 ns BUSY TIMING[14] INTERRUPT TIMING[14] tINS INT set time – 25 ns tINR INT reset time – 25 ns tSOP SEM flag update pulse (OE or SEM) 10 – ns tSWRD SEM flag write to read time 5 – ns tSPS SEM flag contention window 5 – ns SEMAPHORE TIMING Notes 11. Test conditions used are Load 3. 12. This parameter is guaranteed but not tested. 13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 14. Test conditions used are Load 2. 15. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). Document #: 38-06037 Rev. *G Page 6 of 21 [+] Feedback CY7C138 Switching Waveforms Figure 3. Read Cycle No. 1 (Either Port Address Access)[16, 17] tRC Address tOHA Data Out Previous Data Valid tAA Data Valid Notes 16. R/W is HIGH for read cycle. 17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads Document #: 38-06037 Rev. *G Page 7 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)[18, 19, 20, 21] SEM or CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE Data Valid Data Out tPU tPD ICC ISB Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[22, 23] tWC Address R Match t R/W R PWE t Data INR Address L t SD HD VALID Match tDDD Data OUTL Valid tWDD Notes 18. R/W is HIGH for read cycle. 19. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 20. Address valid prior to or coincident with CE transition LOW. 21. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. 22. BUSY = HIGH for the writing port. 23. CEL = CER = LOW. Document #: 38-06037 Rev. *G Page 8 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[24, 25, 26] tWC Address tSCE SEM OR CE tAW tHA tPWE R/W tSA tSD Data In tHD Data Valid OE t tHZOE LZOE High Impedance Data Out Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[24, 26, 27] tWC Address tSCE tHA SEM OR CE R/W tSA tAW tPWE tSD Data Valid Data In tHZWE Data Out tHD tLZWE High Impedance Notes 24. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 25. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 26. R/W must be HIGH during all address transitions. 27. Data I/O pins enter high impedance when OE is held LOW during write. Document #: 38-06037 Rev. *G Page 9 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 8. Semaphore Read After Write Timing, Either Side[28] tAA A0–A 2 Valid Address Valid Address tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O0 Data IN Valid tSA Data OUT Valid tHD tPWE R/W tSWRD tDOE tSOP OE Write Cycle Read Cycle Figure 9. Timing Diagram of Semaphore Contention[29, 30, 31] A0L–A2L Match R/WL SEML tSPS A0R–A2R Match R/WR SEMR Notes 28. CE = HIGH for the duration of the above timing (both write and read cycle). 29. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH 30. Semaphores are reset (available to both ports) at cycle start. 31. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Document #: 38-06037 Rev. *G Page 10 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)[32] tWC Address R Match tPWE R/WR tSD Data In R tHD Valid tPS Address Match L tBLA tBHA BUSYL tBDD tDDD Data OUTL Valid tWDD Figure 11. Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 32. CEL = CER = LOW. Document #: 38-06037 Rev. *G Page 11 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)[33] CEL Valid First: Address Address Match L,R CEL tPS CER tBLC tBHC BUSYR CER Valid First: Address Address Match L,R CER tPS CEL tBLC tBHC BUSY L Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)[33] Left Address Valid First: tRC or tWC Address L Address Match Address Mismatch tPS Address R tBLA tBHA BUSYR Right Address Valid First: tRC or tWC Address R Address Match Address Mismatch tPS Address L tBLA tBHA BUSY L Note 33. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Document #: 38-06037 Rev. *G Page 12 of 21 [+] Feedback CY7C138 Switching Waveforms (continued) Figure 14. Interrupt Timing Diagrams Left Side Sets INTR: tWC Address Write FFF L tHA[34] CE L R/W L INTR tINS[35] Right Side Clears INTR: Address tRC Read FFF R CE R tINR[35] R/W R OE R INT R Right Side Sets INTL: tWC Address R Write FFE tHA[34] CER R/W R INT L tINS[35] Left Side Clears INTL: Address tRC Read FFE R CE L tINR [35] R/W L OE L INT L Notes 34. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 35. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document #: 38-06037 Rev. *G Page 13 of 21 [+] Feedback CY7C138 Architecture The CY7C138 consists of an array of 4K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port–to–port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C138 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C138 has an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which enables data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No. 1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 3. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user of the CY7C138 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Interrupts The interrupt flag (INT) permits communications between ports.When the left port writes to location FFF, the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location FFE. This flag is cleared when the left port reads location FFE. The message at FFF or FFE is user-defined. See Table 4 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate. Busy The CY7C138 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other the Busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Document #: 38-06037 Rev. *G Master/Slave A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented as a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C138 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the a semaphore.If the left side no longer requires the semaphore, a 1 is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to 1 for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port immediately owns the semaphore after the left port releases it. Table 5 shows sample semaphore operations. When reading a semaphore, all eight or nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All semaphores on both sides should have a 1 written into them at initialization from both sides to assure that they are free when needed. Page 14 of 21 [+] Feedback CY7C138 Table 3. Non-Contending Read/Write Inputs CE Outputs Operation R/W OE SEM H X X H High Z Power-down H H L L Data out Read data in semaphore X X H X High Z I/O lines disabled X L Data in Write to semaphore H L H Data ut Read L L X H Data in Write L X X L H L I/O0-7 Illegal condition Table 4. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/W CE OE A0-11 INT R/W CE OE A0-11 INT Set left INT X X X X L L L X FFE X Reset left INT X L L FFE H X X X X X Set right INT L L X FFF X X X X X L Reset right INT X X X X X X L L FFF H Table 5. Semaphore Operation Example I/O0-7 Left I/O0-7 Right No action Function 1 1 Semaphore free Left port writes semaphore 0 1 Left port obtains semaphore Right port writes 0 to semaphore 0 1 Right side is denied access Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore Left port writes 0 to semaphore 1 0 No change. Left port is denied access Right port writes 1 to semaphore 0 1 Left port obtains semaphore Left port writes 1 to semaphore 1 1 No port accessing semaphore address Right port writes 0 to semaphore 1 0 Right port obtains semaphore Right port writes 1 to semaphore 1 1 No port accessing semaphore Left port writes 0 to semaphore 0 1 Left port obtains semaphore Left port writes 1 to semaphore 1 1 No port accessing semaphore Document #: 38-06037 Rev. *G Status Page 15 of 21 [+] Feedback CY7C138 Figure 15. Typical DC and AC Characteristics 0.6 0.4 0.2 4.5 5.0 5.5 ISB3 0.8 0.6 VCC = 5.0 V VIN = 5.0 V 0.4 0.2 0.6 –55 6.0 1.6 1.3 1.4 Normalized tAA 1.4 1.2 1.1 TA = 25 °C 5.0 40 0 0 5.5 1.0 VCC = 5.0 V 0.6 –55 6.0 1.0 2.0 3.0 4.0 5.0 Output Sink Current vs. Output Voltage 120 1.2 0.9 4.5 VCC = 5.0 V TA = 25 °C 80 140 0.8 0.8 4.0 120 Output Voltage (V) Normalized Access Time vs. Ambient Temperature Normalized Access Time vs. Supply Voltage Normalized tAA 125 160 Ambient Temperature (°C) Supply Voltage (V) 1.0 25 Output Source Current (mA) ISB3 0.8 0.0 4.0 200 ICC 1.0 ICC 1.0 Output Source Current vs. Output Voltage Output Sink Current (mA) Normalized ICC, ISB 1.2 1.2 Normalized I,CC ISB 1.4 Normalized Supply Current vs. Ambient Temperature Normalized Supply Current vs. Supply Voltage 25 100 80 60 40 VCC = 5.0 V TA = 25 °C 20 0 0.0 125 1.0 Supply Voltage (V) 2.0 3.0 4.0 5.0 Output Voltage (V) Ambient Temperature (°C) VIN = 5.0 V Typical Power-on Current vs. Supply Voltage Typical Access Time Change vs. Output Loading 30.0 1.00 1.25 Normalized ICC vs. Cycle Time VCC = 5.0 V TA = 25 °C VIN = 5.0 V Delta tAA (ns) Normalized tPC 0.75 Normalized ICC 25.0 20.0 15.0 0.50 0.75 10.0 0.25 0.0 VCC = 4.5 V TA = 25 °C 5.0 0 1.0 2.0 3.0 Supply Voltage (V) Document #: 38-06037 Rev. *G 4.0 5.0 0 1.0 0 200 400 600 Capacitance (pF) 800 1000 0.50 10 28 40 66 Cycle Frequency (MHz) Page 16 of 21 [+] Feedback CY7C138 Ordering Information 4K x8 Dual-Port SRAM Speed (ns) 25 Package Diagram Ordering Code Package Type Operating Range CY7C138-25JXC 51-85005 68-Pin Plastic Leaded Chip Carrier (Pb-free) Commercial CY7C138-25JXI 51-85005 68-Pin Plastic Leaded Chip Carrier (Pb-free) Industrial Ordering Code Definition CY7C XXX - XX XX X Temperature Range: X = C or I C = Commercial; I = Industrial Package: J = PLCC X=X:Pb-free (RoHS Compliant) XX = Speed = 25 ns Density: 138 = Part number identifier CY7C = Cypress Dual Port SRAMs Document #: 38-06037 Rev. *G Page 17 of 21 [+] Feedback CY7C138 Package Diagram Figure 16. 68-Pin Plastic Leaded Chip Carrier (51-85005) 51-85005 *B Document #: 38-06037 Rev. *G Page 18 of 21 [+] Feedback CY7C138 Acronyms Document Conventions Acronym Description CMOS complementary metal oxide semiconductor TQFP thin quad plastic flatpack I/O input/output SRAM static random access memory PLCC plastic leaded chip carrier TTL transistor transistor logic Document #: 38-06037 Rev. *G Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes  Ohms mV milli Volts MHz Mega Hertz pF pico Farad W Watts °C degree Celcius Page 19 of 21 [+] Feedback CY7C138 Document History Page Document Title: CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06037 Rev. ECN No. Orig. of Change Submission Description of Change Date ** 110180 SZV 09/29/01 Change from Spec number: 38-00536 to 38-06037 *A 122287 RBI 12/27/02 power-up requirements added to Maximum Ratings Information *B 393403 YIM See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC *C 2623658 VKN/PYRS 12/17/08 Added CY7C138-25JXI part Removed CY7C139 from the Ordering information table *D 2672737 GNKK *E 2714768 VKN/AESA *F 2898564 RAME *G 3099184 ADMU Document #: 38-06037 Rev. *G 03/12/2009 Corrected title in the Document History table 06/04/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams 03/24/10 Removed inactive parts. Updated package diagram. 12/02/2010 Removed information for CY7C139 parts. Removed speed bins -15,-35,-55. Updated datasheet as per new template Added Acronyms and Units of Measure table Added Ordering Code Definition Updated all footnotes. Page 20 of 21 [+] Feedback CY7C138 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06037 Rev. *G Revised December 2, 2010 Page 21 of 21 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback