CY7C138-25JXI

CY7C138, CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C138/9 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138/9 can be used as a standalone 8/9-bit dual-port static RAM or multiple devices can be combined to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. True Dual-Ported Memory Cells that Enable Simultaneous Reads of the Same Memory Location 4K x 8 Organization (CY7C138) 4K x 9 Organization (CY7C139) 0.65-micron CMOS for Optimum Speed and Power High Speed Access: 15 ns Low Operating Power: ICC = 160 mA (max.) Fully Asynchronous Operation Automatic Power Down TTL Compatible Expandable Data Bus to 32/36 Bits or more using Master/Slave Chip Select when using more than one Device ■ On-Chip Arbitration Logic Semaphores Included to Permit Software Handshaking between Ports ■ INT Flag for Port-to-Port Communication ■ Available in 68-pin PLCC ■ Pb-free Packages Available ■ Logic Block Diagram R/WL CEL OEL R/WR CER OER (7C139)I/O8L I/O7L I/O0L BUSY L[1, 2] A11L A0L ADDRESS DECODER I/O CONTROL I/O CONTROL I/O8R (7C139) I/O7R I/O0R BUSYR A11R A0R [1, 2] MEMORY ARRAY ADDRESS DECODER CEL OE L R/WL SEML INTL[2] \ INTERRUPT SEMAPHORE ARBITRATION CE R OER R/WR SEMR INTR[2] M/S Notes 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor. Cypress Semiconductor Corporation Document #: 38-06037 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 03, 2009 [+] Feedback CY7C138, CY7C139 Pin Configurations Figure 1. 68-Pin PLCC (Top View) NC [4] OE L R/W L SEM L CEL I/O 1L I/O 0L NC NC VCC NC A 11L A 10L A9L 9876 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C138/9 52 51 50 49 48 47 46 45 44 A8L A7L A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 NC [3] OER A 9R A8R R/W R SEM R CER NC NC GND NC A 11R A10R A7R A6R I/O7R Table 1. Pin Definitions Left Port I/O0L–7L(8L) A0L–11L CEL OEL R/WL SEML Right Port I/O0R–7R(8R) A0R–11R CER OER R/WR SEMR Description Data Bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INTL is set when right port writes location FFE and is cleared when left port reads location FFE. INTR is set when left port writes location FFF and is cleared when right port reads location FFF. Busy Flag Master or Slave Select Power Ground INTL BUSYL M/S VCC GND INTR BUSYR Table 2. Selection Guide Description Maximum Access Time (ns) Maximum Operating Current Maximum Standby Current for ISB1 Notes 3. I/O8R on the CY7C139. 4. I/O8L on the CY7C139. Commercial Commercial 7C138-15 7C139-15 15 220 60 7C138-25 7C139-25 25 180 40 A5R 7C138-35 7C139-35 35 160 30 7C138-55 7C139-55 55 160 30 Unit ns mA mA Document #: 38-06037 Rev. *E Page 2 of 17 [+] Feedback CY7C138, CY7C139 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[5] Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential................–0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ................................................–0.5V to +7.0V DC Input Voltage[6] .........................................–0.5V to +7.0V Output Current into Outputs (LOW) ............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current GND < VI < VCC Output Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA, Outputs Disabled CEL and CER > VIH, f = fMAX[7] CEL and CER > VIH, f = fMAX[7] Both Ports CE and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0[7] One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7] Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 125 15 130 60 –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 220 –10 –10 7C138-15 7C139-15 Min 2.4 0.4 2.2 0.8 +10 +10 180 190 40 50 110 120 15 30 100 115 mA mA mA mA Max 7C138-25 7C139-25 Min 2.4 0.4 Max V V V V μA μA mA Unit ISB1 ISB2 ISB3 Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) ISB4 Standby Current (One Port CMOS Level) Notes 5. The Voltage on any input or I/O pin cannot exceed the power pin during power up. 6. Pulse width < 20 ns. 7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3 Document #: 38-06037 Rev. *E Page 3 of 17 [+] Feedback CY7C138, CY7C139 Electrical Characteristics Over the Operating Range (continued) Parameter VOH VOL VIH VIL IIX IOZ ICC Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current GND < VI < VCC Output Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA, Outputs Disabled CEL and CER > VIH, f = fMAX[7] CEL and CER > VIH, f = fMAX[7] Both Ports CE and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0[7] One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7] Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 –10 –10 7C138-35 7C139-35 Min 2.4 0.4 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 mA mA mA mA Max 7C138-55 7C139-55 Min 2.4 0.4 Max V V V V μA μA mA Unit ISB1 ISB2 ISB3 Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) ISB4 Standby Current (One Port CMOS Level) Capacitance[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 10 15 Unit pF pF Document #: 38-06037 Rev. *E Page 4 of 17 [+] Feedback CY7C138, CY7C139 Figure 2. AC Test Loads and Waveforms 5V R1 = 893Ω OUTPUT C = 30 pF R2 = 347Ω OUTPUT C = 30pF VTH = 1.4V (a) Normal Load (Load 1) (b) Thévenin Equivalent Load 1) ( ALL INPUT PULSES OUTPUT C = 30 pF 3.0V GND 10% 90% 90% 10% < 3 ns (c) Three-State Delay (Load 3) RTH = 250Ω 5V R1 = 893Ω OUTPUT C = 5 pF R2 = 347Ω < 3 ns Load (Load 2) Switching Characteristics Over the Operating Range[9] Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE[10,11,12] tHZOE[10,11,12] tLZCE[10,11,12] tHZCE[10,11,12] tPU[12] tPD[12] tWC tSCE tAW tHA tSA tPWE tSD tHD Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold From Write End Address Setup to Write Start Write Pulse Width Data Setup to Write End Data Hold From Write End 15 12 12 2 0 12 10 0 0 15 25 20 20 2 0 20 15 0 3 10 0 25 35 30 30 2 0 25 15 0 3 10 3 15 0 35 55 40 40 2 0 30 20 0 3 15 10 3 15 3 20 0 55 15 15 3 25 15 3 20 3 25 25 25 3 35 20 3 25 35 35 3 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description 7C138-15 7C139-15 Min Max 7C138-25 7C139-25 Min Max 7C138-35 7C139-35 Min Max 7C138-55 7C139-55 Min Max Unit WRITE CYCLE Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06037 Rev. *E Page 5 of 17 [+] Feedback CY7C138, CY7C139 Switching Characteristics Over the Operating Range[9] (continued) Parameter tHZWE[11,12] tLZWE[11,12] tWDD[13] tDDD[13] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[15] INTERRUPT tINS tINR tSOP tSWRD tSPS Description R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid [14] 7C138-15 7C139-15 Min 3 30 25 15 15 15 15 5 0 13 Note 15 15 15 10 5 5 Max 10 7C138-25 7C139-25 Min 3 50 30 20 20 20 20 5 0 20 Note 15 25 25 10 5 5 Max 15 7C138-35 7C139-35 Min 3 60 35 20 20 20 20 5 0 30 Note 15 25 25 15 5 5 Max 20 7C138-55 7C139-55 Min 3 70 40 45 40 40 35 5 0 40 Note 15 30 30 20 5 5 Max 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns BUSY TIMING BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Data Valid TIMING[14] INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEMAPHORE TIMING Switching Waveforms Figure 3. Read Cycle No. 1 (Either Port Address Access)[16, 17] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 10. At any temperature and voltage condition for any device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 11. Test conditions used are Load 3. 12. This parameter is guaranteed but not tested. 13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 14. Test conditions used are Load 2. 15. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). Document #: 38-06037 Rev. *E Page 6 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms (continued) Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)[16, 18, 19] SEM or CE OE tLZOE tLZCE DATA OUT tPU ICC ISB DATA VALID tPD tACE tDOE tHZOE tHZCE Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[20, 21] tWC ADDRESS R R/W R MATCH t PWE t SD t HD DATA INR VALID ADDRESS L MATCH tDDD DATAOUTL tWDD VALID Notes 16. R/W is HIGH for read cycle. 17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 18. Address valid prior to or coincident with CE transition LOW. 19. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. Document #: 38-06037 Rev. *E Page 7 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms (continued) tWC Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24] ADDRESS tSCE SEM OR CE tAW R/W tSA DATA IN tSD DATA VALID tHD tPWE tHA OE tHZOE DATA OUT HIGH IMPEDANCE t LZOE Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[22, 24, 25] tWC ADDRESS tSCE SEM OR CE tSA tAW tPWE tHA R/W tSD DATA IN tHZWE DATA OUT DATA VALID tHD tLZWE HIGH IMPEDANCE Notes 20. BUSY = HIGH for the writing port. 21. CEL = CER = LOW. 22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 24. R/W must be HIGH during all address transitions. Document #: 38-06037 Rev. *E Page 8 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms (continued) Figure 8. Semaphore Read After Write Timing, Either Side[26] tAA tOHA A0–A 2 VALID ADDRESS tAW VALID ADDRESS tACE tSOP SEM tSCE tSD I/O0 tSA R/W tHA DATAIN VALID tPWE tHD DATAOUT VALID tSWRD OE WRITE CYCLE tSOP tDOE READ CYCLE Figure 9. Timing Diagram of Semaphore Contention[27, 28, 29] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR Notes 25. Data I/O pins enter high impedance when OE is held LOW during write. 26. CE = HIGH for the duration of the above timing (both write and read cycle). Document #: 38-06037 Rev. *E Page 9 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms (continued) Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)[21] tWC ADDRESS R R/WR MATCH tPWE tSD tHD DATA INR tPS ADDRESS L MATCH tBLA BUSYL VALID tBHA tBDD tDDD DATAOUTL tWDD VALID Figure 11. Write Timing with Busy Input (M/S=LOW) tPWE R/W tWB BUSY tWH Notes 27. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH 28. Semaphores are reset (available to both ports) at cycle start. 29. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Document #: 38-06037 Rev. *E Page 10 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms CEL Valid First: ADDRESS L,R CEL (continued) Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)[30] ADDRESS MATCH CER tPS tBLC BUSYR tBHC CER Valid First: ADDRESS L,R CER tPS ADDRESS MATCH CEL tBLC BUSY L tBHC Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)[30] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSYR tBHA ADDRESS MISMATCH Right Address Valid First: tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSY L tBHA ADDRESS MISMATCH Note 30. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Document #: 38-06037 Rev. *E Page 11 of 17 [+] Feedback CY7C138, CY7C139 Switching Waveforms Left Side Sets INTR: (continued) Figure 14. Interrupt Timing Diagrams tWC ADDRESS L CE L R/W L INTR tINS[32] WRITE FFF [31] tHA Right Side Clears INTR: ADDRESSR CE R tINR[32] R/W R OE R INT R tRC READ FFF Right Side Sets INTL: tWC ADDRESSR CER R/W R INT L tINS[32] WRITE FFE tHA[31] Left Side Clears INTL: ADDRESSR CE L tINR [32] R/W L OE L INT L Notes 31. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 32. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. tRC READ FFE Document #: 38-06037 Rev. *E Page 12 of 17 [+] Feedback CY7C138, CY7C139 Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port–to–port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C138/9 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C138/9 has an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which enables data to be read from the device. Master/Slave A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented as a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C138/9 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the a semaphore.If the left side no longer requires the semaphore, a 1 is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to 1 for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port immediately owns the semaphore after the left port releases it. Table 5 shows sample semaphore operations. When reading a semaphore, all eight or nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power up. All semaphores on both sides should have a 1 written into them at initialization from both sides to assure that they are free when needed. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No. 1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 3. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user of the CY7C138/9 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Interrupts The interrupt flag (INT) permits communications between ports.When the left port writes to location FFF, the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location FFE. This flag is cleared when the left port reads location FFE. The message at FFF or FFE is user-defined. See Table 4 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate. Busy The CY7C138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other the Busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Document #: 38-06037 Rev. *E Page 13 of 17 [+] Feedback CY7C138, CY7C139 Table 3. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L High Z Data Out High Z Data In Data Out Data In Outputs I/O0-7/8 Power Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition Operation Table 4. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Set Left INT Reset Left INT Set Right INT Reset Right INT Table 5. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Status R/W X X L X CE X L L X OE X L X X A0-11 X FFE FFF X INT L H X X R/W L X X X CE L X X L Right Port OE X X X L A0-11 FFE X X FFF INT X X L H Document #: 38-06037 Rev. *E Page 14 of 17 [+] Feedback CY7C138, CY7C139 Figure 15. Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZED I,CC ISB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 1.0 0.8 0.6 0.4 0.2 0.6 –55 25 125 ISB3 VCC = 5.0V VIN = 5.0V ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 80 40 0 5.0 VCC = 5.0V TA = 25°C 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 ICC ISB3 0.0 4.0 OUTPUT SOURCE CURRENT (mA) 4.5 5.0 5.5 6.0 0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25°C NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 0.8 0.6 –55 140 120 100 80 60 40 20 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5.0V 25 125 0 0.0 VCC = 5.0V TA = 25°C 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) VIN = 5.0V TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.00 NORMALIZED tPC 30.0 25.0 DELTA tAA (ns) 20.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25°C VIN = 5.0V 1.0 0.75 0.50 15.0 10.0 5.0 VCC = 4.5V TA = 25°C 0 200 400 600 800 1000 0.75 0.25 0.0 0 1.0 2.0 3.0 4.0 5.0 0 0.50 10 28 40 66 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-06037 Rev. *E Page 15 of 17 [+] Feedback CY7C138, CY7C139 Ordering Information 4K x8 Dual-Port SRAM Speed (ns) 15 25 Ordering Code CY7C138-15JC CY7C138-15JXC CY7C138-25JC CY7C138-25JXC CY7C138-25JI CY7C138-25JXI 35 55 CY7C138-35JC CY7C138-35JI CY7C138-55JC CY7C138-55JI Package Diagram 51-85005 51-85005 51-85005 51-85005 51-85005 51-85005 51-85005 51-85005 51-85005 51-85005 Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-free) 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-free) 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-free) 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier Commercial Industrial Commercial Industrial Industrial Commercial Operating Range Commercial Package Diagram Figure 16. 68-Pin Plastic Leaded Chip Carrier (51-85005) 51-85005-*A Document #: 38-06037 Rev. *E Page 16 of 17 [+] Feedback CY7C138, CY7C139 Document History Page Document Title: CY7C138, CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06037 Rev. ** *A *B ECN No. 110180 122287 393403 Orig. of Change SZV RBI YIM Submission Description of Change Date 09/29/01 12/27/02 See ECN Change from Spec number: 38-00536 to 38-06037 Power up requirements added to Maximum Ratings Information Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC Added CY7C138-25JXI part Removed CY7C139 from the Ordering information table *C *D *E 2623658 2672737 2714768 VKN/PYRS GNKK VKN/AESA 12/17/08 03/12/2009 Corrected title in the Document History table 06/04/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06037 Rev. *E Revised June 03, 2009 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback