380B
CY7C1380B
CY7C1382B
512K x 36/1M x 18 Pipelined SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
Fast clock speed: 200, 167, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
Optimal for depth expansion
3.3V (–5% / +10%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst sequence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1380B and CY7C1382B SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to
CY7C1380B and DQa,b and DPa,b apply to CY7C1382B. a, b,
c, d each are 8 bits wide in the case of DQ and 1 bit wide in
the case of DP.
Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPc. BWd controls DQd and DPd. BWa,
BWb, BWc, and BWd can be active only with BWE being LOW.
GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the
output for the immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380B and the CY7C1382B
are JEDEC standard JESD8-5 compatible.
Selection Guide
200 MHz
Maximum Access Time
Maximum Operating Current
Commercial
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 38-05267 Rev. *C
•
167 MHz
150 MHz
133 MHz
Unit
3.0
3.4
3.8
4.2
ns
315
285
265
245
mA
20
20
20
20
mA
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1380B
CY7C1382B
Logic Block Diagram CY7C1380B - 512K x 36
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
Q
A[18:0]
19
GW
17
DQd, DPd
BYTEWRITE
REGISTERS
DQc, DPc
BYTEWRITE
REGISTERS
Q
D
DQb, DPb
BYTEWRITE
REGISTERS
Q
D
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
BWE
BW d
D
BWc
BWb
BWa
CE1
CE2
CE3
D
ENABLE CE
REGISTER
19
17
ADDRESS
CE REGISTER
D
512KX36
MEMORY
ARRAY
Q
36
36
Q
D ENABLE DELAY Q
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
SLEEP
CONTROL
ZZ
DQa,b,c,d
DPa,b
Logic Block Diagram CY7C1382B - 1M x 18
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[19:0]
GW
Q
19
BWE
BW b
17
DQb, DPb
BYTEWRITE
REGISTERS
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
ENABLE CE
CE REGISTER
Q
D
D
BWa
CE1
CE2
CE3
ADDRESS
CE REGISTER
D
17
19
1M X 18
MEMORY
ARRAY
Q
18
D ENABLE DELAY Q
REGISTER
OUTPUT
REGISTERS
CLK
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b
DPa,b
Document #: 38-05267 Rev. *C
Page 2 of 34
CY7C1380B
CY7C1382B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1382B
(1M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05267 Rev. *C
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPb NC
NC
DQb
NC
DQb
V
VDDQ DDQ
V
VSSQ SSQ
NC
DQb
NC
DQb
DQb DQb
DQb DQb
VSSQ VSSQ
VDDQ VDDQ
DQb DQb
DQb DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa DQb
VDDQ VDDQ
VSSQ VSSQ
DQa DQb
DQa DQb
DQa DPb
NC
DQa
VSSQ VSSQ
VDDQ VDDQ
NC
DQa
NC
DQa
DQPa NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
CY7C1380B
(512K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100-Pin TQFP
(Top View)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
Page 3 of 34
CY7C1380B
CY7C1382B
Pin Configurations (continued)
CY7C1380B (512K x 36)
1
2
3
A
VDDQ
A
B
C
NC
NC
A
A
D
DQc
4
5
6
7
A
ADSP
A
A
VDDQ
A
A
ADSC
VDD
A
A
A
A
NC
NC
DPc
VSS
NC
VSS
DPb
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
H
J
K
DQc
DQc
VDDQ
DQc
DQc
VDD
BWc
VSS
NC
ADV
GW
VDD
BWb
VSS
NC
DQb
DQb
VDD
DQb
DQb
VDDQ
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
M
N
DQd
VDDQ
DQd
DQd
DQd
DQd
BWd
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
DQa
DQa
DQa
VDDQ
DQa
P
DQd
DPd
VSS
A0
VSS
DPa
DQa
R
NC
A
MODE
VDD
VDD
A
NC
T
U
NC
VDDQ
64M
TMS
A
TDI
A
TCK
A
TDO
32M
NC
ZZ
VDDQ
4
5
6
7
CY7C1382B (1M x 18)
1
2
3
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
A
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
DQb
NC
VSS
NC
VSS
DPa
NC
E
F
NC
VDDQ
DQb
NC
VSS
VSS
CE1
OE
VSS
VSS
NC
DQa
DQa
VDDQ
G
H
J
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
ADV
GW
VDD
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
BWE
VSS
NC
VDDQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DPb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VDD
VDD
A
NC
T
64M
A
A
32M
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05267 Rev. *C
Page 4 of 34
CY7C1380B
CY7C1382B
Pin Configurations (continued)
165-Ball Bump FBGA
CY7C1380B (512K x 36) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWc
BWb
CE3
BWE
ADSC
ADV
A
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
DPc
A
NC
CE2
VDDQ
BWd
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
128M
DPb
DQb
R
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
DQb
DQc
VDDQ
VDD
VSS
VSS
VSS
VDDQ
VDDQ
DQb
DQc
VDD
VDD
DQb
DQb
VDD
DQd
VSS
DQd
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
DQa
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDD
VDDQ
DQa
DQa
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DPd
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
DPa
NC
64M
A
A
TDI
A1
TDO
A
A
A
A
MODE
32M
A
A
TMS
A0
TCK
A
A
A
A
11
CY7C1382B (1M x 18) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
A
NC
A
CE1
BWb
NC
CE3
BWE
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
A
NC
CE2
VDDQ
NC
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
128M
DPa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
R
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDD
DQb
VSS
NC
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
ZZ
NC
NC
NC
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
NC
VDDQ
VDDQ
NC
DQa
DQb
DQb
VDD
VDD
VDD
VDD
VDDQ
DQa
DQa
NC
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DPb
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
NC
NC
64M
A
A
TDI
A1
TDO
A
A
A
A
MODE
32M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05267 Rev. *C
Page 5 of 34
CY7C1380B
CY7C1382B
Pin Definitions
Name
I/O
Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device.(TQFP Only)
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device.(TQFP Only)
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
MODE
Input Pin
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time
critical “sleep” condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by AX during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and
d are 1 bit wide.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. (BGA Only)
Document #: 38-05267 Rev. *C
Page 6 of 34
CY7C1380B
CY7C1382B
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA
Only)
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the
rising edge of TCK. (BGA Only)
TCK
JTAG Serial Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized,
this pin can be disconnected or connected to VSS or VDD. (BGA Only)
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V
–5% +10% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
I/O Power Supply
Power supply for the I/O circuitry. Should be connected to a 2.5 –5% –3.3V
10% power supply.
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
32M
64M
128M
-
No connects. Reserved for address expansion. Pins are not internally connected.
NC
-
No connects. Pins are not internally connected.
Document #: 38-05267 Rev. *C
Page 7 of 34
CY7C1380B
CY7C1382B
Introduction
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
Functional Overview
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx signals. The CY7C1380B/CY7C1382B provides byte write capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1380B and BWa,b for
CY7C1382B) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 4.2 ns (133-MHz
device).
The CY7C1380B/CY7C1382B supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1380 and
BWa,b for CY7C1382) inputs. A Global Write Enable (GW)
overrides all byte write inputs and writes data to all four bytes.
All writes are simplified with on-chip synchronous self-timed
write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is loaded into the address register and the address advancement
logic while being delivered to the RAM core. The write signals
Document #: 38-05267 Rev. *C
Because the CY7C1380B/CY7C1382B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data
presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1380B/CY7C1382B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQ[x:0] inputs. Doing so will three-state
the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1380B/CY7C1382B provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is designed specifically to support Intel® Pentium applications. The
linear burst sequence is designed to support processors that
follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Page 8 of 34
CY7C1380B
CY7C1382B
Interleaved Burst Sequence
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
tZZS
tZZREC
Max.
Unit
ZZ > VDD – 0.2V
20
mA
Device operation to
ZZ
ZZ > VDD – 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
Document #: 38-05267 Rev. *C
Min.
2tCYC
ns
Page 9 of 34
CY7C1380B
CY7C1382B
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
0
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
0
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
0
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
0
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
0
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
0
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
0
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
0
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1. X = “Don't Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
Document #: 38-05267 Rev. *C
Page 10 of 34
CY7C1380B
CY7C1382B
Write Cycle Descriptions
Function (1380)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
0
Write Byte 1 – DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1382)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 – DQ[7:0] and DP0
1
0
1
0
Write Byte 1 – DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Document #: 38-05267 Rev. *C
Page 11 of 34
CY7C1380B
CY7C1382B
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380B/CY7C1382B incorporates a serial boundary
scan Test Access Port (TAP) in the FBGA package only. The
TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does
not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation of the device.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that
TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions
are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuitDocument #: 38-05267 Rev. *C
Page 12 of 34
CY7C1380B
CY7C1382B
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE/PRELOAD
Reserved
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05267 Rev. *C
Bypass
Page 13 of 34
CY7C1380B
CY7C1382B
TAP Controller State Diagram[5]
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
5. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05267 Rev. *C
Page 14 of 34
CY7C1380B
CY7C1382B
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
.
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[6, 7]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −4.0 mA
2.4
V
VOH2
Output HIGH Voltage
IOH = −100 µA
VDD – 0.2
V
VOL1
Output LOW Voltage
IOL = 8.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
−0.5
0.7
V
IX
Input Load Current
−5
5
µA
GND ≤ VI ≤ VDDQ
Notes:
6. All Voltage referenced to Ground.
7. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2, Undershoot:VIL(AC) < 0.5V for t < tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Document #: 38-05267 Rev. *C
Page 15 of 34
CY7C1380B
CY7C1382B
TAP AC Switching Characteristics Over the Operating Range[8, 9]
Parameters
Description
Min.
Max
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
100
ns
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Set-up Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock HIGH to TDO Invalid
20
0
ns
ns
Notes:
8. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05267 Rev. *C
Page 16 of 34
CY7C1380B
CY7C1382B
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
3.3V
Z0 = 50Ω
1.50V
CL = 20 pF
0V
GND
(a)
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
Document #: 38-05267 Rev. *C
tTDOX
Page 17 of 34
CY7C1380B
CY7C1382B
Identification Register Definitions
Instruction Field
512K x 36
1M x 18
xxxx
xxxx
Device Depth
(27:23)
00111
01000
Defines depth of SRAM. 512K or 1M
Device Width
(22:18)
00100
00011
Defines with of the SRAM. x36 or x18
Cypress Device ID
(17:12)
xxxxx
xxxxx
Reserved for future use
Cypress JEDEC ID
(11:1)
00011100100
00011100100
1
1
Revision Number
(31:28)
ID Register Presence
(0)
Description
Reserved for version number
Allows unique identification of SRAM vendor
Indicate the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
51
70
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05267 Rev. *C
Page 18 of 34
CY7C1380B
CY7C1382B
Boundary Scan Order (512K X 36)
Bit #
Signal
Name
Bump
ID
Signal
Name
Bit #
Boundary Scan Order (1M X 18)
Bump
ID
Bit #
Signal
Name
Bump
ID
Signal
Name
Bit #
Bump
ID
1
A
2R
36
A
6B
1
A
2R
36
DQb
2E
2
A
3T
37
BWa
5L
2
A
2T
37
DQb
2G
3
A
4T
38
BWb
5G
3
A
3T
38
DQb
1H
4
A
5T
39
BWc
3G
4
A
5T
39
NC
5R
5
A
6R
40
BWd
3L
5
A
6R
40
DQb
2K
6
A
3B
41
A
2B
6
A
3B
41
DQb
1L
7
A
5B
42
CE
4E
7
A
5B
42
DQb
2M
8
DQa
6P
43
A
3A
8
DQa
7P
43
DQb
1N
9
DQa
7N
44
A
2A
9
DQa
6N
44
DQb
2P
10
DQa
6M
45
DQc
2D
10
DQa
6L
45
MODE
3R
11
DQa
7L
46
DQc
1E
11
DQa
7K
46
A
2C
12
DQa
6K
47
DQc
2F
12
ZZ
7T
47
A
3C
13
DQa
7P
48
DQc
1G
13
DQa
6H
48
A
5C
14
DQa
6N
49
DQc
1D
14
DQa
7G
49
A
6C
15
DQa
6L
50
DQc
1D
15
DQa
6F
50
A1
4N
16
DQa
7K
51
DQc
2E
16
DQa
7E
51
A0
4P
17
ZZ
7T
52
DQc
2G
17
DQa
6D
18
DQb
6H
53
DQc
1H
18
A
6T
19
DQb
7G
54
NC
5R
19
A
6A
20
DQb
6F
55
DQd
2K
20
A
5A
21
DQb
7E
56
DQd
1L
21
ADV
4G
22
DQb
6D
57
DQd
2M
22
ADSP
4A
23
DQb
7H
58
DQd
1N
23
ADSC
4B
24
DQb
6G
59
DQd
2P
24
OE
4F
25
DQb
6E
60
DQd
1K
25
BWE
4M
26
DQb
7D
61
DQd
2L
26
GW
4H
27
A
6A
62
DQd
2N
27
CLK
4K
28
A
5A
63
DQd
1P
28
A
6B
29
ADV
4G
64
MODE
3R
29
BWa
5L
30
ADSP
4A
65
A
2C
30
BWb
3G
31
ADSC
4B
66
A
3C
31
A
2B
32
OE
4F
67
A
5C
32
CE
4E
33
BWE
4M
68
A
6C
33
A
3A
34
GW
4H
69
A1
4N
34
A
2A
35
CLK
4K
70
A0
4P
35
DQb
1D
Document #: 38-05267 Rev. *C
Page 19 of 34
CY7C1380B
CY7C1382B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND ....... –0.3V to +4.6V
DC Voltage Applied to Outputs
in High Z State[10]................................ –0.5V to VDDQ + 0.5V
DC Input Voltage[10] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Static Discharge Voltage........................................... >1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Input LOW
IX
Input Load Current
Ambient
Temp.[11]
Com’l
0°C to +70°C
Ind’l
–40°C to +85°C
Test Conditions
Min.
Max.
Unit
3.135
3.63
V
2.375
3.63
V
VDD = Min., IOH = –1.0 mA
2.5V
2.0
V
VDD = Min., IOL = 8.0 mA
3.3V
VDD = Min., IOL = 1.0 mA
2.5V
0.4
V
V
2.5V
1.7
V
3.3V
–0.3
0.8
2.5V
–0.3
0.7
V
5
µA
-30
30
µA
-30
30
µA
5
µA
5.0-ns cycle, 200 MHz
315
mA
6.0-ns cycle, 167 MHz
285
mA
6.7-ns cycle, 150 MHz
265
mA
7.5-ns cycle, 133 MHz
245
mA
5.0-ns cycle, 200 MHz
140
mA
6.0-ns cycle, 167MHz
120
mA
6.7-ns cycle, 150 MHz
110
mA
7.5-ns cycle, 133 MHz
105
mA
All speed grades
20
mA
Output Leakage
Current
GND < VI < VDDQ, Output Disabled
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device
Deselected, VIN < 0.3V or
VIN > VDDQ – 0.3V, f = 0
V
2.0
GND < VI < VDDQ
Max. VDD, Device
Deselected,
VIN > VIH or VIN VDDQ − 0.3V
f = fMAX = 1/tCYC
Max. VDD, Device
Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Min.
Max.
Unit
5.0-ns cycle, 200 MHz
110
mA
6.0-ns cycle, 167 MHz
100
mA
6.7-ns cycle, 150 MHz
90
mA
7.5-ns cycle, 133 MHz
85
mA
All Speeds
50
mA
Capacitance[13]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1MHz,
VDD = 3.3V,
VDDQ = 3.3V
Max.
Unit
3
pF
3
pF
3
pF
AC Test Loads and Waveforms[14]
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 = 50Ω
3.0V
10%
RL = 50Ω
5 pF
R = 351Ω
VTH = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
≤ 1 V/ns
≤ 1 V/ns
(c)
(b)
Thermal Resistance[13]
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Symbol
TQFP Typ.
Still Air, soldered on a
4.25 x 1.125 inch, 4-layer printed circuit board
ΘJA
25
ΘJC
9
Notes:
13. Tested initially and after any design or process changes that may affect these parameters.
14. Input waveform should have a slew rate of 1 V/ns.
Document #: 38-05267 Rev. *C
Page 21 of 34
CY7C1380B
CY7C1382B
Switching Characteristics Over the Operating Range[15, 16, 17]
-200
Parameter
Description
Min.
Max.
-167
Min.
Max.
-150
Min.
Max.
-133
Min.
Max.
Unit
tCYC
Clock Cycle Time
5.0
6.0
6.7
7.5
ns
tCH
Clock HIGH
1.8
2.1
2.3
2.5
ns
tCL
Clock LOW
1.8
2.1
2.3
2.5
ns
tAS
Address Set-Up Before CLK Rise
1.4
1.5
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
tADS
ADSP, ADSC Set-Up Before CLK Rise
tADH
ADSP, ADSC Hold After CLK Rise
tWES
BWE, GW, BWx Set-Up Before CLK Rise
tWEH
BWE, GW, BWx Hold After CLK Rise
tADVS
ADV Set-Up Before CLK Rise
tADVH
ADV Hold After CLK Rise
tDS
Data Input Set-Up Before CLK Rise
tDH
3.0
3.8
4.2
ns
1.3
1.3
1.3
ns
1.4
1.5
1.5
1.5
ns
0.4
0.5
0.5
0.5
ns
1.4
1.5
1.5
1.5
ns
0.4
0.5
0.5
0.5
ns
1.4
1.5
1.5
1.5
ns
0.4
0.5
0.5
0.5
ns
1.4
1.5
1.5
1.5
ns
Data Input Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tCES
Chip enable Set-Up
1.4
1.5
1.5
1.5
ns
tCEH
Chip enable Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tCHZ
tCLZ
Clock to
High-Z[16]
Clock to
Low-Z[16]
3.0
1.3
High-Z[16, 17]
tEOHZ
OE HIGH to Output
tEOLZ
OE LOW to Output Low-Z[16, 17]
tEOV
OE LOW to Output
1.3
3.4
Valid[16]
3.0
1.3
4.0
0
1.3
4.0
0
3.0
3.0
1.3
4.0
0
3.4
3.0
ns
4.0
0
3.8
ns
ns
ns
4.2
ns
Notes:
15. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
Document #: 38-05267 Rev. *C
Page 22 of 34
CY7C1380B
CY7C1382B
1
Switching Waveforms
Write Cycle Timing[4, 18, 19]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
BWE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
Document #: 38-05267 Rev. *C
Page 23 of 34
CY7C1380B
CY7C1382B
Switching Waveforms (continued)
Read Cycle Timing[4, 18, 20]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
BWE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tCEH
tEOV
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
= DON’T CARE
tCHZ
= UNDEFINED
Note:
20. RDx stands for Read Data from Address X.
Document #: 38-05267 Rev. *C
Page 24 of 34
CY7C1380B
CY7C1382B
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 18, 19, 20]
Single Read
tCYC
Single Write
Unselected
Burst Read
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
tADVS
tADH
ADV
tAS
ADD
tADVH
RD1
WD2
RD3
tAH
GW
tWS
tWS
tWH
BWE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tEOV
OE
Data In/Out
tEOHZ
tEOLZ
tCO
Document #: 38-05267 Rev. *C
1a
1a
Out
tDS
tDH
2a
In
2a
Out
= DON’T CARE
= UNDEFINED
3a
Out
tDOH
3b
Out
3c
Out
3d
Out
tCHZ
Page 25 of 34
CY7C1380B
CY7C1382B
Switching Waveforms (continued)
Pipeline Timing[4, 21, 22]
tCH
tCYC
tCL
CLK
tAS
ADD
RD1
tADS
RD2
RD3
WD1
RD4
WD2
WD3
WD4
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWEH
tWES
BWE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
Out
2a
Out
3a
Out
4a
Out
1a
In
2a
In
3a
In
4a
D(C)
In
tCDV
Back to Back Reads
= DON’T CARE
tDOH
tCHZ
= UNDEFINED
Notes:
21. Device originally deselected.
22. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05267 Rev. *C
Page 26 of 34
CY7C1380B
CY7C1382B
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
I/Os
Three-State
tEOLZ
Document #: 38-05267 Rev. *C
Page 27 of 34
CY7C1380B
CY7C1382B
Switching Waveforms (continued)
ZZ Mode Timing [4, 23, 24]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
NotefjdfdhfdjfdfjdjdjdjNo
Notes:
23. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
24. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05267 Rev. *C
Page 28 of 34
CY7C1380B
CY7C1382B
Ordering Information
Speed
(MHz)
Ordering Code
200
CY7C1380B-200AC
167
CY7C1380B-167AC
150
CY7C1380B-150AC
133
CY7C1380B-133AC
200
CY7C1382B-200AC
167
CY7C1382B-167AC
150
CY7C1382B-150AC
133
CY7C1382B-133AC
200
CY7C1380B-200BGC
167
CY7C1380B-167BGC
150
CY7C1380B-150BGC
133
CY7C1380B-133BGC
200
CY7C1382B-200BGC
167
CY7C1382B-167BGC
150
CY7C1382B-150BGC
133
CY7C1382B-133BGC
200
CY7C1380B-200BZC
167
CY7C1380B-167BZC
150
CY7C1380B-150BZC
133
CY7C1380B-133BZC
200
CY7C1382B-200BZC
167
CY7C1382B-167BZC
150
CY7C1382B-150BZC
133
CY7C1382B-133BZC
Document #: 38-05267 Rev. *C
Package
Name
A101
BG119
BB165A
Package Type
Operating
Range
100-Lead Thin Quad Flat Pack
Commercial
119 BGA
165 FBGA
Page 29 of 34
CY7C1380B
CY7C1382B
Ordering Information
Speed
(MHz)
Ordering Code
167
CY7C1380B-167AI
150
CY7C1380B-150AI
133
CY7C1380B-133AI
167
CY7C1382B-167AI
150
CY7C1382B-150AI
133
CY7C1382B-133AI
167
CY7C1380B-167BGI
150
CY7C1380B-150BGI
133
CY7C1380B-133BGI
167
CY7C1382B-167BGI
150
CY7C1382B-150BGI
133
CY7C1382B-133BGI
167
CY7C1380B-167BZI
150
CY7C1380B-150BZI
133
CY7C1380B-133BZI
167
CY7C1382B-167BZI
150
CY7C1382B-150BZI
133
CY7C1382B-133BZI
Package
Name
A101
BG119
BB165A
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Industrial
119 BGA
165 FBGA
Shaded areas contain advance information.
Document #: 38-05267 Rev. *C
Page 30 of 34
CY7C1380B
CY7C1382B
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05267 Rev. *C
Page 31 of 34
CY7C1380B
CY7C1382B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
Document #: 38-05267 Rev. *C
Page 32 of 34
CY7C1380B
CY7C1382B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*A
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-05267 Rev. *C
Page 33 of 34
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1380B
CY7C1382B
Document History Page
Document Title: CY7C1380B, CY7C1382B 512K x 36M/1M x 18 Pipelined SRAM
Document Number: 38-05267
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
114166
3/18/02
DSG
Change from Spec number: 38-01074 to 38-05267
*A
114817
4/10/02
DSG
Converted updated version: earlier version converted in Rev. **.
The following are the differences between versions:
1. Changed VOH and VOL values to reflect new char. values
2. Maximum voltage rating to 4.6V
3. Modified ESD voltage to 1500V
4. Changed tDOH to 1.3 ns
5. Changed VDD range to +10%/–5%
6. Changed the IDD and ISB values to reflect new char values
7. Added 165 fBGA packaging
8. Added I-temp
9. Changed set-up time from 2.0 ns to 1.5 ns
10.Changed leakage current from mA to µA
11. Changed tEOHZ from 3.0 ns to 4.0 ns
12. Added Thermal Resistance Table
13. Preliminary to Final
*B
119063
09/27/02
HGK
Added TCK pin description.
*C
123134
01/18/03
RBI
Add power up requirements to operating range information
Document #: 38-05267 Rev. *C
DESCRIPTION OF CHANGE
Page 34 of 34
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