CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3V core power supply
■
2.5V or 3.3V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■
Provides high performance 3-1-1-1 access rate
■
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1]
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE1),
depth-expansion chip enables (CE2 and CE3 [2]), burst control
inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package; CY7C1380F/CY7C1382F is available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 119-ball BGA and 165-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
ZZ sleep mode option
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Table 1 on page 6 and “Truth Table” on page 10
for further details). Write cycles can be one to two or four bytes
wide as controlled by the byte write control inputs. GW when
active LOW causes all bytes to be written.
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
350
300
275
mA
Maximum CMOS Standby Current
70
70
70
mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2009
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36)
A0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D , DQP D
BYTE
WRITE REGISTER
DQ D ,DQP D
BYTE
WRITE DRIVER
BW C
DQ C , DQP C
BYTE
WRITE REGISTER
DQ C , DQP C
BYTE
WRITE DRIVER
DQ B , DQP B
BYTE
WRITE REGISTER
DQ B , DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A , DQP A
BYTE
WRITE DRIVER
DQ A , DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1M x 18)
A0, A1, A
ADDRESS
REGISTER
2
BURST Q1
COUNTER AND
LOGIC
ADV
CLK
ADSC
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
MEMORY
ARRAY
BW A
SENSE
OUTPUT
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
BWE
GW
CE 1
CE2
CE3
INPUT
ENABLE
REGISTER
PIPELINED
ENABLE
OE
ZZ
SLEEP
CONTROL
Note
3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).
Document #: 38-05543 Rev. *F
Page 2 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Pin Configurations
100-Pin TQFP Pinout (3-Chip Enable)
Figure 1. CY7C1380D, CY7C1380F(512K X 36)
Document #: 38-05543 Rev. *F
Figure 2. CY7C1382D, CY7C1382F (1M X 18)
Page 3 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
119-Ball BGA Pinout
1
Figure 3. CY7C1380F (512K X 36)
2
3
4
5
A
A
A
ADSP
6
A
7
VDDQ
A
A
A
A
NC/576M
NC/1G
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
VSS
OE
VSS
DQB
VDDQ
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
DQD
DQD
NC
DQA
VDDQ
DQD
BWA
VSS
DQA
M
BWD
VSS
DQA
VDDQ
N
DQD
DQD
VSS
VSS
DQA
DQA
A
VDDQ
B
C
NC/288M
NC/144M
A
A
A
A
ADSC
VDD
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
F
VDDQ
DQC
G
H
J
K
DQC
DQC
VDDQ
DQD
L
GW
VDD
CLK
BWE
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
Figure 4. CY7C1382F (1M X 18)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC/288M
A
A
A
A
NC/576M
C
NC/144M
A
A
ADSC
VDD
A
A
NC/1G
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
VSS
OE
ADV
VSS
DQA
VDDQ
GW
VDD
NC
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
F
VDDQ
NC
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
K
NC
DQB
VSS
CLK
VSS
NC
DQA
L
M
DQB
VDDQ
NC
DQB
NC
VSS
NC
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
BWE
A1
BWA
VSS
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC/72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC/36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05543 Rev. *F
Page 4 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
165-Ball FBGA Pinout (3-Chip Enable)
Figure 5. CY7C1380D/CY7C1380F (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
DQC
NC
DQD
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
TCK
A
A
A
A
8
9
10
11
A
A0
Figure 6. CY7C1382D/CY7C1382F (1M x 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
3
4
5
6
NC
CE3
A
CE1
CE2
BWB
NC/144M
NC
BWA
NC
NC
NC
DQB
VDDQ
VDDQ
VSS
VDD
R
7
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
NC
A
A NC/576M
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
NC
DQB
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
NC
DQA
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05543 Rev. *F
Page 5 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of
Synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0
are fed to the two-bit counter..
BWA, BWB
BWC, BWD
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
Synchronous global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled
only when a new external address is loaded.
CE2 [2]
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3 [2]
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address
is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
InputZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs, DQPX
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
I/O Ground
Ground for the I/O circuitry.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
Document #: 38-05543 Rev. *F
Page 6 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions (continued)
MODE
Input-Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
output
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
Synchronous packages.
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
input
Synchronous TQFP packages.
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
input
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
Synchronous TQFP packages.
TCK
JTAGClock
NC
–
Document #: 38-05543 Rev. *F
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
internally connected to the die.
Page 7 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Functional Overview
Single Write Accesses Initiated by ADSP
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250 MHz device).
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
supports secondary cache in systems using a linear or interleaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence suits
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically increments the address for the rest of the burst access.
This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1,
CE2, and CE3 are all asserted active. The address presented to
A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the write operation is controlled by BWE and BWX signals.
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write cycle
descriptions table. Asserting the byte write enable input (BWE)
with the selected byte write (BWX) input, selectively writes to only
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The corresponding data is enabled to propagate to the input of the output
registers. At the rising edge of the next clock, the data is enabled
to propagate through the output register and onto the data bus
within 2.6 ns (250 MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output tri-states immediately.
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, and CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Document #: 38-05543 Rev. *F
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Page 8 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Burst Sequences
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides a two-bit wraparound counter, fed by A1: A0, that implements an interleaved or a linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Table 3. Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
Table 4. ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Document #: 38-05543 Rev. *F
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
Max
80
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Page 9 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Truth Table
The Truth Table for this data sheet follows.[4, 5, 6, 7, 8]
Operation
Add. Used
CE1
CE2
CE3
ZZ ADSP ADSC
ADV
WRITE OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05543 Rev. *F
Page 10 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Truth Table for Read/Write [4, 9]
Function (CY7C1380D/CY7C1380F)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write [4, 9]
Function (CY7C1382D/CY7C1382F)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
L
H
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Note
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document #: 38-05543 Rev. *F
Page 11 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380D/CY7C1382D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
The CY7C1380D/CY7C1382D contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any
register. (See TAP Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
1
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
x . . . . . 2 1 0
0
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-IR
1
TCK
TMS
0
PAUSE-DR
TAP CONTROLLER
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
0
UPDATE-IR
1
0
The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05543 Rev. *F
TDO
Boundary Scan Register
SHIFT-IR
1
S election
Circuitr y
Identification Register
0
SHIFT-DR
Instruction Register
31 30 29 . . . 2 1 0
CAPTURE-IR
0
1
TDI
0
1
CAPTURE-DR
0
1
Selection
Circuitry
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Page 12 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the “Identification Register Definitions”
on page 16.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in “Identification
Codes” on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail in this section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
Document #: 38-05543 Rev. *F
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. As there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at Bit #85
(for 119-BGA package) or Bit #89 (for 165-fBGA package). When
this scan cell, called the “extest output bus tri-state,” is latched
into the preload register during the Update-DR state in the TAP
controller, it directly controls the state of the output (Q-bus) pins,
Page 13 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
when the EXTEST is entered as the current instruction. When
HIGH, it enables the output buffers to drive the output bus. When
LOW, this bit places the output bus into a High-Z condition.
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range [10, 11]
Parameter
Description
Clock
TCK Clock Cycle Time
tTCYC
TCK Clock Frequency
tTF
TCK Clock HIGH time
tTH
TCK Clock LOW time
tTL
Output Times
TCK Clock LOW to TDO Valid
tTDOV
TCK Clock LOW to TDO Invalid
tTDOX
Setup Times
TMS Setup to TCK Clock Rise
tTMSS
TDI Setup to TCK Clock Rise
tTDIS
Capture Setup to TCK Rise
tCS
Hold Times
TMS Hold after TCK Clock Rise
tTMSH
TDI Hold after Clock Rise
tTDIH
tCH
Capture Hold after Clock Rise
Min
Max
50
20
20
20
10
Unit
ns
MHz
ns
ns
0
ns
ns
5
5
5
ns
ns
ns
5
5
5
ns
ns
ns
Notes
10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1ns.
Document #: 38-05543 Rev. *F
Page 14 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 3.3V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ........................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels ................... ...............................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage ................. .............1.5V
Test load termination supply voltage .................... ........1.25V
Figure 7. 3.3V TAP AC Output Load Equivalent
Figure 8. 2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50 Ω
Z O= 50 Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) [12]
Parameter
Description
Test Conditions
VOH1
Output HIGH Voltage
IOH = –4.0 mA, VDDQ = 3.3V
VOH2
Output HIGH Voltage
VOL1
Output LOW Voltage
IOL = 8.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VDDQ = 3.3V
VIL
Input LOW Voltage
VDDQ = 2.5V
IX
Input Load Current
Min
Max
Unit
2.4
V
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
0.4
V
VDDQ = 2.5V
0.4
V
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
GND < VIN < VDDQ
V
VDDQ = 3.3V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.3
0.8
V
–0.3
0.7
V
–5
5
µA
Note
12. All voltages referenced to VSS (GND).
Document #: 38-05543 Rev. *F
Page 15 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Identification Register Definitions
CY7C1380D/CY7C1380F CY7C1382D/CY7C1382F
(512K x 36)
(1 Mbit x 18)
Instruction Field
Description
Revision Number (31:29)
000
000
Device Depth (28:24) [13]
01011
01011
Device Width (23:18) 119-BGA
101000
101000
Defines the memory type and
architecture.
Device Width (23:18) 165-FBGA
000000
000000
Defines the memory type and
architecture.
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number.
Reserved for internal use.
100101
010101
Defines the width and density.
00000110100
00000110100
Allows unique identification of
SRAM vendor.
1
1
ID Register Presence Indicator (0)
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball FBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05543 Rev. *F
Page 16 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
119-Ball BGA Boundary Scan Order [14, 15]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
H4
T4
23
2
24
3
T5
25
4
T6
26
5
R5
27
G6
49
6
L5
28
E6
50
7
R6
29
D6
51
8
U6
30
C7
52
9
R7
31
B7
53
10
T7
32
C6
54
Bit #
Ball ID
F6
45
G4
67
L1
E7
46
A4
68
M2
D7
47
G3
69
N1
H7
48
C3
70
P1
B2
71
K1
B3
72
L2
A3
73
C2
74
N2
P2
A2
75
R3
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
Document #: 38-05543 Rev. *F
Page 17 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
165-Ball BGA Boundary Scan Order [14, 16]
Bit #
Ball ID
Bit #
Ball ID
1
2
3
N10
4
P11
Bit #
Ball ID
N6
31
N7
32
D10
61
G1
C11
62
D2
33
A11
63
E2
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Note
16. Bit# 89 is pre-set HIGH.
Document #: 38-05543 Rev. *F
Page 18 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND ........–0.3V to +4.6V
Ambient
VDD
VDDQ
Temperature
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
Range
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
VDD
I/O Supply Voltage
VDDQ
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage [17]
VIL
Input LOW Voltage [17]
IX
Input Leakage Current
except ZZ and MODE
Input Current of MODE
IOZ
IDD
[17, 18]
Test Conditions
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND ≤ VI ≤ VDDQ
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE Power
Down Current-CMOS
Inputs
Automatic CE
Power Down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
ISB3
ISB4
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Min
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
Max
3.6
VDD
2.625
Unit
V
V
V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
μA
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
30
5
350
300
275
160
150
140
70
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
135
130
125
80
mA
mA
mA
mA
–30
5
–5
–5
Notes
17. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).
18. TPower up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05543 Rev. *F
Page 19 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Capacitance [19]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CIO
Input/Output Capacitance
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
Test Conditions
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, in accordance with
EIA/JESD51.
28.66
23.8
20.7
°C/W
4.08
6.2
4.0
°C/W
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
Thermal Resistance [19]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Document #: 38-05543 Rev. *F
Page 20 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Figure 9. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
2.5V I/O Test Load
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.25V
(a)
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
≤ 1 ns
(b)
GND
5 pF
90%
10%
90%
≤ 1 ns
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
VDDQ
R = 1538Ω
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05543 Rev. *F
Page 21 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Characteristics Over the Operating Range [20, 21]
Description
Parameter
tPOWER
VDD(Typical) to the first Access [22]
250 MHz
Min
Max
200 MHz
Min
Max
167 MHz
Min
Max
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5
6
ns
tCH
Clock HIGH
1.7
2.0
2.2
ns
tCL
Clock LOW
1.7
2.0
2.2
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.0
1.3
1.3
ns
tCLZ
Clock to Low-Z [23, 24, 25]
1.0
1.3
1.3
ns
tCHZ
Clock to High-Z
[23, 24, 25]
tOEV
OE LOW to Output Valid
[23, 24, 25]
tOELZ
OE LOW to Output Low-Z
tOEHZ
OE HIGH to Output High-Z [23, 24, 25]
2.6
3.0
3.4
ns
2.6
3.0
3.4
ns
2.6
3.0
3.4
ns
0
0
2.6
0
3.0
ns
3.4
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.2
1.4
1.5
ns
tADS
ADSC, ADSP Setup Before CLK Rise
1.2
1.4
1.5
ns
tADVS
ADV Setup Before CLK Rise
1.2
1.4
1.5
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Enable SetUp Before CLK Rise
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
Notes
20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 200
mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document #: 38-05543 Rev. *F
Page 22 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms
Figure 10. Read Cycle Timing [26]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05543 Rev. *F
Page 23 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms
(continued)
Figure 11. Write Cycle Timing [26, 27]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
ata Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05543 Rev. *F
Page 24 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms
(continued)
Figure 12. Read/Write Cycle Timing [26, 28, 29]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A5)
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document #: 38-05543 Rev. *F
Page 25 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms
(continued)
Figure 13. ZZ Mode Timing [30, 31]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05543 Rev. *F
Page 26 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Ordering Information
The following table lists all speed, package and temperature range options. Please note that some options listed below may not
be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products, or contact your local sales representative for the status of
availability of parts.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=201&PageID=230.
Speed
(MHz)
250
Ordering Code
CY7C1380D-250AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1382D-250AXC
CY7C1380F-250AXC
CY7C1382F-250AXC
CY7C1380F-250BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-250BGC
CY7C1380F-250BGXC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-250BGXC
CY7C1380D-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-250BZC
CY7C1380F-250BZC
CY7C1382F-250BZC
CY7C1380D-250BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-250BZXC
CY7C1380F-250BZXC
CY7C1382F-250BZXC
CY7C1380D-250AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1382D-250AXI
CY7C1380F-250AXI
CY7C1382F-250AXI
CY7C1380F-250BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-250BGI
CY7C1380F-250BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-250BGXI
CY7C1380D-250BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-250BZI
CY7C1380F-250BZI
CY7C1382F-250BZI
CY7C1380D-250BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-250BZXI
CY7C1380F-250BZXI
CY7C1382F-250BZXI
Document #: 38-05543 Rev. *F
Page 27 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Speed
(MHz)
200
Ordering Code
CY7C1380D-200AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1382D-200AXC
CY7C1380F-200AXC
CY7C1382F-200AXC
CY7C1380F-200BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-200BGC
CY7C1380F-200BGXC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-200BGXC
CY7C1380D-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-200BZC
CY7C1380F-200BZC
CY7C1382F-200BZC
CY7C1380D-200BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-200BZXC
CY7C1380F-200BZXC
CY7C1382F-200BZXC
CY7C1380D-200AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1382D-200AXI
CY7C1380F-200AXI
CY7C1382F-200AXI
CY7C1380F-200BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-200BGI
CY7C1380F-200BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-200BGXI
CY7C1380D-200BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-200BZI
CY7C1380F-200BZI
CY7C1382F-200BZI
CY7C1380D-200BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-200BZXI
CY7C1380F-200BZXI
CY7C1382F-200BZXI
Document #: 38-05543 Rev. *F
Page 28 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Speed
(MHz)
167
Ordering Code
CY7C1380D-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1382D-167AXC
CY7C1380F-167AXC
CY7C1382F-167AXC
CY7C1380F-167BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-167BGC
CY7C1380F-167BGXC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-167BGXC
CY7C1380D-167BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-167BZC
CY7C1380F-167BZC
CY7C1382F-167BZC
CY7C1380D-167BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-167BZXC
CY7C1380F-167BZXC
CY7C1382F-167BZXC
CY7C1380D-167AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1382D-167AXI
CY7C1380F-167AXI
CY7C1382F-167AXI
CY7C1380F-167BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-167BGI
CY7C1380F-167BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-167BGXI
CY7C1380D-167BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-167BZI
CY7C1380F-167BZI
CY7C1382F-167BZI
CY7C1380D-167BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-167BZXI
CY7C1380F-167BZXI
CY7C1382F-167BZXI
Document #: 38-05543 Rev. *F
Page 29 of 34
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams
Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05543 Rev. *F
A
Page 30 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams
(continued)
Figure 15. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05543 Rev. *F
Page 31 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams
(continued)
Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
BOTTOM VIEW
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 MØ0.05
CAB MC
PIN 1 CORNER
Ø0.25 M C A B
Ø0.50 -0.06
(165X)
PIN 1 CORNER
1
2
1
+0.14
4
2
5
3
6
4
7
5
8
6
9
7
10
11
8
9
11
10
11
10
9
11
8
10
7
9
6
8
5
7
Ø0.50 -0.06 (165X)
4
6
1
3 +0.14
2
5
4
3
2
1A
B
A
C
B
C
B
D
C
D
C
E
D
F
1.00
A
1.00
B
F
E
G
F
G
F
H
G
H
G
J
H
K
J
L
K
M
L
N
M
P
N
P
N
R
P
R
P
7.00
7.00
14.00
D
E
14.00
15.00±0.10
E
15.00±0.10
15.00±0.10
A
15.00±0.10
3
J
H
K
J
L
K
M
L
N
M
R
R
A
A
A
1.00
5.00
A
1.00
5.00
10.00
10.00
B
B
13.00±0.10
B
13.00±0.10
B
13.00±0.10
13.00±0.10
0.15 C
1.40 MAX.
SEATING PLANE
Document #: 38-05543 Rev. *F
NOTES :
NOTES
:
SOLDER
PAD TYPE
: NON-SOLDER MASK DEFINED (NSMD)
PACKAGE
WEIGHT
SOLDER
PAD: 0.475g
TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE
: MO-216
/ DESIGN 4.6C
PACKAGE WEIGHT
: 0.475g
PACKAGE
CODE
: BB0AC : MO-216 / DESIGN 4.6C
JEDEC
REFERENCE
PACKAGE CODE : BB0AC
51-85180-*A
0.35±0.06
C
0.35±0.06
0.36
0.36
SEATING PLANE
C
0.15 C
0.15(4X)
1.40 MAX.
0.53±0.05
0.53±0.05
0.25
C
0.25 C
0.15(4X)
51-85180-*A
Page 32 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document History Page
Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05543
REV.
ECN NO. Submission
Date
Orig. of
Change
Description of Change
**
254515
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225MHz and 133 MHz Speed Bins
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08
°C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W
respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W
respectively
Modified VOL, VOH test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information
Updated Ordering Information Table
*C
416321
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage Current on
page# 18
Changed the IX current values of MODE on page # 18 from –5 μA and 30 μA
to –30 μA and 5 μA
Changed the IX current values of ZZ on page # 18 from –30 μA and 5 μA
to –5 μA and 30 μA
Changed VIH < VDD to VIH < VDDon page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*D
475009
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*E
776456
See ECN
VKN
Added Part numbers CY7C1380F and CY7C1382F and its related information
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
*F
2648065
01/27/09
Document #: 38-05543 Rev. *F
VKN/PYRS Modified note on top of the Ordering information table
Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin
TSOP and 165 BGA package
Page 33 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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image.cypress.com
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psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05543 Rev. *F
Revised January 12, 2009
All products and company names mentioned in this document may be the trademarks of their respective holders.
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