CY7C1380D-200AXCT

CY7C1380D CY7C1380F CY7C1382D 18-Mbit (512K × 36/1M × 18) Pipelined SRAM 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Functional Description ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times ❐ 2.6 ns (for 250 MHz device) ■ Provides high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1380D/CY7C1382D is available in JEDEC-standard Pb-free 100-pin TQFP package; CY7C1380F is available in non Pb-free 165-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write operations (see Pin Definitions on page 6 and Truth Table on page 10 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380D/CY7C1380F/CY7C1382D operates from a +3.3 V core power supply while all outputs operate with a +2.5 or +3.3 V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time Description 2.6 3.0 3.4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA Errata: For information on silicon errata, see “Errata” on page 32. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 38-05543 Rev. *S • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 29, 2016 Not Recommended for New Designs. Features CY7C1380D CY7C1380F CY7C1382D Logic Block Diagram – CY7C1380D/CY7C1380F A0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 BW D DQ D , DQP D BYTE WRITE REGISTER DQ D ,DQP D BYTE WRITE DRIVER BW C DQ C , DQP C BYTE WRITE REGISTER DQ C , DQP C BYTE WRITE DRIVER DQ B , DQP B BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE DRIVER BW B BW A BWE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D DQ A , DQP A BYTE WRITE DRIVER DQ A , DQP A BYTE WRITE REGISTER GW CE 1 CE 2 CE 3 OE MEMORY ARRAY ENABLE REGISTER INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Logic Block Diagram – CY7C1382D A0, A1, A ADDRESS REGISTER 2 BURST Q1 COUNTER AND LOGIC ADV CLK ADSC BW B DQ B, DQP B WRITE DRIVER DQ B, DQP B WRITE REGISTER MEMORY ARRAY BW A SENSE OUTPUT OUTPUT BUFFERS DQs DQP A DQP B DQ A, DQP A WRITE DRIVER DQ A, DQP A WRITE REGISTER BWE GW CE 1 CE2 CE3 INPUT ENABLE REGISTER PIPELINED ENABLE OE ZZ SLEEP CONTROL Document Number: 38-05543 Rev. *S Page 2 of 38 Not Recommended for New Designs. ADSP CY7C1380D CY7C1380F CY7C1382D Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Single Write Accesses Initiated by ADSP ................... 8 Single Write Accesses Initiated by ADSC ................... 8 Burst Sequences ......................................................... 8 Sleep Mode ................................................................. 9 Interleaved Burst Address Table ................................. 9 Linear Burst Address Table ......................................... 9 ZZ Mode Electrical Characteristics .............................. 9 Truth Table ...................................................................... 10 Truth Table for Read/Write ............................................ 11 Truth Table for Read/Write ............................................ 11 IEEE 1149.1 Serial Boundary Scan (JTAG [13]) ........... 12 Disabling the JTAG Feature ...................................... 12 Test Access Port (TAP) ............................................. 12 PERFORMING A TAP RESET .................................. 12 TAP REGISTERS ...................................................... 12 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 14 TAP Controller Block Diagram ...................................... 15 TAP Timing ...................................................................... 16 TAP AC Switching Characteristics ............................... 16 3.3 V TAP AC Test Conditions ....................................... 17 3.3 V TAP AC Output Load Equivalent ......................... 17 2.5 V TAP AC Test Conditions ....................................... 17 2.5 V TAP AC Output Load Equivalent ......................... 17 TAP DC Electrical Characteristics and Operating Conditions ............................................. 17 Identification Register Definitions ................................ 18 Document Number: 38-05543 Rev. *S Scan Register Sizes ....................................................... 18 Identification Codes ....................................................... 18 Boundary Scan Order .................................................... 19 Maximum Ratings ........................................................... 20 Operating Range ............................................................. 20 Electrical Characteristics ............................................... 20 Capacitance .................................................................... 21 Thermal Resistance ........................................................ 21 AC Test Loads and Waveforms ..................................... 22 Switching Characteristics .............................................. 23 Switching Waveforms .................................................... 24 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Package Diagrams .......................................................... 29 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Errata ............................................................................... 32 Part Numbers Affected .............................................. 32 Product Status ........................................................... 32 Ram9 Sync ZZ Pin & JTAG Issues Errata Summary ...................................... 32 Document History Page ................................................. 34 Sales, Solutions, and Legal Information ...................... 38 Worldwide Sales and Design Support ....................... 38 Products .................................................................... 38 PSoC® Solutions ...................................................... 38 Cypress Developer Community ................................. 38 Technical Support ..................................................... 38 Page 3 of 38 Not Recommended for New Designs. Contents CY7C1380D CY7C1380F CY7C1382D Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable) [1] CY7C1382D (1M × 18) Not Recommended for New Designs. CY7C1380D (512K × 36) Note 1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see “Errata” on page 32. Document Number: 38-05543 Rev. *S Page 4 of 38 CY7C1380D CY7C1380F CY7C1382D Pin Configurations (continued) Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable) [2, 3] 1 A B C D E F G H J K L M N P NC/288M R 2 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 NC BWE ADSC ADV A NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA A VSS VDDQ DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS TCK A A A A A0 Notes 2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 32. 3. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata” on page 32. Document Number: 38-05543 Rev. *S Page 5 of 38 Not Recommended for New Designs. CY7C1380F (512K × 36) CY7C1380D CY7C1380F CY7C1382D Pin Definitions Name A0, A1, A I/O Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit counter. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. CLK InputClock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data s pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ [4] InputZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition with data Asynchronou integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal s pull down. DQs, DQPX I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power supply inputs to the core of the device VSS Ground Ground for the core of the device. VSSQ I/O Ground Ground for the I/O circuitry. VDDQ I/O Power Supply Power supply for the I/O circuitry. MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. Note 4. Errata: The ZZ pin needs to be externally connected to ground. For more information, see “Errata” on page 32. Document Number: 38-05543 Rev. *S Page 6 of 38 Not Recommended for New Designs. InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled BWA, BWB, BWC, BWD Synchronous on the rising edge of CLK. CY7C1380D CY7C1380F CY7C1382D Pin Definitions (continued) TDO [5] I/O Description JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP packages. output Synchronous TDI [5] JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. input Synchronous TMS [5] JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. input Synchronous TCK [5] NC JTAGClock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Note 5. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata” on page 32. Document Number: 38-05543 Rev. *S Page 7 of 38 Not Recommended for New Designs. Name CY7C1380D CY7C1380F CY7C1382D All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). CY7C1380D/CY7C1380F/CY7C1382D supports secondary cache in systems using a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence suits processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is enabled to propagate to the input of the output registers. At the rising edge of the next clock, the data is enabled to propagate through the output register and onto the data bus within 2.6 ns (250 MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state; its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tri-states immediately. Single Write Accesses Initiated by ADSP This access is initiated when both the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1, CE2, and CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. Document Number: 38-05543 Rev. *S The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. CY7C1380D/CY7C1380F/CY7C1382D provides byte write capability that is described in the write cycle descriptions table. Asserting the byte write enable input (BWE) with the selected byte write (BWX) input, selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. CY7C1380D/CY7C1380F/CY7C1382D is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, and CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. CY7C1380D/CY7C1380F/CY7C1382D is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences CY7C1380D/CY7C1380F/CY7C1382D provides a two-bit wraparound counter, fed by A1:A0, that implements an interleaved or a linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Page 8 of 38 Not Recommended for New Designs. Functional Overview CY7C1380D CY7C1380F CY7C1382D Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Address Table (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 (MODE = Floating or VDD) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 80 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 38-05543 Rev. *S Page 9 of 38 Not Recommended for New Designs. Interleaved Burst Address Table CY7C1380D CY7C1380F CY7C1382D Truth Table The Truth Table for CY7C1380D/CY7C1380F/CY7C1382D follows. [6, 7, 8, 9, 10] Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L–H Tri-state Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-state Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-state Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-state Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-state Sleep Mode, Power Down None X X X H X X X X X X Tri-state READ Cycle, Begin Burst External L H L L L X X X L L–H Q READ Cycle, Begin Burst External L H L L L X X X H L–H Tri-state WRITE Cycle, Begin Burst External L H L L H L X L X L–H D READ Cycle, Begin Burst External L H L L H L X H L L–H Q READ Cycle, Begin Burst External L H L L H L X H H L–H Tri-state READ Cycle, Continue Burst Next X X X L H H L H L L–H READ Cycle, Continue Burst Next X X X L H H L H H L–H Tri-state READ Cycle, Continue Burst Next H X X L X H L H L L–H READ Cycle, Continue Burst Next H X X L X H L H H L–H Tri-state WRITE Cycle, Continue Burst Next X X X L H H L L X L–H D WRITE Cycle, Continue Burst Next H X X L X H L L X L–H D READ Cycle, Suspend Burst Current X X X L H H H H L L–H Q READ Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-state READ Cycle, Suspend Burst Current H X X L X H H H L L–H READ Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-state WRITE Cycle, Suspend Burst Current X X X L H H H L X L–H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L–H D Q Q Q Notes 6. X = Don't Care, H = Logic HIGH, L = Logic LOW. 7. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05543 Rev. *S Page 10 of 38 Not Recommended for New Designs. Operation CY7C1380D CY7C1380F CY7C1382D Truth Table for Read/Write Function (CY7C1380D/CY7C1380F) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) H L H H H L Write Byte B – (DQB and DQPB) H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write The Truth Table for Read/Write for CY7C1382D follows. [11, 12] Function (CY7C1382D) GW BWE BWB BWA Read H H X X Read H L H H Write Byte A – (DQA and DQPA) H L H L Write Byte B – (DQB and DQPB) H L L H Write Bytes B, A H L L L Write All Bytes H L L L Write All Bytes L X X X Notes 11. X = Don't Care, H = Logic HIGH, L = Logic LOW. 12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. Document Number: 38-05543 Rev. *S Page 11 of 38 Not Recommended for New Designs. The Truth Table for Read/Write for CY7C1380D/CY7C1380F follows. [11, 12] CY7C1380D CY7C1380F CY7C1382D The CY7C1380F incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. CY7C1380F contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. Instruction Register Test Access Port (TAP) When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 14. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Identification Codes on page 18). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 15. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 19 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 18. Note 13. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata” on page 32. Document Number: 38-05543 Rev. *S Page 12 of 38 Not Recommended for New Designs. IEEE 1149.1 Serial Boundary Scan (JTAG [13]) CY7C1380D CY7C1380F CY7C1382D Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in Identification Codes on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail in this section. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. EXTEST The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data is shifted in. The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift-DR controller state. IDCODE The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. The SAMPLE Z command places all SRAM outputs into a high Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. As there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. Document Number: 38-05543 Rev. *S PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at Bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 13 of 38 Not Recommended for New Designs. TAP Instruction Set CY7C1380D CY7C1380F CY7C1382D TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 EXIT1-DR 0 1 Not Recommended for New Designs. 0 0 1 0 The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 38-05543 Rev. *S Page 14 of 38 CY7C1380D CY7C1380F CY7C1382D TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 S election TDO Circuitr y Not Recommended for New Designs. Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS Document Number: 38-05543 Rev. *S TAP CONTROLLER Page 15 of 38 CY7C1380D CY7C1380F CY7C1382D TAP Timing Figure 3. TAP Timing Test Clock (TCK) t t TH t TMSS t TMSH t TDIS t TDIH TL t CYC Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range Parameter [14, 15] Description Min Max Unit 50 – ns Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH time 20 – ns tTL TCK Clock LOW time 20 – ns tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 – ns tTMSH TMS Hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns Output Times Setup Times Hold Times Notes 14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 15. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 38-05543 Rev. *S Page 16 of 38 Not Recommended for New Designs. Test Mode Select (TMS) CY7C1380D CY7C1380F CY7C1382D 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels ............................................... VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 50Ω 50Ω TDO TDO Z O= 50 Ω Z O= 50 Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [16] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Test Conditions Min Max Unit IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V IOH = –100 µA IOL = 8.0 mA IOL = 100 µA Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V VDDQ = 3.3 V – 0.4 V VDDQ = 2.5 V – 0.4 V VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.3 0.8 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA Note 16. All voltages referenced to VSS (GND). Document Number: 38-05543 Rev. *S Page 17 of 38 Not Recommended for New Designs. 1.25V CY7C1380D CY7C1380F CY7C1382D Identification Register Definitions CY7C1380F (512K × 36) 000 Device Depth (28:24) [17] 01011 Device Width (23:18) 165-ball FBGA 000000 Cypress Device ID (17:12) 100101 Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) 1 Description Describes the version number. Reserved for internal use. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary Scan Order (165-ball FBGA package) 89 Identification Codes Code Description EXTEST Instruction 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 17. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05543 Rev. *S Page 18 of 38 Not Recommended for New Designs. Instruction Field Revision Number (31:29) CY7C1380D CY7C1380F CY7C1382D Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Note 18. Balls which are NC (No Connect) are pre-set LOW. 19. Bit# 89 is pre-set HIGH. Document Number: 38-05543 Rev. *S Page 19 of 38 Not Recommended for New Designs. 165-ball BGA [18, 19] CY7C1380D CY7C1380F CY7C1382D Maximum Ratings DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD Range Ambient Temperature DC Voltage Applied to Outputs in tri-state ..........................................–0.5 V to VDDQ + 0.5 V Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [20, 21] Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage [20] Test Conditions Min IX Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V – 0.4 V for 3.3 V I/O, IOL = 8.0 mA for 2.5 V I/O, IOL = 1.0 mA VIL Max – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input Leakage Current except ZZ GND  VI  VDDQ and MODE –5 5 A Input Current of MODE –30 – A 5 A Input LOW Voltage [20] Input = VSS Input = VDD Input Current of ZZ –5 Input = VSS Input = VDD – A 30 A IOZ Output Leakage Current GND  VI  VDDQ, Output Disabled –5 5 A IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz – 350 mA 5.0-ns cycle, 200 MHz – 300 mA 6.0-ns cycle, 167 MHz – 275 mA VDD = Max, Device Deselected, 4.0-ns cycle, VIN  VIH or VIN  VIL, 250 MHz f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz – 160 mA – 150 mA 6.0-ns cycle, 167 MHz – 140 mA ISB1 Automatic CE Power Down Current – TTL Inputs Notes 20. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 21. TPower up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05543 Rev. *S Page 20 of 38 Not Recommended for New Designs. Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. CY7C1380D CY7C1380F CY7C1382D Electrical Characteristics (continued) Parameter [20, 21] Description Test Conditions Min Max Unit ISB2 Automatic CE Power Down Current – CMOS Inputs VDD = Max, Device Deselected, All speeds VIN  0.3 V or VIN > VDDQ – 0.3 V, f = 0 – 70 mA ISB3 Automatic CE Power Down Current – CMOS Inputs VDD = Max, Device Deselected, VIN  0.3 V or VIN > VDDQ – 0.3 V, f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz – 135 mA 5.0-ns cycle, 200 MHz – 130 mA 6.0-ns cycle, 167 MHz – 125 mA – 80 mA ISB4 Automatic CE Power Down Current – TTL Inputs VDD = Max, Device Deselected, All speeds VIN  VIH or VIN  VIL, f = 0 Capacitance Parameter [22] Description CIN Input capacitance CCLK Clock input capacitance CIO Input/Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 100-pin TQFP 165-ball FBGA Unit Package Package 5 9 pF 5 9 pF 5 9 pF Thermal Resistance Parameter [22] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 100-pin TQFP 165-ball FBGA Unit Package Package 28.66 20.7 °C/W 4.08 4.0 °C/W Note 22. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05543 Rev. *S Page 21 of 38 Not Recommended for New Designs. Over the Operating Range CY7C1380D CY7C1380F CY7C1382D AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms R = 317  3.3 V OUTPUT OUTPUT RL = 50  Z0 = 50  GND 5 pF R = 351  VT = 1.5 V INCLUDING JIG AND SCOPE (a) 2.5 V I/O Test Load OUTPUT RL = 50  Z0 = 50  VT = 1.25 V (a) Document Number: 38-05543 Rev. *S 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE  1 ns (b) GND 5 pF R = 1538  (b) 90% 10% 90%  1 ns R = 1667  2.5 V OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90%  1 ns  1 ns (c) Page 22 of 38 Not Recommended for New Designs. 3.3 V I/O Test Load CY7C1380D CY7C1380F CY7C1382D Switching Characteristics Over the Operating Range Parameter [23, 24] tPOWER 250 MHz Description VDD(typical) to the first Access [25] 200 MHz 167 MHz Unit Min Max Min Max Min Max 1 – 1 – 1 – ms tCYC Clock Cycle Time 4.0 – 5 – 6 – ns tCH Clock HIGH 1.7 – 2.0 – 2.2 – ns tCL Clock LOW 1.7 – 2.0 – 2.2 – ns Output Times tCO Data Output Valid After CLK Rise – 2.6 – 3.0 – 3.4 ns tDOH Data Output Hold After CLK Rise 1.0 – 1.3 – 1.3 – ns 1.0 – 1.3 – 1.3 – ns – 2.6 – 3.0 – 3.4 ns – 2.6 – 3.0 – 3.4 ns 0 – 0 – 0 – ns – 2.6 – 3.0 – 3.4 ns [26, 27, 28] tCLZ Clock to Low-Z tCHZ Clock to High-Z [26, 27, 28] tOEV OE LOW to Output Valid tOELZ tOEHZ OE LOW to Output Low-Z [26, 27, 28] OE HIGH to Output High-Z [26, 27, 28] Setup Times tAS Address Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tADS ADSC, ADSP Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tADVS ADV Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tWES GW, BWE, BWX Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tDS Data Input Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tCES Chip Enable SetUp Before CLK Rise 1.2 – 1.4 – 1.5 – ns tAH Address Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tADH ADSP, ADSC Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tADVH ADV Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tWEH GW, BWE, BWX Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tDH Data Input Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tCEH Chip Enable Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns Hold Times Notes 23. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 24. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted. 25. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 26. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage. 27. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 28. This parameter is sampled and not 100% tested. Document Number: 38-05543 Rev. *S Page 23 of 38 Not Recommended for New Designs. Clock CY7C1380D CY7C1380F CY7C1382D Switching Waveforms Figure 5. Read Cycle Timing [29] t CYC CLK t t ADS CH t CL t ADH t ADS Not Recommended for New Designs. ADSP tADH ADSC t AS tAH A1 ADDRESS A2 t WES A3 Burst continued with new base address tWEH GW, BWE, BWx t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05543 Rev. *S Page 24 of 38 CY7C1380D CY7C1380F CY7C1382D Switching Waveforms (continued) Figure 6. Write Cycle Timing [30, 31] t CYC CLK tCH t ADS tCL tADH ADSP ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES tWEH GW t CES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE t DS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) ata Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 30. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 31. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 38-05543 Rev. *S Page 25 of 38 Not Recommended for New Designs. t ADS CY7C1380D CY7C1380F CY7C1382D Switching Waveforms (continued) Figure 7. Read/Write Cycle Timing [32, 33, 34] tCYC CLK tCL tCH t ADS tADH t AS tAH ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO tDH t OELZ Data In (D) High-Z tOEHZ tCLZ Data Out (Q) High-Z Q(A1) D(A3) D(A5) Q(A4) Q(A2) Back-to-Back READs Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) D(A6) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 32. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 33. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 34. GW is HIGH. Document Number: 38-05543 Rev. *S Page 26 of 38 Not Recommended for New Designs. ADSP CY7C1380D CY7C1380F CY7C1382D Switching Waveforms (continued) Figure 8. ZZ Mode Timing [35, 36] CLK t ZZ ZZREC ZZI SUPPLY I t DDZZ ALL INPUTS RZZI Not Recommended for New Designs. I t t ZZ DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 35. Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device. 36. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05543 Rev. *S Page 27 of 38 CY7C1380D CY7C1380F CY7C1382D Ordering Information The below table lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (MHz) MPN Status Package Diagram NRND 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1380D-167AXI [37] 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial CY7C1380F-167BZI [37] 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Ordering Code 250 CY7C1380D-250AXC [37] 200 [37] CY7C1380D-200AXC Part and Package Type Operating Range 167 CY7C1380D-167AXC [37] CY7C1382D-167AXC [37] Ordering Code Definitions CY 7 C 138X X - XXX XX X X Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = A or BZ A = 100-pin TQFP BZ = 165-ball FPBGA Frequency Range: XXX = 250 MHz or 200 MHz or 167 MHz Die Revision: X = D or F D  90 nm F  90nm errata fix PCN084636 Part Identifier: 138X = 1380 or 1382 1380 = SCD, 512 K × 36 (18 Mb) 1382 = SCD, 1 Mb × 18 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Note 37. These MPNs are not recommended for new designs. Document Number: 38-05543 Rev. *S Page 28 of 38 Not Recommended for New Designs. CY7C1382D-200AXC [37] CY7C1380D CY7C1380F CY7C1382D Package Diagrams Not Recommended for New Designs. Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *E Document Number: 38-05543 Rev. *S Page 29 of 38 CY7C1380D CY7C1380F CY7C1382D Package Diagrams (continued) Not Recommended for New Designs. Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 38-05543 Rev. *S Page 30 of 38 CY7C1380D CY7C1380F CY7C1382D Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor FBGA Fine-Pitch Ball Grid Array °C degree Celsius I/O Input/Output MHz megahertz JTAG Joint Test Action Group µA microampere LSB Least Significant Bit mA milliampere MSB Most Significant Bit mm millimeter ms millisecond OE Output Enable SRAM Static Random Access Memory TCK Test Clock TMS Test Mode Select TDI Test Data-In TDO Test Data-Out TQFP Thin Quad Flat Pack TTL Transistor-Transistor Logic Document Number: 38-05543 Rev. *S Symbol Unit of Measure ns nanosecond  ohm % percent pF picofarad V volt W watt Not Recommended for New Designs. Acronyms Page 31 of 38 CY7C1380D CY7C1380F CY7C1382D Errata This section describes the Ram9 Sync ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions. Part Numbers Affected Density & Revision Package Type Operating Range 18Mb-Ram9 Synchronous SRAMs: CY7C138*D, CY7C138*F 100-pin TQFP Commercial/ Industrial 165-ball FBGA Industrial All of the devices in the Ram9 18Mb Sync family are qualified and available in production quantities. Ram9 Sync ZZ Pin & JTAG Issues Errata Summary The following table defines the errata applicable to available Ram9 18Mb Sync family devices. Item Issues Description Device Fix Status 1. ZZ Pin When asserted HIGH, the ZZ pin places device in a “sleep” condition with data integrity preserved.The ZZ pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 18M-Ram9 (90 nm) For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue. 2. JTAG Functionality During JTAG test mode, the Boundary scan circuitry does not perform as described in the datasheet.However, it is possible to perform the JTAG test with these devices in “BYPASS mode”. 18M-Ram9 (90 nm) This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability. Document Number: 38-05543 Rev. *S Page 32 of 38 Not Recommended for New Designs. Product Status CY7C1380D CY7C1380F CY7C1382D ■ PROBLEM DEFINITION The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the SRAM. ■ TRIGGER CONDITIONS Device operated with ZZ pin left floating. ■ SCOPE OF IMPACT When the ZZ pin is left floating, the device delivers incorrect data. ■ WORKAROUND Tie the ZZ pin externally to ground. ■ FIX STATUS For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue. 2. JTAG Functionality ■ PROBLEM DEFINITION The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform incorrectly by delivering the incorrect data or the incorrect scan chain length. ■ TRIGGER CONDITIONS Several conditions can trigger this failure mode. 1. The device can deliver an incorrect length scan chain when operating in JTAG mode. 2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode. 3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation. ■ SCOPE OF IMPACT The device fails for JTAG test. This does not impact the normal functionality of the device. ■ WORKAROUND 1.Perform JTAG testing with these devices in “BYPASS mode”. 2.Do not use JTAG test. ■ FIX STATUS This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability. Document Number: 38-05543 Rev. *S Page 33 of 38 Not Recommended for New Designs. 1. ZZ Pin Issue CY7C1380D CY7C1380F CY7C1382D Document History Page Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Document Number: 38-05543 Rev. ECN No. Submission Date Orig. of Change ** 254515 See ECN RKF New data sheet. *A 288531 See ECN SYT Updated Selection Guide (Removed 225 MHz and 133 MHz frequencies related information). Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Edited description for non-compliance with 1149.1). Updated Electrical Characteristics (Removed 225 MHz and 133 MHz frequencies related information). Updated Switching Characteristics (Removed 225 MHz and 133 MHz frequencies related information). Updated Ordering Information (Added Pb-free information for 100-pin TQFP, 119-ball BGA and 165-ball FBGA packages) and added comment for ‘Pb-free BG packages availability’ below the Ordering Information. *B 326078 See ECN PCI Updated Pin Configurations (Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard). Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Updated TAP Instruction Set (Updated OVERVIEW (description), updated EXTEST (description), added EXTEST Output Bus Tri-State)). Updated Identification Register Definitions (Splitted Device Width (23:18) into two rows (one for 119-ball BGA and another for 165-ball FBGA), retained the same values of 165-ball FBGA and changed the values from 000000 to 101000 for 119-ball BGA) Updated Electrical Characteristics (Modified Test Conditions for VOL, VOH parameters). Updated Thermal Resistance (Changed JA and JC for 100-pin TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively, changed JA and JC for 119-ball BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively, changed JA and JC for 165-ball FBGA Package from 46 and 3 C/W to 20.7 and 4.0 C/W respectively). Updated Ordering Information (Updated part numbers) and removed comment of ‘Pb-free BG packages availability’ below the Ordering Information. *C 416321 See ECN NXR Changed status from Preliminary to Final. Changed address of Cypress Semiconductor Corporation from “3901 North First Street” to “198 Champion Court”. Updated Electrical Characteristics (Changed the description of IX parameter from Input Load Current to Input Leakage Current, changed the minimum and maximum values of IX parameter (corresponding to Input Current of MODE) from –5 A and 30 A to –30 A and 5 A, changed the minimum and maximum values of IX parameter (corresponding to Input current of ZZ) from –30 A and 5 A to –5 A and 30 A, updated Note 21). Updated Ordering Information (Updated part numbers) and replaced Package Name column with Package Diagram in the Ordering Information table. *D 475009 See ECN VKN Updated TAP AC Switching Characteristics (Changed minimum values of tTH, and tTL parameters from 25 ns to 20 ns, and maximum value of tTDOV parameter from 5 ns to 10 ns). Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND). Updated Ordering Information (Updated part numbers). *E 776456 See ECN VKN Updated Features (Included CY7C1380F/CY7C1382F related information). Updated Functional Description (Included CY7C1380F/CY7C1382F related information). Document Number: 38-05543 Rev. *S Page 34 of 38 Not Recommended for New Designs. Description of Change CY7C1380D CY7C1380F CY7C1382D Document History Page (continued) Rev. ECN No. Submission Date Orig. of Change Description of Change *E (cont.) 776456 See ECN VKN Updated Logic Block Diagram – CY7C1380D/CY7C1380F (Included CY7C1380F related information, added the Note “CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and referred the same note in the title). Updated Logic Block Diagram – CY7C1382D/CY7C1382F (Included CY7C1382F related information, added the Note “CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and referred the same note in the title). Updated Pin Configurations (Included CY7C1380F/CY7C1382F related information). Updated Functional Overview (Included CY7C1380F/CY7C1382F related information). Updated Truth Table (Included CY7C1380F/CY7C1382F related information). Updated Truth Table for Read/Write (Included CY7C1380F related information). Updated Truth Table for Read/Write (Included CY7C1382F related information). Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Included CY7C1380F/CY7C1382F related information). Updated Identification Register Definitions (Included CY7C1380F/CY7C1382F related information). Updated Ordering Information (Updated part numbers). *F 2648065 01/27/09 VKN / PYRS Updated Ordering Information (To include CY7C1380F/CY7C1382F in 100-pin TSOP package and 165-ball FBGA package) and modified text on top of the Ordering information table. *G 2897120 03/22/2010 NJY Updated Ordering Information (Removed inactive parts). Updated Package Diagrams. *H 3067398 10/20/10 NJY Updated Ordering Information (The part CY7C1380F-167BGC is found to be in “EOL-Prune” state in Oracle PLM and therefore, it has been removed) and added Ordering Code Definitions. *I 3159479 02/01/2011 NJY Added Acronyms and Units of Measure. Updated Package Diagrams. Minor edits. Updated to new template. *J 3192403 03/10/2011 NJY Updated to new template. *K 3210400 03/30/11 NJY Updated Ordering Information (Removed pruned part CY7C1380D-167BZC from the ordering information table). *L 3575733 04/09/2012 Document Number: 38-05543 Rev. *S NJY / PRIT Updated Features (Removed CY7C1382F related information, removed 165-ball FBGA package related information for CY7C1382D, removed 100-pin TQFP package related information for CY7C1380F, removed 119-ball BGA package related information). Updated Functional Description (Removed the Note “For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.” and its reference, removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip enable.” and its reference). Updated Logic Block Diagram – CY7C1380D/CY7C1380F (Removed the Note “CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and its reference). Updated Logic Block Diagram – CY7C1382D (Removed CY7C1382F related information, removed the Note “CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and its reference). Page 35 of 38 Not Recommended for New Designs. Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Document Number: 38-05543 CY7C1380D CY7C1380F CY7C1382D Document History Page (continued) Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Document Number: 38-05543 Rev. ECN No. Submission Date *L (cont.) 3575733 04/09/2012 *M 3945784 03/27/2013 PRIT Updated Package Diagrams: spec 51-85180 – Changed revision from *E to *F. *N 3977530 04/23/2013 PRIT Added Errata. *O 4068739 07/20/2013 PRIT Added Errata footnotes (Note 1, 2, 3, 4, 5, 13). Updated Pin Configurations: Added Note 1 and referred the same note in Figure 1. Added Note 2, 3 and referred the same note in Figure 2. Updated Pin Definitions: Added Note 4 and referred the same note in ZZ pin. Added Note 5 and referred the same note in TDO, TDI, TMS, TCK pins. Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]): Added Note 13 and referred the same note in JTAG in the heading. Updated Errata. Updated to new template. *P 4150971 10/08/2013 PRIT Updated Errata. *Q 4569232 11/14/2014 PRIT Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams: spec 51-85050 – Changed revision from *D to *E. *R 4739641 04/24/2015 PRIT Updated to new template. Completing Sunset Review. Document Number: 38-05543 Rev. *S Orig. of Change NJY / PRIT Updated Pin Configurations (Removed CY7C1382F related information, removed 119-ball BGA package related information, removed 100-pin TQFP package related information for CY7C1380F, removed 165-ball FBGA package related information for CY7C1382D, removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip enable.” and its reference). Updated Functional Overview (Removed CY7C1382F related information). Updated Truth Table (Removed CY7C1382F related information). Updated Truth Table for Read/Write (Removed CY7C1382F related information). Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Removed CY7C1380D, CY7C1382D, and CY7C1382F related information). Updated Identification Register Definitions (Removed CY7C1380D, CY7C1382D, and CY7C1382F related information, removed 119-ball BGA package related information). Updated Scan Register Sizes (Removed 119-ball BGA package related information). Removed Boundary Scan Order (Corresponding to 119-ball BGA). Updated Capacitance (Removed 119-ball BGA package related information). Updated Thermal Resistance (Removed 119-ball BGA package related information). Updated Package Diagrams (Removed 119-ball BGA package related information). Page 36 of 38 Not Recommended for New Designs. Description of Change CY7C1380D CY7C1380F CY7C1382D Document History Page (continued) Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Document Number: 38-05543 ECN No. Submission Date Orig. of Change *S 5190429 03/29/2016 PRIT Document Number: 38-05543 Rev. *S Description of Change Added watermark “Not Recommended for New Designs.” across the document. Updated Ordering Information: No change in part numbers. Added a column “MPN Status”. Added Note 37 and referred the same note in all MPNs. Updated Package Diagrams: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. Page 37 of 38 Not Recommended for New Designs. Rev. CY7C1380D CY7C1380F CY7C1382D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface Lighting & Power Control cypress.com/interface cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/memory cypress.com/psoc cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-05543 Rev. *S Revised March 29, 2016 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Page 38 of 38 Not Recommended for New Designs. Products