CY7C1381D-100BGXI

PRELIMINARY CY7C1381D CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Features • Supports 133-MHz bus operations • 512K × 36/1M × 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output time — 6.5 ns (133-MHz version) — 8.5 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard lead-free 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages • JTAG boundary scan for BGA and fBGA packages • “ZZ” Sleep Mode option Functional Description[1] The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1381D/CY7C1383D allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1381D/CY7C1383D operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 210 70 100 MHz 8.5 175 70 Unit ns mA mA Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05544 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 2, 2004 PRELIMINARY 1 CY7C1381D CY7C1383D Logic Block Diagram – CY7C1381D (512K x 36) A0, A1, A ADDRESS REGISTER A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD BWD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BWA BWE GW CE1 CE2 CE3 OE DQA, DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BWB BYTE WRITE REGISTER BWC MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL 2 Logic Block Diagram – CY7C1383D (1 Mbit x 18) A0,A1,A MODE ADDRESS REGISTER A[1:0] ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER BWB MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS BWA BWE GW DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER INPUT REGISTERS DQs DQPA DQPB CE1 CE2 CE3 OE ENABLE REGISTER ZZ SLEEP CONTROL Document #: 38-05544 Rev. *A Page 2 of 29 PRELIMINARY Pin Configurations 100-pin TQFP Pinout A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1381D CY7C1383D 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1381D (512K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1383D (1M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A MODE A A A A A1 A0 NC NC VSS VDD Document #: 38-05544 Rev. *A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 29 PRELIMINARY Pin Configurations (continued) 119-ball BGA (1 Chip Enable with JTAG) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A A A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS CY7C1381D (512K x 36) 3 4 5 A A ADSP A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ CY7C1381D CY7C1383D CY7C1383D (1M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A A A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS NC VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC TCK 5 A A A VSS VSS VSS NC VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Document #: 38-05544 Rev. *A Page 4 of 29 PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip Enable) CY7C1381D (512K x 36) CY7C1381D CY7C1383D 1 A B C D E F G H J K L M N P R NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A0 A CY7C1383D (1M x 18) 1 A B C D E F G H J K L M N P R NC / 288M NC NC NC NC NC NC VSS DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A1 A0 A A Document #: 38-05544 Rev. *A Page 5 of 29 PRELIMINARY Pin Definitions Name A0, A1 , A BWA, BWB BWC, BWD GW CLK CE1 CE2 I/O InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description CY7C1381D CY7C1383D Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D]and BWE). Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH.CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Power supply inputs to the core of the device. Ground for the core of the device. CE3[2] OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous BWE ZZ InputSynchronous InputAsynchronous I/OSynchronous DQs DQPX MODE I/OSynchronous Input-Static VDD VDDQ VSS Power Supply Ground I/O Power Supply Power supply for the I/O circuitry. Document #: 38-05544 Rev. *A Page 6 of 29 PRELIMINARY Pin Definitions (continued) Name VSSQ TDO I/O I/O Ground Ground for the I/O circuitry. Description CY7C1381D CY7C1383D JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock – Ground/DNU Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die. This pin can be connected to Ground or should be left floating. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX)are ignored during this first clock cycle. If the write inputs are asserted active ( see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.Byte writes are allowed. All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. TDI TMS TCK NC VSS/DNU Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1381D/CY7C1383D supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Burst Sequences The CY7C1381D/CY7C1383D provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst Document #: 38-05544 Rev. *A Page 7 of 29 PRELIMINARY order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Sleep Mode CY7C1381D CY7C1383D Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Fourth Address A1: A0 11 00 01 10 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max. 80 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns Truth Table [ 3, 4, 5, 6, 7] Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Sleep Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst ADDRESS Used CE1 CE2 CE3 ZZ None None None None None None External External External H L L L X X L L L X L X L X X H H H X X H X X X L L L L L L L L H L L L ADSP X L L H H X L L H ADSC L X X L L X X X L ADV WRITE X X X X X X X X X X X X X X X X X L OE X X X X X X L H X CLK DQ L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State X Tri-State L-H Q L-H Tri-State L-H D Notes: 3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05544 Rev. *A Page 8 of 29 PRELIMINARY Truth Table (continued)[ 3, 4, 5, 6, 7] Cycle Description Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS Used CE1 CE2 CE3 ZZ External External Next Next Next Next Next Next Current Current Current Current Current Current L L X X H H X H X X H H X H H H X X X X X X X X X X X X L L X X X X X X X X X X X X L L L L L L L L L L L L L L ADSP H H H H X X H X H H X X H X ADSC L L H H H H H H H H H H H H ADV WRITE X X L L L L L L H H H H H H H H H H H H L L H H H H L L CY7C1381D CY7C1383D OE L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H DQ Q Tri-State Q Tri-State Q L-H Tri-State L-H D L-H D L-H Q L-H Tri-State L-H Q L-H Tri-State L-H D L-H D Partial Truth Table for Read/Write[3, 8] Function (CY7C1381D) Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A ( DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Note: 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05544 Rev. *A Page 9 of 29 PRELIMINARY Truth Table for Read/Write[3,8] Function (CY7C1383D) Read Read Write Byte A – ( DQA and DQPA) Write Byte B – ( DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X CY7C1381D CY7C1383D BWA X H L H L X IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381D/CY7C1383D incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1381D/CY7C1383D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) Document #: 38-05544 Rev. *A Page 10 of 29 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register 210 CY7C1381D CY7C1383D state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. Document #: 38-05544 Rev. *A Page 11 of 29 PRELIMINARY The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus CY7C1381D CY7C1383D hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK) t TMSS 2 3 4 5 6 t TH t TMSH t TL t CYC Test Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED Document #: 38-05544 Rev. *A Page 12 of 29 PRELIMINARY TAP AC Switching Characteristics Over the operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 50 Description Min. CY7C1381D CY7C1383D Max. Unit ns MHz ns ns ns ns ns ns 20 25 25 5 0 5 5 5 5 5 5 ns ns ns 3.3V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V 2.5V TAP AC Test Conditions Input pulse levels ......................................... VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50Ω TDO Z O= 50Ω 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50Ω TDO Z O= 50Ω 20pF Notes: 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns Document #: 38-05544 Rev. *A Page 13 of 29 PRELIMINARY TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ IOH = –4.0 mA IOH = –1.0 mA IOH = –100 µA IOL = 8.0 mA IOL = 8.0 mA IOL = 100 µA Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 –0.3 –0.3 -5 Min. 2.4 2.0 2.9 2.1 CY7C1381D CY7C1383D Max. Unit V V V V 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 V V V V V V V V µA Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) [12] CY7C1381D (512K × 36) 000 01011 000001 100101 00000110100 1 CY7C1383D (1M × 18) 000 01011 000001 010101 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Instruction Bypass Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball fBGA package) Bit Size (×36) 3 1 32 85 89 Bit Size (×18) 3 1 32 85 89 Notes: 11. All voltages referenced to VSS (GND). 12. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device. Document #: 38-05544 Rev. *A Page 14 of 29 PRELIMINARY Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description CY7C1381D CY7C1383D Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05544 Rev. *A Page 15 of 29 PRELIMINARY 119-Ball BGA Boundary Scan Order [13, 14] CY7C1381D (256K × 36) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 B6 D4 B4 F4 M4 A5 K4 Bit# 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID E4 G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 K2 L1 M2 N1 P1 K1 L2 N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 CY7C1381D CY7C1383D CY7C1383D (512K × 18) Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 B6 D4 B4 F4 M4 A5 K4 Bit# 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID E4 G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 K2 L1 M2 N1 P1 K1 L2 N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal Notes: 13. Balls that are NC (No Connect) are Pre-Set LOW. 14. Bit# 85 is Pre-Set HIGH. Document #: 38-05544 Rev. *A Page 16 of 29 PRELIMINARY 165-Ball BGA Boundary Scan Order [13, 15] CY7C1381D (256K x 36) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball ID N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 Bit# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball ID A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 Bit# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 CY7C1381D CY7C1383D CY7C1381D (256Kx36) Ball ID K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Note: 15. Bit# 89 is Pre-Set HIGH. Document #: 38-05544 Rev. *A Page 17 of 29 PRELIMINARY 165-Ball BGA Boundary Scan Order [13, 15] CY7C1383D (512K x 18) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball ID N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 Bit# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball ID A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 Bit# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 CY7C1381D CY7C1383D CY7C1383D (512Kx18) Ball ID K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Document #: 38-05544 Rev. *A Page 18 of 29 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V CY7C1381D CY7C1383D Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C VDD VDDQ 3.3V – 5%/+10% 2.5V – 5% to VDD –40°C to +85°C Electrical Characteristics Over the Operating Range [16, 17] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[16] Input LOW Voltage[16] Input Load Test Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND ≤ VI ≤ VDDQ Input = VDD Input Current of ZZ IOZ IDD ISB1 ISB2 ISB3 ISB4 Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled VDD Operating Supply Current Automatic CE Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz All speeds –5 –30 5 5 210 175 140 120 70 mA Min. 3.135 3.135 2.375 2.4 2.0 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V µA µA 30 µA µA µA µA mA mA mA 2.0 1.7 –0.3 –0.3 –5 –5 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Input Current of MODE Input = VSS Max. VDD, Device Deselected, Automatic CE Power-down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—CMOS Inputs f = 0, inputs static Automatic CE Max. VDD, Device Deselected, Power-down VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, Current—CMOS Inputs f = fMAX, inputs switching Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz All Speeds 130 110 80 mA mA mA Notes: 16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD Document #: 38-05544 Rev. *A Page 19 of 29 PRELIMINARY Thermal Resistance[18] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. CY7C1381D CY7C1383D TQFP Package BGA Package fBGA Package Unit 31 6 45 7 46 3 °C/W °C/W ΘJA ΘJC Capacitance[18] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V TQFP Package 5 5 5 BGA Package 8 8 8 fBGA Package 9 9 9 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω R = 317Ω VDDQ 5 pF GND R = 351Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1ns VT = 1.5V (a) 2.5V I/O Test Load OUTPUT Z0 = 50Ω INCLUDING JIG AND SCOPE 2.5V ≤ 1ns (b) R = 1667Ω VDDQ (c) ALL INPUT PULSES 10% 90% 90% 10% ≤ 1ns OUTPUT RL = 50Ω VT = 1.25V 5 pF GND R =1538Ω (a) INCLUDING JIG AND SCOPE ≤ 1ns (b) (c) Switching Characteristics Over the Operating Range [20, 21] 133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS Address Set-up Before CLK Rise 1.5 1.5 ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[20, 21, 22] Clock to High-Z[20, 21, 22] OE LOW to Output Valid OE LOW to Output Low-Z[20, 21, 22] [20, 21, 22] 100 MHz Min. 1 10 2.5 2.5 Max. Unit ms ns ns ns 8.5 2.0 2.0 ns ns ns 5.0 3.8 0 5.0 ns ns ns ns Description VDD(Typical) to the first Clock Cycle Time Clock HIGH Clock LOW Access[19] Min. 1 7.5 2.1 2.1 Max. 6.5 2.0 2.0 0 0 4.0 4.0 3.2 0 OE HIGH to Output High-Z Document #: 38-05544 Rev. *A Page 20 of 29 PRELIMINARY Switching Characteristics Over the Operating Range (continued)[20, 21] 133 MHz Parameter tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Description ADSP, ADSC Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Min. 1.5 1.5 1.5 1.5 1.5 Max. CY7C1381D CY7C1383D 100 MHz Min. 1.5 1.5 1.5 1.5 1.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 18. Tested initially and after any design or process change that may affect these parameters. 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions Document #: 38-05544 Rev. *A Page 21 of 29 PRELIMINARY Timing Diagrams Read Cycle Timing[25] tCYC CY7C1381D CY7C1383D CLK t CH t CL tADS tADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 t WES t WEH A2 GW, BWE,BW X tCES t CEH Deselect Cycle CE t t ADVS ADVH ADV ADV suspends burst OE t OEV t CLZ t OEHZ t OELZ tCDV tDOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ DON’T CARE Note: 22. This parameter is sampled and not 100% tested. BURST READ UNDEFINED Document #: 38-05544 Rev. *A Page 22 of 29 PRELIMINARY Timing Diagrams (continued) [25, 26] 3 CY7C1381D CY7C1383D Write Cycle Timing t CYC CLK t CH t CL tADS tADH ADSP tADS tADH ADSC extends burst tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 tWES tWEH BWE, BWX t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t OEHZ D(A1) Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Notes: 23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 24. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05544 Rev. *A Page 23 of 29 PRELIMINARY Timing Diagrams (continued) Read/Write Cycle Timing[25, 27, 28] tCYC CY7C1381D CY7C1383D CLK t CH tADS tADH t CL ADSP ADSC tAS tAH ADDRESS A1 A2 A3 t t WES WEH A4 A5 A6 BWE, BWX tCES tCEH CE ADV OE tDS tDH tOELZ Data In (D) Data Out (Q) High-Z t OEHZ D(A3) tCDV D(A5) D(A6) Q(A1) Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Back-to-Back READs BURST READ UNDEFINED Notes: 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. 27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 28. GW is HIGH. Document #: 38-05544 Rev. *A Page 24 of 29 PRELIMINARY Timing Diagrams (continued) ZZ Mode Timing [29, 30] CLK t ZZ t ZZREC CY7C1381D CY7C1383D ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1381D-133AXC CY7C1383D-133AXC CY7C1381D-133BGC CY7C1383D-133BGC CY7C1381D-133BZC CY7C1383D-133BZC CY7C1381D-133BGXC CY7C1383D-133BGXC CY7C1381D-133BZXC CY7C1383D-133BZXC 100 CY7C1381D-100AXC CY7C1383D-100AXC CY7C1381D-100BGC CY7C1383D-100BGC CY7C1381D-100BZC CY7C1383D-100BZC CY7C1381D-100BGXC CY7C1383D-100BGXC CY7C1381D-100BZXC CY7C1383D-100BZXC BB165D BG119 BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Package Name A101 BG119 BB165D BG119 BB165D A101 BG119 Part and Package Type Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Commercial Operating Range Commercial Notes: 29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 30. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05544 Rev. *A Page 25 of 29 PRELIMINARY Ordering Information (continued) Speed (MHz) 100 Ordering Code CY7C1381D-100AXI CY7C1383D-100AXI CY7C1381D-100BGI CY7C1383D-100BGI CY7C1381D-100BZI CY7C1383D-100BZI CY7C1381D-100BGXI CY7C1383D-100BGXI CY7C1381D-100BZXI CY7C1383D-100BZXI BB165D BG119 BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG BG119 Package Name A101 Part and Package Type CY7C1381D CY7C1383D Operating Range Industrial Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (ordering Code:BGX) will be available in 2005. Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 16.00±0.20 14.00±0.10 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. 1.40±0.05 0.30±0.08 22.00±0.20 20.00±0.10 0.65 TYP. 30 31 50 51 12°±1° (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.10 R 0.08 MIN. 0.20 MAX. 0° MIN. 0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX. SEATING PLANE 0°-7° 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*A Document #: 38-05544 Rev. *A Page 26 of 29 PRELIMINARY Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1381D CY7C1383D 51-85115-*B Document #: 38-05544 Rev. *A Page 27 of 29 PRELIMINARY Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D CY7C1381D CY7C1383D 51-85180-** i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05544 Rev. *A Page 28 of 29 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05544 REV. ** *A ECN NO. 254518 288531 Issue Date See ECN See ECN Orig. of Change RKF SYT New data sheet Description of Change CY7C1381D CY7C1383D Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.1 Removed 117 Mhz Speed Bin Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA package Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Document #: 38-05544 Rev. *A Page 29 of 29