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CY7C1381KV33-100AXC

CY7C1381KV33-100AXC

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    LQFP100

  • 描述:

    IC SRAM 18MBIT PARALLEL 100TQFP

  • 数据手册
  • 价格&库存
CY7C1381KV33-100AXC 数据手册
CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) Features Functional Description ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381KV33/CY7C1381KVE33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball FBGA package. CY7C1383KV33/CY7C1383KVE33 available in JEDEC-standard Pb-free 100-pin TQFP. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option. ■ On-chip error correction code (ECC) to reduce soft error rate (SER) The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ CY7C1383KVE33 allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ CY7C1383KVE33 operates from a +3.3 V core power supply while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide Description Maximum access time Maximum operating current Cypress Semiconductor Corporation Document Number: 001-97888 Rev. *F • 198 Champion Court • 133 MHz 100 MHz Unit 6.5 8.5 ns × 18 129 114 mA × 36 149 134 mA San Jose, CA 95134-1709 • 408-943-2600 Revised February 16, 2018 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Logic Block Diagram – CY7C1381KV33 (512K × 36) ADDRESS REGISTER A0, A1, A A [1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQ D , DQP D DQ D , DQP D BW D BYTE BYTE WRITE REGISTER WRITE REGISTER DQ C , DQP C DQ C , DQP C BW C WRITE REGISTER WRITE REGISTER DQ B , DQP B MEMORY ARRAY DQ B , DQP B BW B SENSE AMPS OUTPUT BUFFERS DQs DQP A DQP B DQP C WRITE REGISTER DQP D WRITE REGISTER DQ A , DQP DQ A , DQP BW A BYTE A WRITE REGISTER BYTE BWE WRITE REGISTER INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE SLEEP Logic Block Diagram – CY7C1381KVE33 (512K × 36) ADDRESS REGISTER A0, A1, A A[1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQD, DQPD BWD BYTE WRITE REGISTER DQC, DQPC BWC BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BWB DQB, DQPB BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS ECC DECODER OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD WRITE REGISTER DQA, DQPA BWA BWE DQA, DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER GW ENABLE REGISTER CE1 CE2 ECC ENCODER INPUT REGISTERS CE3 OE ZZ SLEEP CONTROL Document Number: 001-97888 Rev. *F Page 2 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Logic Block Diagram – CY7C1383KV33 (1M × 18) A0,A1,A ADDRESS REGISTER A[1:0] MODE BURST Q1 COUNTER AND ADV Q0 DQ B ,DQP B BW B DQ A ,DQP A BW A DQ B ,DQP B WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQP A DQP B DQ A ,DQP A WRITE DRIVER BWE GW CE 1 CE 2 CE 3 ENABLE INPUT REGISTERS OE SLEEP CONTROL Logic Block Diagram – CY7C1383KVE33 (1M × 18) Document Number: 001-97888 Rev. *F Page 3 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 9 Single Read Accesses ................................................ 9 Single Write Accesses Initiated by ADSP ................... 9 Single Write Accesses Initiated by ADSC ................... 9 Burst Sequences ......................................................... 9 Sleep Mode ................................................................. 9 Interleaved Burst Address Table ............................... 10 Linear Burst Address Table ....................................... 10 ZZ Mode Electrical Characteristics ............................ 10 Truth Table ...................................................................... 11 Truth Table for Read/Write ............................................ 12 Truth Table for Read/Write ............................................ 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port (TAP) ............................................. 13 PERFORMING A TAP RESET .................................. 13 TAP REGISTERS ...................................................... 13 TAP Instruction Set ................................................... 14 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Timing ...................................................................... 17 TAP AC Switching Characteristics ............................... 17 3.3 V TAP AC Test Conditions ....................................... 18 3.3 V TAP AC Output Load Equivalent ......................... 18 2.5 V TAP AC Test Conditions ....................................... 18 2.5 V TAP AC Output Load Equivalent ......................... 18 Document Number: 001-97888 Rev. *F TAP DC Electrical Characteristics and Operating Conditions ............................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................. 21 Neutron Soft Error Immunity ......................................... 21 Electrical Characteristics ............................................... 21 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 AC Test Loads and Waveforms ..................................... 23 Switching Characteristics .............................................. 24 Timing Diagrams ............................................................ 25 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Package Diagrams .......................................................... 30 Acronyms ........................................................................ 32 Document Conventions ................................................. 32 Units of Measure ....................................................... 32 Document History Page ................................................. 33 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC® Solutions ...................................................... 34 Cypress Developer Community ................................. 34 Technical Support ..................................................... 34 Page 4 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable) CY7C1381KV33/CY7C1381KVE33 (512K × 36) Document Number: 001-97888 Rev. *F CY7C1383KV33/CY7C1383KVE33 (1M × 18) Page 5 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Pin Configurations (continued) Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable) CY7C1381KV33 (512K × 36) 1 A B C D E F G H J K L M N P NC/288M R 2 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 NC BWE ADSC ADV A NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS TCK A A A A A Document Number: 001-97888 Rev. *F VSS A0 Page 6 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Pin Definitions Name A0, A1, A I/O Description Input Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB, Input Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled BWC, BWD Synchronous on the rising edge of CLK. GW CLK Input Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is Synchronous conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). Input Clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 Input Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 Input Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Input Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data s pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments Synchronous the address in a burst cycle. ADSP Input Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE Input Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. ZZ Input ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data Asynchronou integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal s pull down. DQs I/O Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/O Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write Synchronous sequences, DQPX is controlled by BWX correspondingly. Document Number: 001-97888 Rev. *F Page 7 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Pin Definitions (continued) Name MODE VDD VDDQ VSS VSSQ I/O Description Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull-up. Power Supply Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. Ground Ground for the core of the device. I/O Ground Ground for the I/O circuitry. TDO JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is Output not being used, this pin can be left unconnected. This pin is not available on TQFP packages. Synchronous TDI JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being Input used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available Synchronous on TQFP packages. TMS JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being Input used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Synchronous TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. VSS/DNU Ground/DNU This pin can be connected to ground or can be left floating. Document Number: 001-97888 Rev. *F Page 8 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138 3KVE33 supports secondary cache in systems using a linear or interleaved burst sequence. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and later presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs with a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table for Read/Write on page 12 for appropriate states that indicate a write) on the next Document Number: 001-97888 Rev. *F clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. All I/O are tristated during a byte write. As this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core The information presented to DQ[A:D] is written into the specified address location. Byte writes are allowed. All I/O are tristated when a write is detected, even a byte write. Because this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Burst Sequences CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138 3KVE33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 9 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Interleaved Burst Address Table Linear Burst Address Table (MODE = Floating or VDD) (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 00 01 01 00 Fourth Address A1:A0 10 11 00 01 10 11 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 65 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-97888 Rev. *F Page 10 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Truth Table The truth table for CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 follows. [1, 2, 3, 4, 5] Cycle Description Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L–H Tri-State Deselected Cycle, Power Down None L L X L L X X X X L–H Tri-State Deselected Cycle, Power Down None L X H L L X X X X L–H Tri-State Deselected Cycle, Power Down None L L X L H L X X X L–H Tri-State Deselected Cycle, Power Down None X X H L H L X X X L–H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L–H D Read Cycle, Begin Burst External L H L L H L X H L L–H Q Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State Read Cycle, Continue Burst Next X X X L H H L H L L–H Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L–H Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L–H D Write Cycle, Continue Burst Next H X X L X H L L X L–H D Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L–H Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L–H D Write Cycle, Suspend Burst Current H X X L X H H L X L–H D Q Q Q Notes 1. X = Don't Care, H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-97888 Rev. *F Page 11 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Truth Table for Read/Write The truth table for CY7C1381KV33/CY7C1381KVE33 read/write follows. [6, 7] Function (CY7C1381KV33/CY7C1381KVE33) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A (DQA, DQPA) H L H H H L Write Byte B(DQB, DQPB) H L H H L H Write Bytes A, B (DQA, DQB, DQPA, DQPB) H L H H L L Write Byte C (DQC, DQPC) H L H L H H Write Bytes C, A (DQC, DQA, DQPC, DQPA) H L H L H L Write Bytes C, B (DQC, DQB, DQPC, DQPB) H L H L L H Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) H L H L L L Write Byte D (DQD, DQPD) H L L H H H Write Bytes D, A (DQD, DQA, DQPD, DQPA) H L L H H L Write Bytes D, B (DQD, DQA, DQPD, DQPA) H L L H L H Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L H L L Write Bytes D, B (DQD, DQB, DQPD, DQPB) H L L L H H Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) H L L L H L Truth Table for Read/Write The truth table for CY7C1383KV33/CY7C1383KVE33 read/write follows. [6, 7] Function (CY7C1383KV33/CY7C1383KVE33) GW BWE BWB BWA Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L L Write All Bytes H L L L Write All Bytes L X X X Read H H X X Read H L H H Write Byte A – (DQA and DQPA) H L H L Write Byte B – (DQB and DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X Notes 6. X=Don't Care, H = Logic HIGH, L = Logic LOW. 7. The table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. Document Number: 001-97888 Rev. *F Page 12 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Registers The CY7C1381KV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. Registers are connected between the TDI and TDO balls and allow data to be scanned in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. CY7C1381KV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO may be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 16. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Test Access Port (TAP) When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board level serial test path. Test Clock (TCK) Bypass Register The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction Codes on page 19). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state. Document Number: 001-97888 Rev. *F Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 20 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 19. Page 13 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in Instruction Codes on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state, when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction when it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift-DR controller state. there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data is shifted in. IDCODE BYPASS The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. EXTEST Output Bus Tri-State SAMPLE Z The boundary scan register has a special bit located at bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. The SAMPLE Z command places all SRAM outputs into a high Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but Document Number: 001-97888 Rev. *F IEEE standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 14 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 EXIT1-DR 0 1 0 1 0 The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-97888 Rev. *F Page 15 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS Document Number: 001-97888 Rev. *F TAP CONTROLLER Page 16 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 TAP Timing Figure 3. TAP Timing 1 2 Test Clock (TCK) 3 t t TH t TMSS t TMSH t TDIS t TDIH TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range Parameter [8, 9] Description Min Max Unit 50 – ns Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH Time 20 – ns tTL TCK Clock LOW Time 20 – ns tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 – ns tTMSH TMS Hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns Output Times Setup Times Hold Times Notes 8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 001-97888 Rev. *F Page 17 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels ............................................... VSS to 2.5 V Input rise and fall times (Slew Rate) ........................... 2 V/ns Input rise and fall time (Slew Rate) ............................. 2 V/ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O= 50 Ω Z O= 50 Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [10] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Test Conditions Max Unit IOH = –4.0 mA VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.3 0.8 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA Input HIGH Voltage Input LOW Voltage Input Load Current Min GND < VIN < VDDQ Note 10. All voltages referenced to VSS (GND). Document Number: 001-97888 Rev. *F Page 18 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Identification Register Definitions CY7C1381KV33 (512K × 36) Instruction Field Revision Number (31:29) 000 Device Depth (28:24) [11] 01011 Device Width (23:18) 165-ball FBGA Description Describes the version number. Reserved for internal use. 000001 Defines the memory type and architecture. Cypress Device ID (17:12) 100101 Defines the width and density. Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Instruction Bypass 3 Bypass 1 ID 32 Boundary Scan Order (165-ball FBGA package) 89 Instruction Codes Code Description EXTEST Instruction 000 Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 11. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 001-97888 Rev. *F Page 19 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Boundary Scan Order 165-ball FBGA [12, 13] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 89 Internal 29 F10 59 E1 30 E10 60 F1 Notes 12. Balls which are NC (No Connect) are pre-set LOW. 13. Bit# 89 is pre-set HIGH. Document Number: 001-97888 Rev. *F Page 20 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Maximum Ratings Operating Range Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Range Ambient Temperature Storage Temperature ............................... –65 °C to +150 °C Commercial Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Industrial Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V Neutron Soft Error Immunity Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA Parameter LSBU (Device without ECC) 0 °C to +70 °C VDD –40 °C to +85 °C Description 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Test Conditions Typ Logical Single-Bit Upsets 25 °C LSBU (Device with ECC) LMBU SEL VDDQ Max* Unit –2 V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ VDDQ 0.3 V, f=0 All speed grades × 18 – 65 × 36 – 70 Automatic CE Power-down Current – CMOS Inputs Max. VDD, Device Deselected, VIN  0.3 V or VIN > VDDQ 0.3 V, f = fMAX = 1/tCYC 100 MHz × 18 – 75 × 36 – 80 × 18 – 75 × 36 – 80 Max. VDD, Device Deselected, VIN  VIH or VIN  VIL, f=0 All speed grades × 18 – 65 × 36 – 70 Automatic CE Power-down Current – TTL Inputs Automatic CE Power-down Current – TTL Inputs Document Number: 001-97888 Rev. *F 100 MHz 133 MHz mA mA mA mA Page 22 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Capacitance Parameter Description CIN Input capacitance CCLK Clock input capacitance CIO Input/Output capacitance 100-pin TQFP 165-ball FBGA Unit Package Package Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 5 5 pF 5 5 pF 5 5 pF Thermal Resistance Parameter JA Description Test conditions follow With Still Air (0 m/s) standard test With Air Flow (1 m/s) methods and procedures for With Air Flow (3 m/s) measuring thermal -impedance, per EIA/JESD51. Thermal resistance (junction to ambient) JB Thermal resistance (junction to board) JC Thermal resistance (junction to case) 100-pin TQFP 165-ball FBGA Unit Package Package Test Conditions 37.95 17.34 C/W 33.19 14.33 C/W 30.44 12.63 C/W 24.07 8.95 C/W 8.36 3.50 C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317  3.3 V OUTPUT OUTPUT RL = 50  Z0 = 50  VT = 1.5 V (a) INCLUDING JIG AND SCOPE OUTPUT RL = 50  VT = 1.25 V (a) Document Number: 001-97888 Rev. *F R = 351  10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE  1 ns (b) GND 5 pF R = 1538  (b) 90% 10% 90%  1 ns R = 1667  2.5 V Z0 = 50  GND 5 pF 2.5 V I/O Test Load OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90%  1 ns  1 ns (c) Page 23 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Switching Characteristics Over the Operating Range Parameter [16, 17] tPOWER Description VDD(typical) to the first access [18] 133 MHz 100 MHz Unit Min Max Min Max 1 – 1 – ms Clock tCYC Clock cycle time 7.5 – 10 – ns tCH Clock HIGH 2.1 – 2.5 – ns tCL Clock LOW 2.1 – 2.5 – ns Output Times tCDV Data output valid after CLK rise – 6.5 – 8.5 ns tDOH Data output hold after CLK rise 2.0 – 2.0 – ns 2.0 – 2.0 – ns 0 4.0 0 5.0 ns – 3.2 – 3.8 ns 0 – 0 – ns – 4.0 – 5.0 ns [19, 20, 21] tCLZ Clock to low Z tCHZ Clock to high Z [19, 20, 21] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [19, 20, 21] OE HIGH to output high Z [19, 20, 21] Setup Times tAS Address setup before CLK rise 1.5 – 1.5 – ns tADS ADSP, ADSC setup before CLK rise 1.5 – 1.5 – ns tADVS ADV setup before CLK rise 1.5 – 1.5 – ns tWES GW, BWE, BW[A:D] setup before CLK rise 1.5 – 1.5 – ns tDS Data input setup before CLK rise 1.5 – 1.5 – ns tCES Chip enable setup 1.5 – 1.5 – ns tAH Address hold after CLK rise 0.5 – 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – 0.5 – ns tWEH GW, BWE, BW[A:D] hold after CLK rise 0.5 – 0.5 – ns tADVH ADV hold after CLK rise 0.5 – 0.5 – ns tDH Data input hold after CLK rise 0.5 – 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – 0.5 – ns Hold Times Notes 16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 17. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted. 18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage 20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system condition. 21. This parameter is sampled and not 100% tested. Document Number: 001-97888 Rev. *F Page 24 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Timing Diagrams Figure 5. Read Cycle Timing [22] tCYC CLK t t ADS CH t CL tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t GW, BWE,BW WES t WEH X t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED . Note 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-97888 Rev. *F Page 25 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Timing Diagrams (continued) Figure 6. Write Cycle Timing [23, 24] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED . Notes 23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 001-97888 Rev. *F Page 26 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Timing Diagrams (continued) Figure 7. Read/Write Cycle Timing [25, 26, 27] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A4) Q(A2) Back-to-Back READs D(A6) t CDV Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED . Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 27. GW is HIGH. Document Number: 001-97888 Rev. *F Page 27 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Timing Diagrams (continued) Figure 8. ZZ Mode Timing [28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 28. Device must be deselected when entering ZZ mode. See Truth Table on page 11 for all possible signal conditions to deselect the device. 29. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-97888 Rev. *F Page 28 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Ordering Code CY7C1381KV33-133AXC Package Diagram Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial CY7C1383KV33-133AXC CY7C1381KVE33-133AXI lndustrial CY7C1381KV33-133AXI CY7C1383KVE33-133AXI CY7C1383KV33-133AXI 100 CY7C1381KV33-100AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1381KV33-100BZXI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free lndustrial Ordering Code Definitions CY 7 C 13XX KV E 33 - XXX XX X X Temperature range: X = C or I C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C X = Pb-free; X Absent = Leaded Package Type: XX = A or BZ A = 100-pin TQFP BZ = 165-ball FBGA Speed Grade: XXX = 100 MHz or 133 MHz 33 = 3.3 V VDD E = Device with ECC; E Absent = Device without ECC Process Technology: K =65 nm Part Identifier: 13XX = 1381 or 1383 1381 = FT, 512Kb × 36 (18Mb) 1383 = FT, 1Mb × 18 (18Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-97888 Rev. *F Page 29 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 ș2 ș1 ș SYMBOL DIMENSIONS MIN. NOM. MAX. A 1.60 A1 0.05 A2 1.35 1.40 1.45 0.15 NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH. D 15.80 16.00 16.20 MOLD PROTRUSION/END FLASH SHALL D1 13.90 14.00 14.10 E 21.80 22.00 22.20 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE. BODY LENGTH DIMENSIONS ARE MAX PLASTIC E1 19.90 20.00 20.10 R1 0.08 0.20 R2 0.08 0.20 ș 0° 7° ș1 0° ș2 11° 13° 12° 0.20 c b 0.22 0.30 0.38 L 0.45 0.60 0.75 L1 L2 L3 e BODY SIZE INCLUDING MOLD MISMATCH. 3. JEDEC SPECIFICATION NO. REF: MS-026. 1.00 REF 0.25 BSC 0.20 0.65 TYP 51-85050 *G Document Number: 001-97888 Rev. *F Page 30 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Package Diagrams (continued) Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-97888 Rev. *F Page 31 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance MHz megahertz FBGA Fine-Pitch Ball Grid Array µA microampere I/O Input/Output mA milliampere JEDEC Joint Electron Devices Engineering Council mm millimeter JTAG Joint Test Action Group ms millisecond LMBU Logical Multi-Bit Upsets mV millivolt LSB Least Significant Bit ns nanosecond LSBU Logical Single-Bit Upsets  ohm MSB Most Significant Bit % percent OE Output Enable pF picofarad SEL Single Event Latch Up V volt SRAM Static Random Access Memory W watt TAP Test Access Port TCK Test Clock TDI Test Data-In TDO Test Data-Out TMS Test Mode Select TQFP Thin Quad Flat Pack TTL Transistor-Transistor Logic Document Number: 001-97888 Rev. *F Symbol Unit of Measure Page 32 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Document History Page Document Title: CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) Document Number: 001-97888 Rev. ECN No. Orig. of Change Submission Date *C 4983482 DEVM 10/26/2015 *D 5085859 DEVM 01/14/2016 Post to external web. *E 5333612 PRIT 07/01/2016 Updated Truth Table: Updated details in “CE3” column corresponding to fifth row of “Deselected Cycle, Power Down”. Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC) parameter. Updated to new template. *F 6073260 CNX 02/16/2018 Updated Package Diagrams: spec 51-85050 – Changed revision from *E to *G. Updated to new template. Document Number: 001-97888 Rev. *F Description of Change Changed status from Preliminary to Final. Page 33 of 34 CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-97888 Rev. *F Revised February 16, 2018 Page 34 of 34
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