CY7C1382CV25-200BZC

380CV25 PRELIMINARY CY7C1380CV25 CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) • Automatic power-down available using ZZ mode or CE deselect • Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages • JTAG boundary scan for BGA packaging version (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1380CV25 and the CY7C1382CV25 are JEDEC standard JESD8-5 compatible. Functional Description The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. 225 MHz 2.8 325 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns mA mA 2.6 350 70 Cypress Semiconductor Corporation Document #: 38-05240 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 20, 2002 PRELIMINARY CY7C1380CV25 - 512K x 36 CLK ADV ADSC ADSP A[18:0] GW BWE BW d BWc D BWb D BWa CE1 CE2 CE3 D CY7C1380CV25 CY7C1382CV25 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS ENABLE CE REGISTER Q 17 19 19 17 D 512KX36 MEMORY ARRAY D Q Q Q 36 Q 36 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQa,b,c,d DPa,b CY7C1382CV25 - 1M X 18 CLK ADV ADSC ADSP A[19:0] GW BWE BW b BWa MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q 18 20 20 18 D 1M X 18 MEMORY ARRAY D Q CE1 CE2 CE3 18 D ENABLE CE CE REGISTER Q 18 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQa,b DPa,b Document #: 38-05240 Rev. *A Page 2 of 33 PRELIMINARY Pin Configurations 100-Pin TQFP Top View A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1380CV25 CY7C1382CV25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC,DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd NC,DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1380CV25 (512K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC,DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa NC,DQPa NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DPb NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1382CV25 (1M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD Document #: 38-05240 Rev. *A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 33 PRELIMINARY Pin Configurations (continued) 119-Ball BGA CY7C1380CV25 CY7C1382CV25 CY7C1380CV25 (512K x 36) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A A A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A 72M TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A 36M NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ CY7C1382CV25 (1M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC 72M VDDQ 2 A A A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD 36M TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Document #: 38-05240 Rev. *A Page 4 of 33 PRELIMINARY Pin Configurations (continued) 165-Ball Bump FBGA CY7C1380CV25 (512K x 36) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC DPc DQc DQc DQc DQc NC DQd DQd DQd DQd DPd NC MODE CY7C1380CV25 CY7C1382CV25 2 A A NC DQc DQc DQc DQc VSS DQd DQd DQd DQd NC 72M 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC 144M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A CY7C1382CV25 (1M x 18) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DPb NC MODE 2 A A NC DQb DQb DQb DQb VSS NC NC NC NC NC 72M 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A 144M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A Document #: 38-05240 Rev. *A Page 5 of 33 PRELIMINARY Pin Definitions Name A0 A1 A BWa BWb BWc BWd GW I/O InputSynchronous InputSynchronous Description CY7C1380CV25 CY7C1382CV25 Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. InputSynchronous InputSynchronous Input-Clock Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only) Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only) Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[X] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP a,b,c, and d are 1 bit wide. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only) Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only) Page 6 of 33 BWE CLK CE1 InputSynchronous InputSynchronous InputSynchronous InputAsynchronous CE2 CE3 OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous MODE Input-Pin ZZ DQa, DPa DQb, DPb DQc, DPc DQd, DPd InputAsynchronous I/OSynchronous TDO TDI JTAG serial output Synchronous JTAG serial input Synchronous Document #: 38-05240 Rev. *A PRELIMINARY Pin Definitions Name TMS TCK VDD VSS VDDQ VSSQ NC 36M 72M 144M I/O Test Mode Select Synchronous JTAG serial clock Power Supply Ground I/O Power Supply I/O Ground Description CY7C1380CV25 CY7C1382CV25 This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. (BGA Only) Serial clock to the JTAG circuit. (BGA Only) Power supply inputs to the core of the device. Should be connected to 2.5V ± 5% power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Ground for the I/O circuitry. Should be connected to ground of the system. No Connects.Pins are not internally connected. No Connects. Reserved for address expansion. Document #: 38-05240 Rev. *A Page 7 of 33 PRELIMINARY Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). The CY7C1380CV25/CY7C1382CV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWa,b,c,d for CY7C1380V25 and BWa,b for CY7C1382V25) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals CY7C1380CV25 CY7C1382CV25 (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BWx signals. The CY7C1380CV25/CY7C1382CV25 provides byte write capability that is described in the write cycle description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1380CV25 and BWa,b for CY7C1382CV25) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will threestate the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ[x:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1380CV25/CY7C1382CV25 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel® Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Document #: 38-05240 Rev. *A Page 8 of 33 PRELIMINARY Interleaved Burst Sequence First Address A[1:0]] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 Sleep Mode CY7C1380CV25 CY7C1382CV25 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC Description Sleep mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V 2tCYC Min. Max. 60 2tCYC Unit mA ns ns Document #: 38-05240 Rev. *A Page 9 of 33 PRELIMINARY Cycle Descriptions[1, 2, 3, 4] Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ “sleep” Add. Used None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current None ZZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X X CE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X X CE1 1 0 0 0 0 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 X CY7C1380CV25 CY7C1382CV25 ADV X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 X OE X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write X Notes: 1. X = “Don't Care,” 1 = HIGH, 0 = LOW. 2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. CE1, CE2 and CE3 are available only in the TQFP package. The BGA package has a single chip select, CE1. Document #: 38-05240 Rev. *A Page 10 of 33 PRELIMINARY Write Cycle Descriptions[1, 5, 6] Function (1380CV25) Read Read Write Byte 0 – DQa Write Byte 1 – DQb Write Bytes 1, 0 Write Byte 2 – DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 – DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X CY7C1380CV25 CY7C1382CV25 BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Function (1382CV25) Read Read Write Byte 0 – DQ[7:0] and DP0 Write Byte 1 – DQ[15:8] and DP1 Write All Bytes Write All Bytes GW 1 1 1 1 1 0 BWE 1 0 0 0 0 X BWb X 1 1 0 0 X BWa X 1 0 1 0 X Notes: 5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a “don't care” for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05240 Rev. *A Page 11 of 33 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380CV25/CY7C1382CV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP)—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The e output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitDocument #: 38-05240 Rev. *A CY7C1380CV25 CY7C1382CV25 ry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the Page 12 of 33 PRELIMINARY SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the ShiftIR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. CY7C1380CV25 CY7C1382CV25 When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05240 Rev. *A Page 13 of 33 PRELIMINARY TAP Controller State Diagram CY7C1380CV25 CY7C1382CV25 1 TEST-LOGIC RESET 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-DR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 1 Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05240 Rev. *A Page 14 of 33 PRELIMINARY TAP Controller Block Diagram CY7C1380CV25 CY7C1382CV25 0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO 2 Instruction Register 1 0 31 30 29 . . 2 1 0 Identification Register x . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[7, 8] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VI < VDDQ IOH = −1.0 mA IOH = −100 µA IOL = 1.0 mA IOL = 100 µA 1.7 −0.3 −5 Test Conditions Min. 1.7 2.1 0.4 0.2 VDD + 0.3 0.7 5 Max. Unit V V V V V V µA Notes: 7. All Voltage referenced to Ground. 8. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2, Undershoot: VIL(AC) > −0.5V for t < tTCYC/2. Document #: 38-05240 Rev. *A Page 15 of 33 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameters tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW Description CY7C1380CV25 CY7C1382CV25 Min. 100 Max 10 Unit ns MHz ns ns ns ns ns ns ns ns 40 40 10 10 10 10 10 10 20 0 ns ns Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns. Document #: 38-05240 Rev. *A Page 16 of 33 PRELIMINARY TAP Timing and Test Conditions CY7C1380CV25 CY7C1382CV25 1.25V 50Ω TDO Z0 = 50Ω CL = 20 pF 0V ALL INPUT PULSES 2.5V 1.25V GND (a) tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV tTDOX Document #: 38-05240 Rev. *A Page 17 of 33 PRELIMINARY Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device ID (27:24) Device Type (23:18) Device Width and Density (17:12) Cypress JEDEC ID (11:0) 512K x 36 0100 1011 000000 100101 000001101001 1M x 18 0100 1011 000000 010101 000001101001 CY7C1380CV25 CY7C1382CV25 Description Reserved for version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 51 Bit Size (x36) 3 1 32 70 Identification Codes Instruction EXTEST 000 Code Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD 001 010 011 100 RESERVED RESERVED BYPASS 101 110 111 Document #: 38-05240 Rev. *A Page 18 of 33 PRELIMINARY Boundary Scan Order (512K x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD CY7C1380CV25 CY7C1382CV25 Boundary Scan Order (1M x 18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Document #: 38-05240 Rev. *A Page 19 of 33 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –55°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND ....... –0.3V to +3.6V DC Voltage Applied to Outputs in High Z State[11] ................................ –0.5V to VDDQ + 0.5V DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V Current into Outputs (LOW) .........................................20 mA CY7C1380CV25 CY7C1382CV25 Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Com’l Ind’l Ambient Temp.[12] 0°C to 70°C –40°C to +85°C VDD/VDDQ 2.5V ± 5% Electrical Characteristics Over the Operating Range Parameter VDD/VDDQ VOH VOL VIH VIL IX IZZ IOZ IDD Description Power Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[11] Input Load Current except ZZ and MODE Input Current of MODE Input Current of ZZ Output Leakage Current VDD Operating Supply Input = VSS GND < VI < VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE PowerMax. VDD, Device Deselected, Down Current—TTL Inputs VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB2 Automatic CE PowerDown Current—CMOS Inputs Automatic CE PowerDown Current—CMOS Inputs Max. VDD, Device Deselected, VIN < 0.3V or VIN > VDDQ – 0.3V, f=0 All speed grades GND < VI < VDDQ VDD = Min., IOH = −1.0 mA VDD = Min., IOL = 1.0 mA 1.7 –0.3 –5 −30 −30 –5 Test Conditions Min. 2.375 2.0 0.4 VDD + 0.3 0.7 5 30 30 5 350 325 300 275 120 110 100 90 70 µA µA µA µA mA mA mA mA mA mA mA mA mA Max. 2.625 Unit V V ISB3 Max. VDD, Device Deselected, or 4.0-ns cycle, 250 MHz VIN < 0.3V or VIN > VDDQ – 0.3V 4.4-ns cycle, 225 MHz f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz All Speeds 105 100 95 85 80 mA mA mA mA mA ISB4 Automatic CE PowerMax. VDD, Device Deselected, Down Current—TTL Inputs VIN > VIH or VIN < VIL, f = 0 Shaded areas contain advance information. Notes: 11. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. 12. TA is the temperature. Document #: 38-05240 Rev. *A Page 20 of 33 PRELIMINARY Capacitance[13] CY7C1380CV25 CY7C1382CV25 Max. Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz 100-TQFP TBD TBD TBD 119-BGA TBD TBD TBD 165-FBGA TBD TBD TBD Unit pF pF pF AC Test Loads and Waveforms[14] OUTPUT Z0 = 50Ω 30 pF Vt = 1.25 Vt - Termination Voltage (a) Rt - Termination Resistance INCLUDING JIG AND SCOPE Rt = 50Ω VDDQ OUTPUT 5 pF R = 1667Ω ALL INPUT PULSES 2.5V 10% GND R = 1538Ω ≤ 1 ns 90% [10] 90% 10% ≤ 1 ns (b) (c) Thermal Resistance[13] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch2, 2-layer printed circuit board Symbol ΘJA ΘJC TQFP 31 6 119 BGA 45 7 165 FBGA 46 3 Unit °C/W °C/W Notes: 13. Tested initially and after any design or process changes that may affect these parameters. 14. Input waveform should have a slew rate of < 1 ns. Document #: 38-05240 Rev. *A Page 21 of 33 PRELIMINARY Switching Characteristics Over the Operating Range[15, 16, 17] -250 Parameter tCYC tCH tCL tAS tAH tCO tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Clock HIGH Clock LOW Address Set-up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-up Before CLK Rise ADSP, ADSC Hold After CLK Rise BWE, GW, BWx Set-up Before CLK Rise BWE, GW, BWx Hold After CLK Rise ADV Set-up Before CLK Rise ADV Hold After CLK Rise Data Input Set-up Before CLK Rise Data Input Hold After CLK Rise Chip Enable Set-up Chip Enable Hold After CLK Rise Clock to Clock to High-Z[16] Low-Z[16] High-Z[16, 17] 0 2.6 Valid[16] 1.0 2.6 0 2.8 1.0 1.2 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 0.3 2.6 1.0 2.8 0 Description Clock Cycle Time Min. 4.0 1.7 1.7 1.2 0.3 2.6 1.0 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 2.8 1.3 Max. 4.4 2.0 2.0 1.4 0.4 2.8 1.3 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 -225 Min. Max. 5 2.0 2.0 1.4 0.4 CY7C1380CV25 CY7C1382CV25 -200 Min. Max. 6 2.2 2.2 1.5 0.5 3.0 1.3 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.0 1.3 3.0 0 3.0 -167 Min. Max. Unit ns ns ns ns ns 3.4 ns ns ns ns ns ns ns ns ns ns ns ns 3.4 3.4 3.4 ns ns ns ns ns OE HIGH to Output OE LOW to Output OE LOW to Output Low-Z[16, 17] Shaded areas contain preliminary information. Notes: 15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads. 16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steadystate voltage. 17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ. Document #: 38-05240 Rev. *A Page 22 of 33 PRELIMINARY 1 CY7C1380CV25 CY7C1382CV25 Switching Waveforms Write Cycle Timing[4, 18, 19, 20] Single Write tCH tCYC Burst Write Pipelined Write Unselected CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS tADH ADSC initiated write ADSC tADVS tADVH ADV tAS ADV Must Be Inactive for ADSP Write WD1 tAH WD2 WD3 ADD GW tWS tWH tWS CE1 masks ADSP tWH WE tCES tCEH CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDS tDH High-Z Data High-Z In 1a 1a 2a = UNDEFINED 2b 2c 2d 3a = DON’T CARE Notes: 18. WE is the combination of BWE and BWx to define a write cycle (see Write Cycle Descriptions table). 19. WDx stands for Write Data to Address X. 20. Device originally deselected. Document #: 38-05240 Rev. *A Page 23 of 33 PRELIMINARY Switching Waveforms (continued) Read Cycle Timing[4, 18, 20, 21] CY7C1380CV25 CY7C1382CV25 Single Read tCYC Burst Read tCH Pipelined Read Unselected CLK tADS tADH tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH tADVH RD1 tAH RD2 RD3 Suspend Burst ADV tAS ADD GW tWS tWH tWS WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES tCEH tEOV tOEHZ tDOH tCO OE Data Out 1a 1a tCLZ 2a 2b 2c 2c 2d 3a tCHZ = DON’T CARE Note: 21. RDx stands for Read Data from Address X. = UNDEFINED Document #: 38-05240 Rev. *A Page 24 of 33 PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[4, 18, 19, 20, 21] CY7C1380CV25 CY7C1382CV25 Single Read tCYC Single Write tCH Single Write Burst Read Single cycle deselect Pipelined Read CLK tADS tADH tCL ADSP ADSC tADVS ADV tAS tADVH RD1 tAH WD2 WD3 RD4 RD5 ADD GW tWS tWH tWS WE tCES tCEH tWH CE1 Unselected CE1 CE2 tCES tCEH CE3 tCES tCEH tEOV tEOHZ tEOLZ tCO 1a 1a Out 2a In 3a In = UNDEFINED OE tDS 4a Out tDH 4b Out 4c Out tDOH 4d Out tCHZ Data In/Out = DON’T CARE I/O Disabled within one clock cycle after deselect Document #: 38-05240 Rev. *A Page 25 of 33 PRELIMINARY Switching Waveforms (continued) Pipelined Read/Write Timing[4, 18, 19, 20, 21] Selected ADSC read ADSP read Unselected ADSC write CY7C1380CV25 CY7C1382CV25 ADSP write CLK ADSP ADSC ADV ADD RD1 RD2 RD3 RD4 WD5 WD6 WD7 WD8 GW WE CE1 CE2 CE3 OE Data In/Out 1a 1a Out 2a Out 3a Out 4a Out 5a In 6a In 7a In = DON’T CARE = UNDEFINED Document #: 38-05240 Rev. *A Page 26 of 33 PRELIMINARY Switching Waveforms (continued) OE Switching Waveforms CY7C1380CV25 CY7C1382CV25 OE tEOHZ tEOV I/Os Three-State tEOLZ Document #: 38-05240 Rev. *A Page 27 of 33 PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing [4, 22, 23] CY7C1380CV25 CY7C1382CV25 CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ tZZS IDD IDD(active) IDDZZ tZZREC I/Os Three-state Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 23. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05240 Rev. *A Page 28 of 33 PRELIMINARY Ordering Information Speed (MHz) 250 Ordering Code CY7C1382CV25-250AC CY7C1380CV25-250AC CY7C1382CV25-250BGC CY7C1380CV25-250BGC CY7C1382CV25-250BZC CY7C1380CV25-250BZC 225 CY7C1382CV25-225AC CY7C1380CV25-225AC CY7C1382CV25-225BGC CY7C1380CV25-225BGC CY7C1382CV25-225BZC CY7C1380CV25-225BZC 200 CY7C1382CV25-200AC CY7C1380CV25-200AC CY7C1382CV25-200BGC CY7C1380CV25-200BGC CY7C1382CV25-200BZC CY7C1380CV25-200BZC 167 CY7C1382CV25-167AC CY7C1380CV25-167AC CY7C1382CV25-167BGC CY7C1380CV25-167BGC CY7C1382CV25-167BZC CY7C1380CV25-167BZC 225 CY7C1382CV25-225AI CY7C1380CV25-225AI CY7C1382CV25-225BGI CY7C1380CV25-225BGI CY7C1382CV25-225BZI CY7C1380CV25-225BZC 200 CY7C1382CV25-200AI CY7C1380CV25-200AI CY7C1382CV25-200BGI CY7C1380CV25-200BGI CY7C1382CV25-200BZI CY7C1380CV25-200BZI 167 CY7C1382CV25-167AI CY7C1380CV25-167AI CY7C1382CV25-167BGI CY7C1380CV25-167BGI CY7C1382CV25-167BZI CY7C1380CV25-167BZI Package Name A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A Package Type 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 PBGA 165 FBGA CY7C1380CV25 CY7C1382CV25 Operating Range Commercial Industrial Shaded areas contain advance information and parts that may not be offered. Document #: 38-05240 Rev. *A Page 29 of 33 PRELIMINARY Package Diagrams CY7C1380CV25 CY7C1382CV25 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05240 Rev. *A Page 30 of 33 PRELIMINARY Package Diagrams (continued) 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A CY7C1380CV25 CY7C1382CV25 51-85122-*C Document #: 38-05240 Rev. *A Page 31 of 33 PRELIMINARY Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1380CV25 CY7C1382CV25 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-05240 Rev. *A Page 32 of 33 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY7C1380CV25/CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Document Number: 38-05240 Rev. ** *A ECN No. 116280 121543 Issue Date 08/29/02 11/21/02 Orig. of Change SKX DSG New Data Sheet CY7C1380CV25 CY7C1382CV25 Description of Change Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev. *C Document #: 38-05240 Rev. *A Page 33 of 33