CY7C1386D
CY7C1387D
18-Mbit (512K × 36/1M × 18)
Pipelined DCD Sync SRAM
Features
Functional Description
■
Supports bus operation up to 200 MHz
■
Available speed grades are 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
Optimal for performance (double-cycle deselect)
■
Depth expansion without wait state
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O power supply (VDDQ)
The
CY7C1386D/CY7C1387D
SRAM
integrates
512K × 36/1M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
■
Fast clock-to-output times
❐ 3 ns (for 200 MHz device)
■
Provides high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
Interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
CY7C1386D available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1387D available in JEDEC-standard Pb-free
100-pin TQFP and non Pb-free 165-ball BGA package
■
IEEE 1149.1 JTAG-compatible boundary scan
■
ZZ sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Configurations on page 5 and Truth Table on
page 11 for further details). Write cycles can be one to four bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing
system performance.
The CY7C1386D/CY7C1387D operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or +2.5 V
supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
200 MHz
167 MHz
Unit
Maximum access time
3.0
3.4
ns
Maximum operating current
300
275
mA
Maximum CMOS standby current
70
70
mA
Errata: For information on silicon errata, see “Errata” on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05545 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 27, 2016
Not Recommended for New Design
18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
CY7C1386D
CY7C1387D
Logic Block Diagram – CY7C1386D
A0,A1,A
ADDRESS
REGISTER
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
BW D
DQ D, DQP D
BYTE
WRITE REGISTER
DQ D, DQP D
BYTE
WRITE DRIVER
BW C
DQ c ,DQP C
BYTE
WRITE REGISTER
DQ c ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
DQP D
E
DQ A, DQP A
BYTE
WRITE DRIVER
DQ A, DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
CONTROL
Document Number: 38-05545 Rev. *P
Page 2 of 38
Not Recommended for New Design
ADSP
CY7C1386D
CY7C1387D
Logic Block Diagram – CY7C1387D
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A [1:0]
Q1
BURST
COUNTER AND
CLR
Q0
ADSC
BW B
BW A
BWE
CE 1
CE 2
CE 3
DQ B , DQP B
BYTE
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
DQ A , DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQ s,
DQP A
DQP B
E
INPUT
REGISTERS
OE
SLEEP
CONTROL
Document Number: 38-05545 Rev. *P
Page 3 of 38
Not Recommended for New Design
ADSP
CY7C1386D
CY7C1387D
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG [13]) ........... 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing Diagram ...................................................... 16
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Document Number: 38-05545 Rev. *P
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Errata ............................................................................... 33
Part Numbers Affected .............................................. 33
Product Status ........................................................... 33
Ram9 Sync ZZ Pin
& JTAG Issues Errata Summary ...................................... 33
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC®Solutions ....................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Page 4 of 38
Not Recommended for New Design
Contents
CY7C1386D
CY7C1387D
Pin Configurations
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1387D
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see “Errata” on page 33.
Document Number: 38-05545 Rev. *P
Page 5 of 38
Not Recommended for New Design
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
A
A
A
A
A
A
A
A
A
CY7C1386D
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable) [1]
CY7C1386D
CY7C1387D
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enable) [2, 3]
CY7C1387D (1M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
CE2
BWB
NC
CE3
CLK
ADV
ADSP
A
BWA
ADSC
OE
A
NC
BWE
GW
VDDQ
VSS
VSS
VSS
VSS
VDD
VDDQ
DQPA
DQA
R
A
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VDDQ
NC/1G
NC
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
NC
DQB
DQB
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
‘VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
DQA
ZZ
NC
DQB
NC
NC
A
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
Note
2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 33.
3. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 33.
Document Number: 38-05545 Rev. *P
Page 6 of 38
Not Recommended for New Design
NC/576M
NC/144M
CY7C1386D
CY7C1387D
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. Not connected for BGA. Where referenced, CE3 is assumed
active throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ [4]
InputZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an
internal pull down.
DQs,
DQPX
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
VSSQ
I/O Ground
Ground for the I/O circuitry.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
Ground for the core of the device.
Note
4. Errata: The ZZ pin needs to be externally connected to ground. For more information, see “Errata” on page 33.
Document Number: 38-05545 Rev. *P
Page 7 of 38
Not Recommended for New Design
BWA, BWB,
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD Synchronous on the rising edge of CLK.
CY7C1386D
CY7C1387D
Name
I/O
Description
MODE
InputStatic
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
TDO [5]
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not used, this pin must be disconnected. This pin is not available on TQFP packages.
output
Synchronous
TDI [5]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
Synchronous
TMS [5]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
Synchronous
TCK [5]
JTAGClock
NC
–
No Connects. Not internally connected to the die.
NC/(36M,
72M,
144M,
288M,
576M, 1G)
–
These pins are not connected. They are used for expansion up to 36M, 72M, 144M, 288M, 576M, and
1G densities.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
Note
5. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 33.
Document Number: 38-05545 Rev. *P
Page 8 of 38
Not Recommended for New Design
Pin Definitions (continued)
CY7C1386D
CY7C1387D
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1386D/CY7C1387D supports secondary cache in
systems using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that use a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tristate control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals (GW,
BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH.
The address presented to the address inputs is stored into the
address advancement logic and the address register while being
presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The CY7C1386D/CY7C1387D is a double cycle deselect part.
After the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output tristates immediately
after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
Document Number: 38-05545 Rev. *P
BWE, and BWX) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, the write operation is controlled by BWE and BWX signals.
The CY7C1386D/CY7C1387D provides byte write capability that
is described in the write cycle description table. Asserting the
byte write enable input (BWE) with the selected byte write input,
selectively writes to the desired bytes. Bytes not selected during
a byte write operation remains unaltered. A synchronous self
timed write mechanism has been provided to simplify the write
operations.
The CY7C1386D/CY7C1387D is a common I/O device, the
output enable (OE) must be deasserted HIGH before presenting
data to the DQ inputs. This tristates the output drivers. As a
safety precaution, DQ are automatically tristated whenever a
write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BWX) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation remains
unaltered. A synchronous self timed write mechanism has been
provided to simplify the write operations.
The CY7C1386D/CY7C1387D is a common I/O device, the
output enable (OE) must be deasserted HIGH before presenting
data to the DQX inputs. This tristates the output drivers. As a
safety precaution, DQX are automatically tristated whenever a
write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1386D/CY7C1387D provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications. The
linear burst sequence is designed to support processors that
follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Page 9 of 38
Not Recommended for New Design
Functional Overview
CY7C1386D
CY7C1387D
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05545 Rev. *P
Page 10 of 38
Not Recommended for New Design
First
Address
A1:A0
CY7C1386D
CY7C1387D
Truth Table
Operation
Add. Used CE1 CE2 CE3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
6. X = Do not care, H = Logic HIGH, L = Logic LOW.
7. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05545 Rev. *P
Page 11 of 38
Not Recommended for New Design
The Truth Table for CY7C1386D and CY7C1387D follow. [6, 7, 8, 9, 10]
CY7C1386D
CY7C1387D
Truth Table for Read/Write
Function (CY7C1386D)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1387D follows. [11, 12]
Function (CY7C1387D)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes
11. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid appropriate write is done based on which byte write is active.
Document Number: 38-05545 Rev. *P
Page 12 of 38
Not Recommended for New Design
The Truth Table for Read/Write for CY7C1386D follows. [11, 12]
CY7C1386D
CY7C1387D
IEEE 1149.1 Serial Boundary Scan (JTAG [13])
TAP Registers
The CY7C1387D incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
can be left unconnected. Upon power-up, the device comes up
in a reset state which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 19.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Note
13. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 33.
Document Number: 38-05545 Rev. *P
Page 13 of 38
Not Recommended for New Design
The CY7C1387D contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
CY7C1386D
CY7C1387D
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
EXTEST
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data can be shifted in.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. As there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
Document Number: 38-05545 Rev. *P
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tristate
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package) or bit #89 (for 165-ball FBGA
package). When this scan cell, called the “extest output bus
tristate,” is latched into the preload register during the
Update-DR state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered-up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 38
Not Recommended for New Design
TAP Instruction Set
CY7C1386D
CY7C1387D
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
Not Recommended for New Design
0
0
1
0
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05545 Rev. *P
Page 15 of 38
CY7C1386D
CY7C1387D
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Not Recommended for New Design
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing Diagram
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05545 Rev. *P
UNDEFINED
Page 16 of 38
CY7C1386D
CY7C1387D
TAP AC Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK Clock LOW to TDO invalid
0
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Setup Times
Hold Times
Notes
14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
15. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05545 Rev. *P
Page 17 of 38
Not Recommended for New Design
Output Times
CY7C1386D
CY7C1387D
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels .............................................. .VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
Z O= 50 Ω
TDO
20pF
Z O= 50 Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [16]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
Test Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA, VDDQ = 3.3 V
–
0.4
V
IOL = 8.0 mA, VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Note
16. All voltages referenced to VSS (GND).
Document Number: 38-05545 Rev. *P
Page 18 of 38
Not Recommended for New Design
50Ω
TDO
CY7C1386D
CY7C1387D
Identification Register Definitions
CY7C1387D (1M × 18)
Revision Number (31:29)
000
[17]
Description
Describes the version number
01011
Reserved for internal use.
Device Width (23:18) 165-ball FBGA
000110
Defines the memory type and architecture.
Cypress Device ID (17:12)
010101
Defines the width and density.
Device Depth (28:24)
Cypress JEDEC ID Code (11:1)
00000110100
ID Register Presence Indicator (0)
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 18)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Codes
Code
Description
EXTEST
Instruction
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
17. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05545 Rev. *P
Page 19 of 38
Not Recommended for New Design
Instruction Field
CY7C1386D
CY7C1387D
Boundary Scan Order
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Notes
18. Balls that are NC (No Connect) are preset LOW.
19. Bit#89 is preset HIGH.
Document Number: 38-05545 Rev. *P
Page 20 of 38
Not Recommended for New Design
165-ball BGA [18, 19]
CY7C1386D
CY7C1387D
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Range
Ambient
Temperature
VDD
VDDQ
Storage temperature ................................ –65 °C to +150 °C
Commercial
0 °C to +70 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Industrial
3.3 V– 5% /
+10%
2.5 V – 5% to
VDD
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
–40 °C to +85 °C
Neutron Soft Error Immunity
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Parameter
DC input voltage ................................. –0.5 V to VDD + 0.5 V
LSBU
Logical
single-bit
upsets
25 °C
LMBU
Logical
multi-bit
upsets
Single event
latch-up
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Description
Latch-up current .................................................... > 200 mA
SEL
Test
Conditions Typ
Max*
Unit
361
394
FIT/
Mb
25 °C
0
0.01
FIT/
Mb
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [20, 21]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
[20]
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
µA
Input current of MODE
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
GND VI VDDQ, Output Disabled
–5
5
µA
Input LOW voltage
[20]
Input current of ZZ
IOZ
Test Conditions
Output leakage current
Input = VSS
Notes
20. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
21. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05545 Rev. *P
Page 21 of 38
Not Recommended for New Design
Maximum Ratings
CY7C1386D
CY7C1387D
Electrical Characteristics (continued)
Parameter [20, 21]
IDD
Description
VDD operating supply current
Test Conditions
Min
Max
Unit
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
5 ns cycle, 200 MHz
–
300
mA
6 ns cycle, 167 MHz
–
275
mA
Automatic CE power-down
current – TTL inputs
VDD = Max,
device deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
5 ns cycle, 200 MHz
–
150
mA
6 ns cycle, 167 MHz
–
140
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max,
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f=0
All speeds
–
70
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max,
5 ns cycle, 200 MHz
device deselected, or
6 ns cycle, 167 MHz
VIN 0.3 V or
VIN > VDDQ – 0.3 V
f = fMAX = 1/tCYC
–
130
mA
–
125
mA
Automatic CE power-down
current – TTL inputs
VDD = Max,
All speeds
device deselected,
VIN VIH or VIN VIL,
f=0
–
80
mA
ISB1
ISB4
Capacitance
Parameter [22]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA Unit
Max
Max
5
9
pF
5
9
pF
5
9
pF
Thermal Resistance
Parameter [22]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
100-pin TQFP 165-ball FBGA Unit
Package
Package
28.66
20.7
°C/W
4.08
4.0
°C/W
Note
22. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05545 Rev. *P
Page 22 of 38
Not Recommended for New Design
Over the Operating Range
CY7C1386D
CY7C1387D
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
10%
90%
10%
90%
GND
5 pF
R = 351
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
(c)
(b)
Z0 = 50
10%
R = 1538
VT = 1.25 V
Document Number: 38-05545 Rev. *P
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
(b)
1 ns
1 ns
(c)
Page 23 of 38
Not Recommended for New Design
VT = 1.5 V
CY7C1386D
CY7C1387D
Switching Characteristics
Over the Operating Range
Parameter [23, 24]
tPOWER
Description
VDD(typical) to the first access [25]
-200
-167
Unit
Min
Max
Min
Max
1
–
1
–
ms
tCYC
Clock cycle time
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.3
–
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
–
3.0
–
3.4
ns
[26, 27, 28]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [26, 27, 28]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[26, 27, 28]
OE HIGH to output high Z
[26, 27, 28]
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.4
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.4
–
0.5
–
ns
Hold Times
Notes
23. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
24. Test conditions shown in (a) of Figure 3 on page 23 unless otherwise noted.
25. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
26. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 3 on page 23. Transition is measured ±200 mV from steady-state voltage.
27. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
28. This parameter is sampled and not 100% tested.
Document Number: 38-05545 Rev. *P
Page 24 of 38
Not Recommended for New Design
Clock
CY7C1386D
CY7C1387D
Switching Waveforms
Figure 4. Read Cycle Timing [29]
tCYC
CLK
tCH
t ADS
tCL
tADH
t ADS
tADH
ADSC
t AS
ADDRESS
tAH
A1
A2
t WES
GW, BWE,BW
A3
Burst continued with
new base address
tWEH
X
t CES
Deselect
cycle
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
29. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 38-05545 Rev. *P
Page 25 of 38
Not Recommended for New Design
ADSP
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
Figure 5. Write Cycle Timing [30]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
t AS
tAH
A1
ADDRESS
Not Recommended for New Design
ADSC
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
OEHZ
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 3)
D(A3)
D(A3 + 1)
Data Out (Q)
BURST READ
BURST WRITE
Single WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note
30. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 38-05545 Rev. *P
Page 26 of 38
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
Figure 6. Read/Write Cycle Timing [31, 32, 33]
t CYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE, BW
X
t CES
tCEH
CE
ADV
OE
t DS
tCO
Data In (D)
t OELZ
High-Z
tOEHZ
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
D(A3)
Q(A4)
Q(A2)
Back-to-Back READs
D(A5)
DON’T CARE
Q(A4+3)
BURST READ
Single WRITE
D(A6)
Back-to-Back
WRITEs
UNDEFINED
Notes
31. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW.
32. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
33. GW is HIGH.
Document Number: 38-05545 Rev. *P
Page 27 of 38
Not Recommended for New Design
ADSP
CY7C1386D
CY7C1387D
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [34, 35]
CLK
t
ZZ
ZZREC
ZZI
SUPPLY
I
t
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
RZZI
Not Recommended for New Design
I
t
t
ZZ
DESELECT or READ Only
High-Z
DON’T CARE
Notes
34. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.
35. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05545 Rev. *P
Page 28 of 38
CY7C1386D
CY7C1387D
Ordering Information
The table below contains only the parts that are currently available. If you do not see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Package
Diagram
Ordering Code
CY7C1386D-167AXC
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
CY7C1386D-200AXC
Not Recommended for New Design
CY7C1387D-167AXC
Ordering Code Definitions
CY 7
C 13XX D - XXX X
X
X
Temperature Range:
C = Commercial
X = Pb-free; X Absent = Leaded
Package Type:
A = 100-pin TQFP
Speed Grade: XXX = 167 MHz / 200 MHz
Process Technology: D 90 nm Technology
Part Identifier: 13XX = 1386 or 1387
1386 = DCD, 512K × 36 (18Mb)
1387 = DCD, 1M × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05545 Rev. *P
Page 29 of 38
CY7C1386D
CY7C1387D
Package Diagrams
Not Recommended for New Design
Figure 10. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05545 Rev. *P
Page 30 of 38
CY7C1386D
CY7C1387D
Package Diagrams (continued)
Not Recommended for New Design
Figure 8. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05545 Rev. *P
Page 31 of 38
CY7C1386D
CY7C1387D
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CE
Chip Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
k
kilohm
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JTAG
Joint Test Action Group
µs
microsecond
mA
milliampere
mV
millivolt
mm
millimeter
ms
millisecond
ns
nanosecond
Symbol
Unit of Measure
LMBU
Logical Multiple-Bit Upsets
LSB
Least Significant Bit
LSBU
Logical Single-Bit Upsets
MSB
Most Significant Bit
OE
Output Enable
ohm
SEL
Single Event Latch-Up
%
percent
SRAM
Static Random Access Memory
pF
picofarad
TAP
Test Access Port
ps
picosecond
TCK
Test Clock
V
volt
TDI
Test Data-In
W
watt
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
Document Number: 38-05545 Rev. *P
Not Recommended for New Design
Acronyms
Page 32 of 38
CY7C1386D
CY7C1387D
Errata
This section describes the Ram9 Sync ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
18Mb-Ram9 Synchronous SRAMs: CY7C138*D
Package Type
Operating Range
100-pin TQFP
Commercial
165-ball FBGA
Industrial
All of the devices in the Ram9 18Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin & JTAG Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb Sync family devices.
Item
Issues
Description
Device
Fix Status
1.
ZZ Pin
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2.
JTAG
Functionality
During JTAG test mode, the Boundary scan
circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
18M-Ram9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Document Number: 38-05545 Rev. *P
Page 33 of 38
Not Recommended for New Design
Product Status
CY7C1386D
CY7C1387D
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue.
2. JTAG Functionality
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■
TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■
SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■
WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
■
FIX STATUS
This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability.
Document Number: 38-05545 Rev. *P
Page 34 of 38
Not Recommended for New Design
1. ZZ Pin Issue
CY7C1386D
CY7C1387D
Document History Page
Document Title: CY7C1386D/CY7C1387D, 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05545
Revision
ECN
Orig. of
Change
Submission
Date
**
254550
RKF
See ECN
New data sheet.
*A
288531
SYT
See ECN
Updated Features (Removed 225 MHz speed bin information).
Updated Selection Guide (Removed 225 MHz speed bin information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Edited description
for non-compliance with 1149.1).
Updated Electrical Characteristics (Removed 225 MHz speed bin information).
Updated Switching Characteristics (Removed 225 MHz speed bin information).
Updated Ordering Information (Updated part numbers (Added Pb-free
information for 100-pin TQFP, 119-ball BGA and 165-ball FBGA Packages) and
added comment of ‘Pb-free BG packages availability’ below the Ordering
Information).
*B
326078
PCI
See ECN
Updated Pin Configurations (Modified Address Expansion pins/balls in the
pinouts for all packages as per JEDEC standards)
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Updated TAP
Instruction Set (Updated OVERVIEW, updated EXTEST, added EXTEST
Output Bus Tristate)).
Updated Identification Register Definitions (Splitted Device Width (23:18) into
two rows, one row for 119-ball BGA and another row for 165-ball FBGA and
updated the values).
Updated Electrical Characteristics (Updated test conditions for VOH and VOL
parameters).
Updated Thermal Resistance (Changed values of JA and JC parameters for
100-pin TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W
respectively, changed values of JA and JC parameters for 119-ball BGA
Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively, changed
values of JA and JC parameters for 165-ball FBGA Package from 46 and
3 C/W to 20.7 and 4.0 C/W respectively).
Updated Ordering Information (updated part numbers and removed comment
of “Pb-free BG packages availability” below the Ordering Information).
*C
418125
NXR
See ECN
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Changed the description of IX parameter
from Input Load Current to Input Leakage Current, changed minimum and
maximum values of IX parameter for Input Current of MODE from –5 A and
30 A to –30 A and 5 A, changed minimum and maximum values of IX
parameter for Input Current of ZZ from –30 A and 5 A to –5 A and 30 A,
updated Note 21 (changed VIH < VDD to VIH < VDD)).
Updated Ordering Information (updated part numbers and replaced Package
Name column with Package Diagram in the Ordering Information table).
*D
475009
VKN
See ECN
Updated TAP AC Switching Characteristics (Changed minimum values of tTH
and tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (updated part numbers).
*E
793579
VKN
See ECN
Added Part numbers CY7C1386F and CY7C1387F
Updated Features (Included all information related to CY7C1386F and
CY7C1387F).
Updated Functional Description (Included all information related to
CY7C1386F and CY7C1387F).
Document Number: 38-05545 Rev. *P
Page 35 of 38
Not Recommended for New Design
Description of Change
CY7C1386D
CY7C1387D
Document History Page (continued)
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*E (Cont.)
793579
VKN
See ECN
Updated Logic Block Diagram and added a note regarding Chip Enable
“CY7C1386F and CY7C1387F have only 1 Chip Enable (CE1).”.
Updated Pin Configurations (Included all information related to CY7C1386F
and CY7C1387F).
Updated Functional Overview (Included all information related to CY7C1386F
and CY7C1387F).
Updated Truth Table (Included all information related to CY7C1386F and
CY7C1387F).
Updated Truth Table for Read/Write (Included all information related to
CY7C1386F and CY7C1387F).
Updated Truth Table for Read/Write (Included all information related to
CY7C1386F and CY7C1387F).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Included all
information related to CY7C1386F and CY7C1387F).
Updated Identification Register Definitions (Included all information related to
CY7C1386F and CY7C1387F).
Updated Ordering Information (updated part numbers).
*F
2756940
VKN
08/27/2009
Added Neutron Soft Error Immunity.
Modified Ordering Information (by including parts that are available) and
modified the disclaimer for the Ordering Information.
*G
3006369
NJY
08/12/10
*H
3309506
OSN
07/12/2011
Updated Package Diagrams.
Added Units of Measure.
Updated to new template.
*I
3541411
PRIT
03/03/2012
Updated Features (Removed all information related to CY7C1386F and
CY7C1387F).
Updated Functional Description (Removed all information related to
CY7C1386F and CY7C1387F, removed the notes “For best practices or
recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines on www.cypress.com.” and “CE3 and CE2
are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is
offered only in Single Chip Enable.”).
Updated Selection Guide (Removed 250 MHz speed bin information).
Updated Logic Block Diagram – CY7C1386D (Removed all information related
to CY7C1386F and CY7C1387F).
Updated Logic Block Diagram – CY7C1387D (Removed all information related
to CY7C1386F and CY7C1387F).
Updated Pin Configurations (Removed all information related to CY7C1386F
and CY7C1387F).
Updated Pin Definitions (Removed the note “CE3 and CE2 are for 100-pin
TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single
Chip Enable.” and its references in the same section).
Updated Functional Overview (Removed all information related to CY7C1386F
and CY7C1387F, removed the note “CE3 and CE2 are for 100-pin TQFP and
165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip
Enable.” and its references in the same section).
Updated Truth Table (Removed all information related to CY7C1386F and
CY7C1387F).
Updated Truth Table for Read/Write (Removed all information related to
CY7C1386F and CY7C1387F).
Updated Truth Table for Read/Write (Removed all information related to
CY7C1386F and CY7C1387F).
Document Number: 38-05545 Rev. *P
Added Ordering Code Definitions.
Added Acronyms.
Updated to new template.
Page 36 of 38
Not Recommended for New Design
Document Title: CY7C1386D/CY7C1387D, 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05545
CY7C1386D
CY7C1387D
Document History Page (continued)
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*I (Cont.)
3541411
PRIT
03/03/2012
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]) (Removed all
information related to CY7C1386F and CY7C1387F).
Updated Identification Register Definitions (Removed all information related to
CY7C1386F and CY7C1387F).
Updated Scan Register Sizes (Removed Bit Size (× 36) information).
Updated Boundary Scan Order (Removed all 119-ball BGA information).
Updated Electrical Characteristics (Removed 250 MHz speed bin information).
Updated Capacitance (Removed all 119-ball BGA information).
Updated Thermal Resistance (Removed all 119-ball BGA information).
Updated Switching Characteristics (Removed 250 MHz speed bin information).
Updated Ordering Information (updated part numbers) and updated Ordering
Code Definitions.
Updated Package Diagrams.
*J
3690005
PRIT
07/24/2012
No technical updates.
Completing Sunset Review.
*K
3990993
PRIT
05/04/2013
Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
Added Errata.
*L
4068739
PRIT
07/20/2013
Added Errata footnotes (Note 1, 2, 3, 4, 5, 13).
Updated Pin Configurations:
Added Note 1 and referred the same note in Figure 1.
Added Note 2, 3 and referred the same note in Figure 2.
Updated Pin Definitions:
Added Note 4 and referred the same note in ZZ pin.
Added Note 5 and referred the same note in TDO, TDI, TMS, TCK pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [13]):
Added Note 13 and referred the same note in JTAG in the heading.
Updated Errata.
Updated to new template.
*M
4150971
PRIT
10/08/2013
Updated Errata.
*N
4572829
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*O
4865506
PRIT
07/30/2015
Updated to new template.
Completing Sunset Review.
*P
5375669
PRIT
07/27/2016
Added watermark “Not Recommended for New Design” across the document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05545 Rev. *P
Page 37 of 38
Not Recommended for New Design
Document Title: CY7C1386D/CY7C1387D, 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Document Number: 38-05545
CY7C1386D
CY7C1387D
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05545 Rev. *P
Revised July 27, 2016
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation.
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