CY7C139-15JC

1CY 7C13 9 fax id: 5204 CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization (CY7C138) • 4K x 9 organization (CY7C139) • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 160 mA (max.) • Fully asynchronous operation • Automatic power-down • TTL compatible • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Available in 68-pin PLCC are included on the CY7C138/9 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138/9 can be utilized as a standalone 8/9-bit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE ), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. The CY7C138 and CY7C139 are available in a 68-pin PLCC. Functional Description The CY7C138 and CY7C139 are high-speed CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Various arbitration schemes Logic Block Diagram R/WL CEL OE L R/WR CER OER (7C139)I/O8L I/O7L I/O0L BUSYL[1, 2] A11L A0L ADDRESS DECODER I/O CONTROL I/O CONTROL I/O8R (7C139) I/O7R I/O0R BUSYR A11R A0R [1, 2] MEMORY ARRAY ADDRESS DECODER CEL OE L R/WL INTERRUPT SEMAPHORE ARBITRATION CE R OER R/WR SEML INTL[2] M/S SEMR INT R[2] C138-1 Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 1996 CY7C138 CY7C139 Pin Configurations \ 68-Pin PLCC Top View 9876 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C138/9 52 51 50 49 48 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R 47 46 45 44 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 C138-2 Notes: 3. I/O8R on the CY7C139. 4. I/O8L o n the CY7C139. Pin Definitions Left Port I/O0L–7L(8L) A0L–11L CEL OEL R/WL SEML Right Port I/O0R–7R(8R) A0R–11R CER OER R/WR SEMR Data Bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INTL is set when right port writes location FFE and is cleared when left port reads location FFE. INTR is set when left port writes location FFF and is cleared when right port reads location FFF. Busy Flag Master or Slave Select Power Ground Description INTL INTR BUSYL M/S VCC GND BUSYR Selection Guide 7C138-15 7C139-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current for ISB1(mA) Commercial Commercial 15 220 60 7C138-25 7C139-25 25 180 40 7C138-35 7C139-35 35 160 30 7C138-55 7C139-55 55 160 30 2 CY7C138 CY7C139 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage[5]......................................... –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL–STD–883, Method 3015) Latch–Up Current ................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C138-15 7C139-15 Parameter VOH VOL VIH VIL IIX IOZ ICC Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current GND < VI < VCC Output Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA, Outputs Disabled CEL and CER > VIH, f = fMAX[6] CEL and CER > VIH, f = fMAX[6] Both Ports CE and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0[6] One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[6] Com’l Ind Com’l Ind Com’l Ind Com’l Ind Com’l Ind 125 15 130 60 –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 220 –10 –10 Min. 2.4 0.4 2.2 0.8 +10 +10 180 190 40 50 110 120 15 30 100 115 mA mA mA mA Max. 7C138-25 7C139-25 Min. 2.4 0.4 Max. Unit V V V V µA µA mA ISB1 ISB2 ISB3 Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) ISB4 Standby Current (One Port CMOS Level) Notes: 5. Pulse width < 20 ns. 6. fMAX = 1 /t RC = A ll inputs cycling at f = 1/t RC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I SB3 . 3 CY7C138 CY7C139 ] Electrical Characteristics Over the Operating Range (continued) 7C138-35 7C139-35 Parameter VOH VOL VIH VIL IIX IOZ ICC Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current GND < V I < VCC Output Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA, Outputs Disabled CEL and CER > VIH, f = fMAX[6] CEL and CER > VIH, f = fMAX[6] Both Ports CE and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0[6] One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[6] Com’l Ind Com’l Ind Com’l Ind Com’l Ind Com’l Ind –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 –10 –10 Min. 2.4 0.4 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 mA mA mA mA Max. 7C138-55 7C139-55 Min. 2.4 0.4 Max. Unit V V V V µA µA mA ISB1 ISB2 ISB3 Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) ISB4 Standby Current (One Port CMOS Level) Capacitance[7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 15 Unit pF pF AC Test Loads and Waveforms 5V R1=893Ω OUTPUT C = 30 pF R2=347Ω OUTPUT C=30pF VTH =1.4V (a) Normal Load (Load 1) C138-3 5V RTH =250 Ω R1=893Ω OUTPUT C = 5 pF R2=347Ω (b) Thévenin EquivalentLoad 1) ( C138-4 (c) Three-State Delay (Load 3) C138-5 ALL INPUT PULSES OUTPUT C = 30 pF 3.0V GND 10% 90% 90% 10% < 3 ns C138-7 < 3 ns Load (Load 2) C138-6 Note: 7. Tested initially and after any design or process changes that may affect these parameters. 4 CY7C138 CY7C139 Switching Characteristics Over the Operating Range[8] 7C138-15 7C139-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE[9,10,11] tHZOE[9,10,11] tLZCE[9,10,11] tHZCE[9,10,11] tPU[11] tPD[11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE[10,11] tLZWE[10,11] tWDD[12] tDDD[12] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[14] Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down 0 15 3 10 0 25 3 10 3 15 0 35 3 15 10 3 15 3 20 0 55 15 15 3 25 15 3 20 3 25 25 25 3 35 20 3 25 35 35 3 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C138-25 7C139-25 Min. Max. 7C138-35 7C139-35 Min. Max. 7C138-55 7C139-55 Min. Max. Unit WRITE CYCLE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid [13] 15 12 12 2 0 12 10 0 10 3 30 25 25 20 20 2 0 20 15 0 15 3 50 30 35 30 30 2 0 25 15 0 20 3 60 35 55 40 40 2 0 30 20 0 25 3 70 40 ns ns ns ns ns ns ns ns ns ns ns ns BUSY TIMING BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Data Valid 5 0 13 15 15 15 15 5 0 20 Note 13 20 20 20 20 5 0 30 Note 13 20 20 20 20 5 0 40 Note 13 45 40 40 35 ns ns ns ns ns ns ns Note 13 ns INTERRUPT TIMING[13] tINS tINR INT Set Time INT Reset Time 15 15 25 25 25 25 30 30 ns ns 5 CY7C138 CY7C139 Switching Characteristics Over the Operating Range[8] (continued) 7C138-15 7C139-15 Parameter SEMAPHORE TIMING tSOP tSWRD tSPS SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window 10 5 5 10 5 5 15 5 5 20 5 5 ns ns ns Description Min. Max. 7C138-25 7C139-25 Min. Max. 7C138-35 7C139-35 Min. Max. 7C138-55 7C139-55 Min. Max. Unit Switching Waveforms Read Cycle No. 1 (Either Port Address Access) [15, 16] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C138-8 Read Cycle No. 2 (Either Port CE/OE Access) SEM or CE OE tLZOE tLZCE DATA OUT tPU ICC ISB tACE [15, 17, 18] tHZCE tHZOE tDOE DATA VALID tPD C138-9 Notes: 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 10. Test conditions used are Load 3. 11. This parameter is guaranteed but not tested. 12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 13. Test conditions used are Load 2. 14. tBDD is a calculated parameter and is the greater of tWDD - tPWE (actual) or tDDD - tSD (actual). 15. R/W is HIGH for read cycle. 16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 17. Address valid prior to or coincident with CE transition LOW. 18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. 6 CY7C138 CY7C139 Switching Waveforms (continued) Read Timing with Port-to-Port Delay (M/S = L) [19, 20] tWC ADDRESS R R/W R MATCH t PWE t SD t HD DATA INR VALID ADDRESS L MATCH tDDD DATAOUTL tWDD VALID C138-10 Write Cycle No. 1: OE Three-States Data I/Os (Either Port) [21, 22, 23] tWC ADDRESS tSCE SEM OR CE tAW R/W tSA DATA IN tSD DATA VALID tHD tPWE tHA OE tHZOE DATA OUT HIGH IMPEDANCE C138-11 t LZOE Notes: 19. BUSY = HIGH for the writing port. 20. CEL = CER = LOW. 21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 23. R/W must be HIGH during all address transitions. 7 CY7C138 CY7C139 Switching Waveforms (continued) Write Cycle No. 2: R/W Three-States Data I/Os (Either Port) tWC ADDRESS tSCE SEM OR CE tSA R/W tAW tPWE tHA [21, 23, 24] tSD DATAIN tHZWE DATA OUT DATA VALID tHD tLZWE HIGH IMPEDANCE C138-12 Semaphore Read After Write Timing, Either Side [25] tAA A0–A 2 VALID ADDRESS tAW SEM tSCE tSD I/O0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE C138-13 tOHA VALID ADDRESS tACE tSOP tHA DATAIN VALID tPWE tHD DATAOUT VALID tDOE Notes: 24. Data I/O pins enter high impedance when OE is held LOW during write. 25. CE = HIGH for the duration of the above timing (both write and read cycle). 8 CY7C138 CY7C139 Switching Waveforms (continued) Timing Diagram of Semaphore Contention [26, 27, 28] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR C138-14 Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/WR [20] tWC MATCH tPWE tSD DATA INR tPS ADDRESS L MATCH tBLA BUSYL tDDD DATAOUTL tWDD VALID tHD tBHA tBDD VALID C138-15 Write Timing with Busy Input (M/S=LOW) R/W tWB tPWE BUSY tWH C138-16 Notes: 26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH 27. Semaphores are reset (available to both ports) at cycle start. 28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. 9 CY7C138 CY7C139 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESS L,R CEL tPS CER tBLC BUSYR C138-17 [29] ADDRESS MATCH tBHC CER Valid First: ADDRESS L,R CER tPS CEL tBLC BUSY L C138-18 ADDRESS MATCH tBHC Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSYR [29] ADDRESS MISMATCH tBHA C138-19 Right Address Valid First: tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSY L C138-20 ADDRESS MISMATCH tBHA Note: 29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. 10 CY7C138 CY7C139 Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESS L CE L R/W L INTR tINS[31] C138-21 WRITE FFF [30] tHA Right Side Clears INTR: ADDRESSR CE R [31] tINR tRC READ FFF R/W R OE R INT R C138-22 Right Side Sets INTL: tWC ADDRESSR CER WRITE FFE tHA[30] R/W R INT L tINS[31] C138-23 Left Side Clears INTL: ADDRESSR CE L tINR[31] R/W L OE L INT L tRC READ FFE C138-24 Notes: 30. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 11 CY7C138 CY7C139 Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual–port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port–to–port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C138/9 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C138/9 has an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented as a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C138/9 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the a semaphore.If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all eight/nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No. 1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user of the CY7C138/9 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Interrupts The interrupt flag (INT) permits communications between ports.When the left port writes to location FFF, the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location FFE. This flag is cleared when the left port reads location FFE. The message at FFF or FFE is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate. Busy The CY7C138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other the Busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device 12 CY7C138 CY7C139 Table 1. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L Outputs I/O0-7/8 High Z Data Out High Z Data In Data Out Data In Operation Power-Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Set Left INT Reset Left INT Set Right INT Reset Right INT Table 3. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Status R/W X X L X CE X L L X OE X L X X A0-11 X FFE FFF X INT L H X X R/W L X X X CE L X X L Right Port OE X X X L A0-11 FFE X X FFF INT X X L H 13 CY7C138 CY7C139 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 0.6 0.4 0.2 0.0 4.0 4.5 5.0 5.5 6.0 0.4 0.2 0.6 –55 25 125 VCC =5.0V VIN =5.0V ICC ISB3 1.2 ICC 1.0 0.8 ISB3 120 80 40 0 0 1.0 2.0 3.0 4.0 5.0 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) VCC =5.0V TA =25°C 160 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 200 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE SUPPLYVOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25_C 1.0 1.6 1.4 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 1.2 80 60 VCC=5.0V 0.8 0.6 -55 40 20 25 125 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC =5.0V TA =25°C 1.0 2.0 3.0 4.0 5.0 0 0.0 SUPPLYVOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.00 30.0 25.0 0.75 20.0 15.0 10.0 0.25 5.0 0.0 0 1.0 2.0 3.0 4.0 5.0 0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC vs.CYCLE TIME VCC =5.0V TA =25°C VIN =0.5V 1.0 0.50 0.75 VCC =4.5V TA =25°C 0 200 400 600 800 1000 0.50 10 28 40 66 SUPPLYVOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) 14 CY7C138 CY7C139 Ordering Information 4K x8 Dual-Port SRAM Speed (ns) 15 25 35 55 Ordering Code CY7C138–15JC CY7C138–25JC CY7C138–25JI CY7C138–35JC CY7C138–35JI CY7C138–55JC CY7C138–55JI 4K x9 Dual-Port SRAM Speed (ns) 15 25 35 55 Ordering Code CY7C139–15JC CY7C139–25JC CY7C139–25JI CY7C139–35JC CY7C139–35JI CY7C139–55JC CY7C139–55JI Document #: 38–00536 Package Type J81 J81 J81 J81 J81 J81 J81 Package Type 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Package Name J81 J81 J81 J81 J81 J81 J81 Package Type 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier 68–Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Package Diagram 68-Lead Plastic Leaded Chip Carrier J81 © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.