CY7C1399B-15ZXCT

CY7C1399B 256K(32K x 8) Static RAM Features active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 10/12/15 ns • Low active power — 216 mW (max.) • Low-power alpha immune 6T cell • Plastic SOJ and TSOP packaging Functional Description[1] The CY7C1399B is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399B is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUT BUFFER I/O1 ROW DECODER I/O 0 I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 32K x 8 ARRAY I/O1 I/O2 GND I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 A 14 A 12 A 13 A 11 A 10 OE Selection Guide Maximum Access Time 1399B-10 1399B-12 1399B-15 1399B-20 Unit 10 12 15 20 ns Maximum Operating Current 60 55 50 45 mA Maximum CMOS Standby Current 500 500 500 500 µA 50 50 50 50 µA L Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05071 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 11, 2005 CY7C1399B Pin Configuration TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 21 22 23 20 19 18 17 16 15 14 13 12 11 10 9 8 24 25 26 27 28 1 2 3 4 5 6 7 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V Commercial DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Industrial Ambient Temperature VCC 0°C to +70°C 3.3V ±300 mV –40°C to +85°C 3.3V ±300 mV Electrical Characteristics Over the Operating Range[1] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[2] 7C1399B-10 7C1399B-12 Min. Min. Max. 2.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC +0.3V 2.2 VCC +0.3V V –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA IIX Input Load Current IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 55 mA ISB1 Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL,f = fMAX 5 5 mA 4 4 mA Automatic CE Power-Down Current — CMOS Inputs[4] Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, L WE ≥VCC – 0.3V or WE ≤0.3V, f = fMAX 500 500 µA 50 50 µA ISB2 L Notes: 2. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Device draws low standby current regardless of switching on the addresses. Document #: 38-05071 Rev. *D Page 2 of 10 CY7C1399B Electrical Characteristics Over the Operating Range (continued) 1399B-15 Parameter Description Test Conditions Min. 2.4 VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA VIH Input HIGH Voltage 2.2 VCC +0.3V VIL Input LOW Voltage –0.3 IIX Input Load Current IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND ICC VCC Operating Supply Current ISB1 ISB2 1399B-20 Max. Min. Max. Unit 2.4 V 0.4 0.4 V 2.2 VCC +0.3V V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA –300 –300 mA VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 50 45 mA Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL, f = fMAX 5 5 mA 4 4 mA Automatic CE Power-Down Current — CMOS Inputs[4] Max. VCC, CE ≥ VCC–0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, WE≥VCC–0.3V or WE≤ 0.3V, f=fMAX 500 500 µA 50 50 µA L L Capacitance[5] Parameter Description CIN: Addresses Input Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 5 pF 6 pF 6 pF CIN: Controls COUT Output Capacitance AC Test Loads and Waveforms R1 317Ω 3.3V ALL INPUT PULSES OUTPUT 3.0V R2 351Ω CL INCLUDING JIG AND SCOPE Equivalent to: 10% GND ≤ 3 ns 90% 90% 10% ≤ 3 ns THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05071 Rev. *D Page 3 of 10 CY7C1399B Switching Characteristics Over the Operating Range[6] 1399B-10 Parameter Description Min. Max. 1399B-12 Min. Max. Unit Read Cycle tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 5 ns [7] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z tHZCE CE HIGH to High Z[7, 8] tPU CE LOW to Power-Up tPD Write 10 3 12 3 ns 5 3 5 0 ns ns 6 0 10 ns ns 0 5 CE HIGH to Power-Down ns 3 0 [7, 8] [7] 12 ns ns 12 ns Cycle[9, 10] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 8 8 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5 7 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[9] tLZWE Z[7] WE HIGH to Low 0 7 3 ns 7 3 ns ns Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05071 Rev. *D Page 4 of 10 CY7C1399B Switching Characteristics Over the Operating Range[6] (continued) 1399B-15 Parameter Description Min. 1399B-20 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 15 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 15 20 ns tDOE OE LOW to Data Valid 6 7 ns OE LOW to Low Z tHZOE OE HIGH to High Z[7, 8] tLZCE CE LOW to Low tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 3 0 ns 6 3 3 ns ns 7 7 0 ns ns 6 Z[7, 8] CE HIGH to High 20 3 0 Z[7] tHZCE ns 15 [7] tLZOE 20 0 ns ns 15 20 ns Cycle[9, 10] Write tWC Write Cycle Time 15 20 ns tSCE CE LOW to Write End 10 12 ns tAW Address Set-Up to Write End 10 12 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 10 12 ns tSD Data Set-Up to Write End 8 10 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z[9] WE HIGH to Low Z[7] 7 7 3 3 ns ns Data Retention Characteristics (Over the Operating Range - L version only) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Document #: 38-05071 Rev. *D Conditions Min. Max. 2.0 Com’l VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V 0 Unit V 20 µA 0 ns tRC ns Page 5 of 10 CY7C1399B Data Retention Waveform DATA RETENTION MODE VDR > 2V 3.0V VCC 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[12, 13] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05071 Rev. *D Page 6 of 10 CY7C1399B Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[9, 14, 15] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 16 tHD DATAINVALID tHZOE Write Cycle No. 2 (CE Controlled)[9, 14, 15] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAINVALID Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATA IN VALID NOTE 16 tHZWE tLZWE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05071 Rev. *D Page 7 of 10 CY7C1399B Truth Table CE WE OE Input/Output Mode Power H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 12 15 20 Ordering Code Package Name Package Type CY7C1399B-12VC V21 28-Lead Molded SOJ CY7C1399B-12VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399B-12ZC Z28 28-Lead Thin Small Outline Package CY7C1399B-12ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) Operating Range Commercial CY7C1399BL-12ZC Z28 28-Lead Thin Small Outline Package CY7C1399BL-12ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399B-12VXI V21 28-Lead Molded SOJ (Pb-Free) Industrial CY7C1399B-15VC V21 28-Lead Molded SOJ Commercial CY7C1399B-15VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399B-15ZC Z28 28-Lead Thin Small Outline Package CY7C1399B-15ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399BL-15VC V21 28-Lead Molded SOJ CY7C1399BL-15VXC V21 28-Lead Molded SOJ (Pb-Free) CY7C1399BL-15ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399B-15VI V21 28-Lead Molded SOJ CY7C1399B-15VXI V21 28-Lead Molded SOJ (Pb-Free) CY7C1399B-15ZI Z28 28-Lead Thin Small Outline Package CY7C1399B-15ZXI Z28 28-Lead Thin Small Outline Package (Pb-Free) CY7C1399B-20ZC Z28 28-Lead Thin Small Outline Package CY7C1399B-20ZXC Z28 28-Lead Thin Small Outline Package (Pb-Free) Document #: 38-05071 Rev. *D Industrial Commercial Page 8 of 10 CY7C1399B Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 MIN. MAX. DIMENSIONS IN INCHES PIN 1 ID 14 DETAIL A EXTERNAL LEAD DESIGN 1 0.291 0.300 15 0.330 0.350 OPTION 1 0.697 0.713 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 A 0.050 TYP. 0.026 0.032 0.013 0.019 28 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*B 28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28 51-85071-*G All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05071 Rev. *D Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1399B Document History Page Document Title: CY7C1399B 256K(32K x 8) Static RAM Document Number: 38-05071 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 107264 05/25/01 SZV Change from Spec #: 38-01102 to 38-05071 *A 107533 06/28/01 MAX Add Low Power *B 116472 09/17/02 CEA Add applications foot note to data sheet, page 1. *C 224340 See ECN RKF Option 1 of the Orientation ID on TSOP-I Package Diagram [Page #9] removed *D 386100 See ECN SYT Converted the Datasheet from “Preliminary” to “Final” Added Pb-Free offerings in the Ordering Information Edited the title to “256K (32K x 8) Static RAM” from “32K x 8 3.3V Static RAM” Document #: 38-05071 Rev. *D DESCRIPTION OF CHANGE Page 10 of 10