CY7C1399BN-15VXCT

CY7C1399BN 256K (32K x 8) Static RAM Features expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. • Temperature Ranges — Industrial: –40°C to 85°C An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. — Automotive-A: –40°C to 85°C • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed: 12 ns • Low active power — 180 mW (max.) • Low-power alpha immune 6T cell • Available in Pb-free and non Pb-free Plastic SOJ and TSOP I packages Functional Description[1] The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399BN is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. The CY7C1399BN is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 32K x 8 ARRAY I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O7 A 14 A 12 A 13 A 11 A 10 OE Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (µA) Commercial -12 -15 -20 12 15 20 55 50 45 500 500 500 50 Commercial (L) 50 50 Industrial 500 500 Automotive-A 500 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06490 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 31, 2006 [+] Feedback CY7C1399BN Pin Configuration TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 21 22 23 20 19 18 17 16 15 14 13 12 11 10 9 8 24 25 26 27 28 1 2 3 4 5 6 7 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V Commercial 0°C to +70°C 3.3V ±300 mV DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Industrial –40°C to +85°C Automotive-A –40°C to +85°C Electrical Characteristics Over the Operating Range[1] -12 Parameter Description Test Conditions Min. -15 Max. 2.4 -20 Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3V 2.2 VCC + 0.3V VIL Input LOW Voltage[2] –0.3 0.8 –0.3 IIX Input Leakage Current –1 +1 IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –5 +5 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current— TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL, f = fMAX 0.4 Automatic CE Power-Down Current— CMOS Inputs[3] Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC + 0.3V V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA 55 50 45 mA Comm’l 5 5 5 mA Comm’l (L) 4 4 Ind’l 5 5 Auto-A ISB2 Min. Max. VCC, CE ≥ VCC – 0.3V, Comm’l VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, Comm’l (L) WE ≥VCC – 0.3V or WE ≤ 0.3V, Ind’l f = fMAX Auto-A mA 5 500 µA 500 500 50 50 µA 500 500 µA 500 µA Notes: 2. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns. 3. Device draws low standby current regardless of switching on the addresses. Document #: 001-06490 Rev. *A Page 2 of 8 [+] Feedback CY7C1399BN Capacitance[4] Parameter Description CIN: Addresses Test Conditions Input Capacitance CIN: Controls COUT Max. Unit 5 pF 6 pF 6 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Output Capacitance AC Test Loads and Waveforms[5] R1 317Ω 3.3V ALL INPUT PULSES 3.0V OUTPUT INCLUDING JIG AND SCOPE CL GND R2 351Ω 10% Equivalent to: 90% 10% 90% THÉVENINEQUIVALENT 167Ω OUTPUT 1.73V ≤ 3 ns ≤ 3 ns Switching Characteristics Over the Operating Range[5] -12 Parameter Description Min. -15 Max. Min. -20 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 15 20 ns tDOE OE LOW to Data Valid 5 6 7 ns tLZOE OE LOW to Low 12 Z[6] 12 3 OE HIGH to High tLZCE CE LOW to Low Z[6] tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 15 5 0 20 6 0 12 ns 6 3 7 ns ns 7 0 15 ns ns 0 3 6 ns 3 0 3 Z[6, 7] 20 3 0 Z[6, 7] tHZOE 15 ns ns 20 ns Write Cycle[8, 9] tWC Write Cycle Time 12 15 20 ns tSCE CE LOW to Write End 8 10 12 ns tAW Address Set-Up to Write End 8 10 12 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 8 10 12 ns tSD Data Set-Up to Write End 7 8 10 ns tHD Data Hold from Write End 0 0 0 ns tHZWE tLZWE WE LOW to High Z [8] [6] WE HIGH to Low Z 7 3 7 3 7 3 ns ns Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06490 Rev. *A Page 3 of 8 [+] Feedback CY7C1399BN Data Retention Characteristics (Over the Operating Range - L version only) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Min. Max. Unit 20 µA 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V V 0 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[11, 12] tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZOE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU ICC 50% 50% ISB Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 001-06490 Rev. *A Page 4 of 8 [+] Feedback CY7C1399BN Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[8, 13, 14] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 15 tHD DATAINVALID tHZOE Write Cycle No. 2 (CE Controlled)[8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAINVALID Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATA IN VALID NOTE 15 tHZWE tLZWE Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 001-06490 Rev. *A Page 5 of 8 [+] Feedback CY7C1399BN Truth Table CE WE OE H X X High Z Input/Output Deselect/Power-Down Mode Standby (ISB) Power L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1399BN-12VC Package Diagram 51-85031 28-Lead Molded SOJ 51-85071 28-Lead TSOP I CY7C1399BN-12VXC CY7C1399BN-12ZC CY7C1399BN-12ZXC 28-Lead TSOP I (Pb-free) CY7C1399BNL-12ZC 28-Lead TSOP I CY7C1399BN-12VXI 28-Lead Molded SOJ 28-Lead Molded SOJ (Pb-free) 51-85071 CY7C1399BN-15ZXC Commercial 28-Lead TSOP I 28-Lead TSOP I (Pb-free) 51-85031 28-Lead Molded SOJ (Pb-free) CY7C1399BN-15VI 28-Lead Molded SOJ CY7C1399BN-15VXI 28-Lead Molded SOJ (Pb-free) CY7C1399BN-15ZI Industrial 28-Lead TSOP I (Pb-free) CY7C1399BNL-15ZXC 51-85071 CY7C1399BN-15ZXI 20 28-Lead Molded SOJ (Pb-free) CY7C1399BN-15VXC CY7C1399BNL-15VXC Commercial 28-Lead TSOP I (Pb-free) 51-85031 CY7C1399BN-15VC CY7C1399BN-15ZC Operating Range 28-Lead Molded SOJ (Pb-free) CY7C1399BNL-12ZXC 15 Package Type Industrial 28-Lead TSOP I 28-Lead TSOP I (Pb-free) CY7C1399BN-15VXA 51-85031 28-Lead Molded SOJ (Pb-free) CY7C1399BN-20ZXC 51-85071 28-Lead TSOP I (Pb-free) Automotive-A Commercial Please contact local sales representative regarding availability of these parts. Document #: 001-06490 Rev. *A Page 6 of 8 [+] Feedback CY7C1399BN Package Diagrams 28-Lead (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 A 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C 28-Lead TSOP 1 (8x13.4 mm) (51-85071) 51-85071-*G All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06490 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1399BN Document History Page Document Title: CY7C1399BN 256K (32K x 8) Static RAM Document Number: 001-06490 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 423877 See ECN NXR New Data Sheet *A 498575 See ECN NXR Added Automotive-A range Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information table. Document #: 001-06490 Rev. *A DESCRIPTION OF CHANGE Page 8 of 8 [+] Feedback