CY7C141-55NC

CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 110 mA (max.) • Fully asynchronous operation • Automatic power-down • Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141 • BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141 • INT flag for port-to-port communication • Available in 48-pin DIP (CY7C130/140), 52-pin PLCC, 52-Pin TQFP. • Pb-Free packages available Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130 and CY7C140 are available in 48-pin DIP. The CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP. Logic Block Diagram R/WL CEL OEL R/WR CER OER Pin Configurations DIP Top View CE L R/W L BUSY L INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 12 7C130 37 13 7C140 36 14 35 15 34 16 33 17 32 18 31 30 19 20 29 28 21 22 27 23 26 24 25 VCC CER R/WR BUSY R INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O0L BUSYL I/O CONTROL I/O CONTROL I/O7R I/O0R BUSYR [1] A 9L A 0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER A 9R A 0R CEL OEL R/WL INTL ARBITRATION LOGIC (7C130/7C131 ONLY) AND INTERRUPT LOGIC CER OER R/WR INTR [2] [2] Note: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor CY7C140/CY7C141 (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required. Cypress Semiconductor Corporation Document #: 38-06002 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 29, 2005 CY7C130/CY7C131 CY7C140/CY7C141 Pin Configuration (continued) PLCC Top View BUSY R INTR NC BUSYL R/W L CEL VCC CER R/W R A0L OEL NC INT L A0L OEL NC INT L PQFP Top View BUSY R INTR NC BUSYL R/W L CEL VCC CER R/W R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C131 40 7C141 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L NC GND OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 52 5150 49 48 47 4645 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R 7C131 7C141 1415 16 17 18 19 20 21 22 23 24 25 26 NC GND I/O0R I/O1R Pin Definitions Left Port CEL R/WL OEL A0L–A11/12L I/O0L–I/O15/17L INTL BUSYL VCC GND CER R/WR OER A0R–A11/12R I/O0R–I/O15/17R INTR BUSYR Right Port Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output Interrupt Flag Busy Flag Power Ground Description Selection Guide 7C131-15[3] 7C141-15 Maximum Access Time Maximum Operating Com’l/Ind Current Military Maximum Standby Current Com’l/Ind Military 15 190 75 7C131-25[3] 7C141-25 25 170 65 7C130-30 7C131-30 7C140-30 7C141-30 30 170 65 7C130-35 7C131-35 7C140-35 7C141-35 35 120 170 45 65 7C130-45 7C131-45 7C140-45 7C141-45 45 120 170 45 65 7C130-55 7C131-55 7C140-55 7C141-55 55 110 120 35 45 mA I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L Unit ns mA Shaded areas contain preliminary information. Note: 3. 15 and 25-ns version available only in PLCC/PQFP packages. Document #: 38-06002 Rev. *D Page 2 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Maximum Ratings[4] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –3.5V to +7.0V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial Military [5] Ambient Temperature 0°C to +70°C –40°C to +85°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[6] 7C131-15[3] 7C141-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled –5 –5 Test Conditions VCC = Min., IOH = –4.0 mA IOL = 4.0 mA IOL = 16.0 mA[7] 2.2 0.8 +5 +5 –350 Com’l Mil Com’l Mil 135 115 75 65 190 –5 –5 Min. 2.4 0.4 0.5 2.2 0.8 +5 +5 –350 170 –5 –5 Max. 7C130-30[3] 7C131-25,30 7C140-30 7C141-25,30 Min. 2.4 0.4 0.5 2.2 0.8 +5 +5 –350 120 170 45 65 90 115 15 15 15 15 –5 –5 Max. 7C130-35,45 7C131-35,45 7C140-35,45 7C141-35,45 Min. 2.4 0.4 0.5 2.2 0.8 +5 +5 Max. 7C130-55 7C131-55 7C140-55 7C141-55 Min. 2.4 0.4 0.5 V V µA µA Max. Unit V V Output Short VCC = Max., Circuit Current[8, 9] VOUT = GND VCC Operating Supply Current Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs CE = VIL, Outputs Open, f = fMAX[10] CEL and CER > VIH, f = fMAX[10] –350 mA 110 120 35 45 75 90 15 15 mA mA mA mA ISB1 ISB2 CEL or CER > VIH, Com’l Active Port Outputs Mil Open, [10] f = fMAX Both Ports CEL and Com’l CER > Mil VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 ISB3 Shaded areas contain preliminary information. Note: 4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 5. TA is the “instant on” case temperature 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Duration of the short circuit should not exceed 30 seconds. 9. This parameter is guaranteed but not tested. 10. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V. Document #: 38-06002 Rev. *D Page 3 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Electrical Characteristics Over the Operating Range[6] (continued) 7C131-15[3] 7C141-15 Parameter ISB4 Description Standby Current One Port, CMOS Inputs Test Conditions One Port CEL or Com’l CER > VCC – 0.2V, Mil VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[10] Min. Max. 125 7C130-30[3] 7C131-25,30 7C140-30 7C141-25,30 Min. Max. 105 7C130-35,45 7C131-35,45 7C140-35,45 7C141-35,45 Min. Max. 85 105 7C130-55 7C131-55 7C140-55 7C141-55 Min. Max. Unit 70 85 mA Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIGAND SCOPE Equivalent to: OUTPUT R2 347Ω (a) THÉVENIN EQUIVALENT 250Ω 1.40V R1 893Ω 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R2 347Ω (b) 3.0V GND 10% ALL INPUT PULSES 90% 90% 10% ≤5ns BUSY OR INT R1 893Ω 5V 281Ω 30 pF BUSY Output Load (CY7C130/CY7C131 ONLY) ≤ 5 ns Document #: 38-06002 Rev. *D Page 4 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Characteristics Over the Operating Range[6, 11] 7C131-15 7C141-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid [12] [3] 7C130-25[3] 7C131-25 7C140-25 7C141-25 Min. 25 Max. 7C130-30 7C131-30 7C140-30 7C141-30 Min. 30 Max. Unit ns 30 0 30 20 3 15 5 15 0 25 30 25 25 2 0 25 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 0 ns ns Description Min. 15 Max. 15 0 15 10 3 10 3 10 0 15 15 12 12 2 0 12 10 0 10 0 0 25 20 20 2 0 15 15 0 0 5 3 0 25 25 15 15 15 25 Data Hold from Address Change CE LOW to Data Valid OE LOW to Low CE LOW to Low CE LOW to CYCLE[15] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z[14] R/W HIGH to Low Z [14] [12] [12] OE LOW to Data Valid Z[9, 13, 14] Z[9, 13, 14] Z[9, 13, 14] OE HIGH to High Z[9, 13, 14] CE HIGH to High Power-Up[9] CE HIGH to Power-Down[9] 15 Shaded areas contain preliminary information. Note: 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 12. AC Test Conditions use VOH = 1.6V and VOL = 1.4V. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-06002 Rev. *D Page 5 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Characteristics Over the Operating Range[6, 11] (continued) 7C131-15[3] 7C141-15 Parameter BUSY/INTERRUPT TIMING tBLA tBHA tBLC tBHC tPS tWB[17] tWH tBDD tDDD tWDD tWINS tEINS tINS tOINR tEINR tINR BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset CE to INTERRUPT Reset Time[16] Time[16] [16] [16] 7C130-25[3] 7C131-25 7C140-25 7C141-25 Min. Max. 20 20 20 20 5 0 20 7C130-30 7C131-30 7C140-30 7C141-30 Min. Max. 20 20 20 20 5 0 30 Unit ns ns ns ns ns ns ns 30 Note 18 Note 18 25 25 25 25 25 25 ns ns ns ns ns ns ns ns ns Description Min. Max. 15 15 15 15 5 0 13 15 Note 18 Note 18 15 15 15 15 15 15 25 Note 18 Note 18 25 25 25 25 25 25 INTERRUPT TIMING Address to INTERRUPT Reset Time[16] Shaded areas contain preliminary information. Note: 16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. CY7C140/CY7C141 only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address is toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Switching Characteristics Over the Operating Range[6,11] 7C130-35 7C131-35 7C140-35 7C141-35 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE Read Cycle Time Address to Data Valid [12] 7C130-45 7C131-45 7C140-45 7C141-45 Min. 45 Max. 7C130-55 7C131-55 7C140-55 7C141-55 Min. 55 Max. Unit ns 55 0 55 25 3 25 5 ns ns ns ns ns ns ns Description Min. 35 Max. 35 0 35 20 3 20 5 5 3 0 45 45 25 20 Data Hold from Address Change CE LOW to Data Valid[12] OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z [12] [9, 13, 14] [9, 13, 14] CE LOW to Low Z[9, 13, 14] Document #: 38-06002 Rev. *D Page 6 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Characteristics Over the Operating Range[6,11] (continued) 7C130-35 7C131-35 7C140-35 7C141-35 Parameter tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB[17] tWH tBDD tDDD tWDD Description CE HIGH to High Z [9, 13, 14] [9] [9] 7C130-45 7C131-45 7C140-45 7C141-45 Min. 0 Max. 20 7C130-55 7C131-55 7C140-55 7C141-55 Min. 0 Max. 25 35 55 40 40 2 0 30 20 0 Unit ns ns ns ns ns ns ns ns ns ns ns 25 0 ns ns 30 30 30 30 5 0 35 ns ns ns ns ns ns ns 45 Note 18 Note 18 45 45 45 45 45 45 ns ns ns Min. 0 Max. 20 35 CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End 35 45 35 35 2 0 30 20 0 WRITE CYCLE[15] 35 30 30 2 0 25 15 0 20 0 20 20 20 20 5 0 30 35 Note 18 Note 18 25 25 25 25 25 25 5 0 35 45 Note 18 Note 18 35 35 35 35 35 35 0 25 25 25 25 Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z[14] R/W HIGH to Low Z[14] BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[16] Port Set Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Mismatch[16] 20 BUSY/INTERRUPT TIMING INTERRUPT TIMING tWINS tEINS tINS tOINR tEINR tINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset CE to INTERRUPT Reset Time[16] Time[16] ns ns ns ns ns ns Address to INTERRUPT Reset Time[16] Document #: 38-06002 Rev. *D Page 7 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Waveforms Read Cycle No. 1[19, 20] Either Port Address Access tRC ADDRESS tOHA DATA OUT PREVIOUS DATAVALID tAA DATA VALID Read Cycle No. 2[19, 21] Either Port CE/OE Access CE OE tLZOE tLZCE DATA OUT tPU ICC ISB DATA VALID tPD tACE tDOE tHZOE tHZCE Read Cycle No. 3[20] Read with BUSY, Master: CY7C130 and CY7C131 tRC ADDRESSR R/WR DINR ADDRESSL tPS BUSYL tBLA DOUTL tWDD tDDD tBHA tBDD VALID ADDRESS MATCH tPWE tHD VALID ADDRESS MATCH Notes: 19. R/W is HIGH for read cycle. 20. Device is continuously selected, CE = VIL and OE = VIL. 21. Address valid prior to or coincident with CE transition LOW. Document #: 38-06002 Rev. *D Page 8 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Waveforms (continued) Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[15, 22] Either Port tWC ADDRESS tSCE CE tSA R/W tSD DATAIN OE tHZOE DOUT HIGH IMPEDANCE DATA VALID tHD tAW tPWE tHA Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23] tWC ADDRESS tSCE CE tSA R/W tSD DATAIN tHZWE DATAOUT Notes: 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. tHA tAW tPWE tHD DATA VALID tLZWE HIGH IMPEDANCE Document #: 38-06002 Rev. *D Page 9 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESS L, R CEL tPS ADDRESS MATCH CER tBLC BUSYR tBHC CER Valid First: ADDRESSL,R CER tPS ADDRESS MATCH CEL tBLC BUSYL tBHC Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS MATCH tPS ADDRESS MISMATCH ADDRESSL ADDRESS R BUSYR tBLA tBHA Right Address Valid First: tRC or tWC ADDRESS MATCH tPS ADDRESS MISMATCH ADDRESSR ADDRESSL BUSYL tBLA tBHA Document #: 38-06002 Rev. *D Page 10 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Waveforms (continued) Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141) CE tPWE R/W tWB BUSY tWH Document #: 38-06002 Rev. *D Page 11 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR ADDRL tINS CEL tEINS R/WL tSA INTR tWINS tWC WRITE 3FF tHA Right Side Clears INTR tRC ADDRR tHA CER tEINR R/WR OER tOINR INTR READ 3FF tINT Right Side Sets INTL t WC ADDRR tINS CER tEINS R/WR INTL tSA tWINS WRITE 3FE tHA Left Side Clears INTL ADDRR CEL tEINR R/WL OEL tOINR INTL tHA tRC READ 3FE tINR Document #: 38-06002 Rev. *D Page 12 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZED ICC, ISB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 1.0 0.8 0.6 0.4 0.2 0.6 –55 25 VCC = 5.0V VIN = 5.0V I SB3 125 ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25°C 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 ICC I SB3 4.5 5.0 5.5 6.0 0.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT SOURCE CURRENT (mA) OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25°C NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 –55 140 120 100 80 60 40 20 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 25 125 0 0.0 VCC = 5.0V TA = 25°C 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED tPC 2.5 2.0 1.5 1.0 0.5 0.0 0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 DELTA tAA (ns) 20.0 15.0 10.0 5.0 0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC NORMALIZED ICC vs. CYCLE TIME VCC = 4.5V TA = 25°C VIN = 0.5V 1.0 0.75 VCC = 4.5V TA = 25°C 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CYCLE FREQUENCY (MHz) Document #: 38-06002 Rev. *D Page 13 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Ordering Information Speed (ns) 30 35 Ordering Code CY7C130-30PC CY7C130-30PI CY7C130-35PC CY7C130-35PI CY7C130-35DMB 45 CY7C130-45PC CY7C130-45PI CY7C130-45DMB 55 CY7C130-55PC CY7C130-55PI CY7C130-55DMB 15 CY7C131-15JC CY7C131-15JXC CY7C131-15NC CY7C131-15JI CY7C131-15JXI 25 CY7C131-25JC CY7C131-25JXC CY7C131-25NC CY7C131-25NXC CY7C131-25JI CY7C131-25NI 30 CY7C131-30JC CY7C131-30NC CY7C131-30JI 35 CY7C131-35JC CY7C131-35NC CY7C131-35JI CY7C131-35NI 45 CY7C131-45JC CY7C131-45NC CY7C131-45JI CY7C131-45NI 55 CY7C131-55JC CY7C131-55JXC CY7C131-55NC CY7C131-55NXC CY7C131-55JI CY7C131-55JXI CY7C131-55NI Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 J69 J69 N52 J69 J69 J69 J69 N52 N52 J69 N52 J69 N52 J69 J69 N52 J69 N52 J69 N52 J69 N52 J69 J69 N52 N52 J69 J69 N52 Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Pb-Free Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Pb-Free Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack Industrial Commercial Industrial Commercial Industrial Industrial Commercial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Commercial Document #: 38-06002 Rev. *D Page 14 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Ordering Information (continued) Speed (ns) 30 35 Ordering Code CY7C140-30PC CY7C140-30PI CY7C140-35PC CY7C140-35PI CY7C140-35DMB 45 CY7C140-45PC CY7C140-45PI CY7C140-45DMB 55 CY7C140-55PC CY7C140-55PI CY7C140-55DMB 15 25 CY7C141-15JC CY7C141-15NC CY7C141-25JC CY7C141-25JXC CY7C141-25NC CY7C141-25JI CY7C141-25NI 30 CY7C141-30JC CY7C141-30NC CY7C141-30JI 35 CY7C141-35JC CY7C141-35NC CY7C141-35JI CY7C141-35NI 45 CY7C141-45JC CY7C141-45NC CY7C141-45JI CY7C141-45NI 55 CY7C141-55JC CY7C141-55NC CY7C141-55JI CY7C141-55NI Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 J69 N52 J69 J69 N52 J69 N52 J69 N52 J69 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52 Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack Industrial Commercial Industrial Commercial Industrial Industrial Commercial Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Commercial Document #: 38-06002 Rev. *D Page 15 of 19 CY7C130/CY7C131 CY7C140/CY7C141 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter READ CYCLE tRC tAA tACE tDOE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD BUSY/INTERRUPT TIMING tBLA tBHA tBLC tBHC tPS tWINS tEINS tINS tOINR tEINR tINR BUSY TIMING tWB[24] tWH tBDD Note: 24. CY7C140/CY7C141 only. Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Document #: 38-06002 Rev. *D Page 16 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C 51-80044 ** 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Pb-Free Plastic Leaded Chip Carrier J69 DIMENSIONS IN INCHES 0.004 MIN. MAX. PIN #1 ID SEATING PLANE 7 1 47 8 46 0.013 0.021 0.785 0.795 0.750 0.756 0.045 0.055 0.690 0.730 20 34 0.023 0.033 21 0.750 0.756 0.785 0.795 33 0.090 0.130 0.165 0.200 0.020 MIN. 51-85004-*A Document #: 38-06002 Rev. *D Page 17 of 19 CY7C130/CY7C131 CY7C140/CY7C141 Package Diagrams (continued) 48-Lead (600-Mil) Molded DIP P25 51-85020-*A 52-Lead Plastic Quad Flatpack N52 52-Lead Pb-Free Plastic Quad Flatpack N52 51-85042-** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06002 Rev. *D Page 18 of 19 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C130/CY7C131 CY7C140/CY7C141 Document History Page Document Title: CY7C130/CY7C131/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Document Number: 38-06002 REV. ** *A *B *C *D ECN NO. 110169 122255 236751 325936 393153 Issue Date 09/29/01 12/26/02 See ECN See ECN See ECN Orig. of Change SZV RBI YDT RUY YIM Description of Change Change from Spec number: 38-00027 to 38-06002 Power up requirements added to Maximum Ratings Information Removed cross information from features section Added pin definitions table, 52-pin PQFP package diagram and Pb-free information Added CY7C131-15JI to ordering information Added Pb-Free parts to ordering information: CY7C131-15JXI Document #: 38-06002 Rev. *D Page 19 of 19