CY7C1414KV18-250BZXIT

CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR® II SRAM Two-Word Burst Architecture 36-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1425KV18 – 4M × 9 ■ 333 MHz clock for high bandwidth CY7C1414KV18 – 1M × 36 ■ Two-word burst on all accesses Functional Description ■ Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 9-bit words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or 36-bit words (CY7C1414KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. ■ ■ Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW ■ Available in × 9, × 18, and × 36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD ❐ Supports both 1.5 V and 1.8 V I/O supply ■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm) ■ Offered in both Pb-free and non Pb-free Packages ■ Variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement CY7C1412KV18 – 2M × 18 Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related documentation, click here. Selection Guide Description Maximum operating frequency Maximum operating current Cypress Semiconductor Corporation Document Number: 001-57825 Rev. *O • 198 Champion Court • 333 MHz 300 MHz 250 MHz Unit 333 300 250 MHz mA ×9 730 680 590 × 18 750 700 610 × 36 910 850 730 San Jose, CA 95134-1709 • 408-943-2600 Revised January 3, 2018 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Logic Block Diagram – CY7C1425KV18 K CLK Gen. DOFF 21 Address Register Read Add. Decode K Write Reg 2M x 9 Array A(20:0) Address Register Write Reg 2M x 9 Array 21 9 Write Add. Decode D[8:0] A(20:0) RPS Control Logic C Read Data Reg. C CQ 18 VREF WPS BWS[0] 9 Control Logic Reg. 9 Reg. Reg. CQ 9 9 9 Q[8:0] Logic Block Diagram – CY7C1412KV18 K CLK Gen. DOFF 20 Address Register Read Add. Decode K Write Reg 1M x 18 Array Address Register Write Reg 1M x 18 Array A(19:0) 20 18 Write Add. Decode D[17:0] A(19:0) RPS Control Logic C Read Data Reg. C CQ 36 VREF WPS BWS[1:0] 18 Control Logic Document Number: 001-57825 Rev. *O 18 Reg. Reg. 18 Reg. 18 CQ 18 Q[17:0] Page 2 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Logic Block Diagram – CY7C1414KV18 K CLK Gen. DOFF 19 Address Register Read Add. Decode K Write Reg 512K x 36 Array Address Register Write Reg 512K x 36 Array A(18:0) 19 36 Write Add. Decode D[35:0] A(18:0) RPS Control Logic C Read Data Reg. C CQ 72 VREF WPS BWS[3:0] 36 Control Logic Document Number: 001-57825 Rev. *O 36 Reg. Reg. 36 Reg. 36 CQ 36 Q[35:0] Page 3 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 8 Read Operations ......................................................... 8 Write Operations ......................................................... 9 Byte Write Operations ................................................. 9 Concurrent Transactions ............................................. 9 Depth Expansion ......................................................... 9 Programmable Impedance .......................................... 9 Echo Clocks ................................................................ 9 PLL .............................................................................. 9 Application Example ...................................................... 10 Truth Table ...................................................................... 11 Write Cycle Descriptions ............................................... 11 Write Cycle Descriptions ............................................... 12 Write Cycle Descriptions ............................................... 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port ....................................................... 13 Performing a TAP Reset ........................................... 13 TAP Registers ........................................................... 13 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Electrical Characteristics ...................................... 16 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Document Number: 001-57825 Rev. *O Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in QDR II SRAM ........................... 21 Power Up Sequence ................................................. 21 PLL Constraints ......................................................... 21 Maximum Ratings ........................................................... 22 Operating Range ............................................................. 22 Neutron Soft Error Immunity ......................................... 22 Electrical Characteristics ............................................... 22 DC Electrical Characteristics ..................................... 22 AC Electrical Characteristics ..................................... 24 Capacitance .................................................................... 24 Thermal Resistance ........................................................ 24 AC Test Loads and Waveforms ..................................... 24 Switching Characteristics .............................................. 25 Switching Waveforms .................................................... 27 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Package Diagram ............................................................ 29 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC® Solutions ...................................................... 33 Cypress Developer Community ................................. 33 Technical Support ..................................................... 33 Page 4 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Pin Configurations The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [1] Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1425KV18 (4M × 9) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A WPS NC K NC/144M RPS A A CQ B NC NC NC A NC/288M K BWS0 A NC NC Q4 C NC NC NC VSS A A A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS A A A VSS NC NC NC P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI Note 1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-57825 Rev. *O Page 5 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Pin Configurations (continued) The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [1] Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1412KV18 (2M × 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A WPS BWS1 K NC/288M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS0 A NC NC Q8 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI 9 10 11 CY7C1414KV18 (1M × 36) 1 2 3 NC/288M NC/72M 4 5 6 7 8 A CQ WPS BWS2 K BWS1 RPS A NC/144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C A A A TMS TDI Document Number: 001-57825 Rev. *O Page 6 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData input signals. Sampled on the rising edge of K and K clocks during valid write operations. synchronous CY7C1425KV18  D[8:0] CY7C1412KV18  D[17:0] CY7C1414KV18  D[35:0] WPS InputWrite port select  active LOW. Sampled on the rising edge of the K clock. When asserted active, a synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. BWS0, BWS1, BWS2, BWS3 InputByte write select 0, 1, 2, and 3  active LOW. Sampled on the rising edge of the K and K clocks during synchronous write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1425KV18 BWS0 controls D[8:0]. CY7C1412KV18  BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1414KV18  BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. A InputAddress inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during synchronous active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M × 9 (2 arrays each of 2M × 9) for CY7C1425KV18, 2M × 18 (2 arrays each of 1M × 18) for CY7C1412KV18, and 1M × 36 (2 arrays each of 512K × 36) for CY7C1414KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1425KV18, 20 address inputs for CY7C1412KV18, and 19 address inputs for CY7C1414KV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputData output signals. These pins drive out the requested data during a read operation. Valid data is synchronous driven out on the rising edge of the C and C clocks during read operations, or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tristated. CY7C1425KV18  Q[8:0] CY7C1412KV18  Q[17:0] CY7C1414KV18  Q[35:0] RPS InputRead port select  active LOW. Sampled on the rising edge of positive input clock (K). When active, a synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. C Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the device. Use C and C together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. C Input clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from the device. Use C and C together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 25. CQ Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 25. Document Number: 001-57825 Rev. *O Page 7 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Pin Definitions (continued) Pin Name I/O Pin Description ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input PLL turn off  active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR I timing. TDO Output TDO pin for JTAG. TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/72M Input Not connected to the die. Can be tied to any voltage level. NC/144M Input Not connected to the die. Can be tied to any voltage level. NC/288M Input Not connected to the die. Can be tied to any voltage level. VREF VDD VSS VDDQ Inputreference Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Power supply Power supply inputs to the core of the device. Ground Ground for the device. Power supply Power supply inputs for the outputs of the device. Functional Overview rising edge of the output clocks (C and C, or K and K when in single clock mode). The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are synchronous pipelined burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 9-bit data transfers in the case of CY7C1425KV18, two 18-bit data transfers in the case of CY7C1412KV18, and two 36-bit data transfers in the case of CY7C1414KV18 in one clock cycle. All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then the device behaves in QDR I mode with a read latency of one clock cycle. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the Document Number: 001-57825 Rev. *O CY7C1412KV18 is described in the following sections. The same basic descriptions apply to CY7C1425KV18, and CY7C1414KV18. Read Operations The CY7C1412KV18 is organized internally as two arrays of 1M × 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. The address presented to the address inputs is stored in the read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode). Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the output clocks (C/C). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Page 8 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port ignores all inputs after the pending write operations are completed. Byte Write Operations Byte write operations are supported by the CY7C1412KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, or write operations to a byte write operation. Concurrent Transactions The read and write ports on the CY7C1412KV18 operate completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. The user can start reads and writes in the same clock cycle. If the ports access the same location at the same time, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Depth Expansion on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175  and 350 , with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 25. PLL These chips use a PLL which is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time). The CY7C1412KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled Document Number: 001-57825 Rev. *O Page 9 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Application Example Figure 2 shows two QDR II used in an application. Figure 2. Application Example (Width Expansion) SRAM#1 ZQ CQ/CQ D[x:0] Q[x:0] A RPS WPS BWS C C K K RQ SRAM#2 ZQ CQ/CQ D[x:0] Q[x:0] A RPS WPS BWS C C K K RQ DATA IN[2x:0] DATA OUT [2x:0] ADDRESS RPS WPS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K DELAYED K DELAYED K FPGA / ASIC Document Number: 001-57825 Rev. *O Page 10 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Truth Table The truth table for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write cycle: Load address on the rising edge of K; input write data on K and K rising edges. L–H X L D(A + 0) at K(t)  Read cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. L–H L X Q(A + 0) at C(t + 1)  Q(A + 1) at C(t + 2)  NOP: No operation L–H H H D=X Q = high Z D=X Q = high Z Stopped X X Previous state Previous state Standby: Clock stopped D(A + 1) at K(t)  Write Cycle Descriptions The write cycle description table for CY7C1412KV18 follow. [2, 8] BWS0 BWS1 K K L L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – Comments During the data portion of a write sequence CY7C1412KV18 both bytes (D[17:0]) are written into the device. L–H During the data portion of a write sequence: CY7C1412KV18 both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence: CY7C1412KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence CY7C1412KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence CY7C1412KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence CY7C1412KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57825 Rev. *O Page 11 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Write Cycle Descriptions The write cycle description table for CY7C1425KV18 follow. [9, 10] BWS0 K K L L–H – L – H L–H H – Comments During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1414KV18 follow. [9, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Notes 9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 10. Is based on a write cycle that was initiated in accordance with the Truth Table on page 11. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57825 Rev. *O Page 12 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8 V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO must be left unconnected. Upon power-up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 19). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and is performed when the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-57825 Rev. *O Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 16. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are used to capture the contents of the input and output ring. The Boundary Scan Order on page 20 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 19. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. Page 13 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 IDCODE BYPASS The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit is set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. Document Number: 001-57825 Rev. *O Page 14 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-57825 Rev. *O Page 15 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [12, 13, 14] Description Test Conditions Min Max Unit VOH1 Output HIGH voltage IOH =2.0 mA 1.4 – V VOH2 Output HIGH voltage IOH =100 A 1.6 – V VOL1 Output LOW voltage IOL = 2.0 mA – 0.4 V VOL2 Output LOW voltage IOL = 100 A – 0.2 V VIH Input HIGH voltage VIL Input LOW voltage IX Input and output load current 0.65 × VDD VDD + 0.3 GND  VI  VDD V –0.3 0.35 × VDD V –5 5 A Notes 12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 22. 13. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 14. All voltage referenced to Ground. Document Number: 001-57825 Rev. *O Page 16 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 TAP AC Switching Characteristics Over the Operating Range Parameter [15, 16] Description Min Max Unit 50 – ns tTCYC TCK clock cycle time tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH 20 – ns tTL TCK clock LOW 20 – ns tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns Setup Times Hold Times Output Times Notes 15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-57825 Rev. *O Page 17 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 TAP Timing and Test Conditions Figure 3 shows the TAP timing and test conditions. [17] Figure 3. TAP Timing and Test Conditions 0.9V ALL INPUT PULSES 1.8V 50 0.9V TDO 0V Z0 = 50 (a) CL = 20 pF tTH GND tTL Test Clock TCK tTMSH tTMSS tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-57825 Rev. *O Page 18 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Identification Register Definitions Value Instruction Field CY7C1425KV18 Revision number (31:29) CY7C1412KV18 CY7C1414KV18 Description 000 000 000 Cypress device ID (28:12) 11010011010001111 11010011010010111 11010011010100111 Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. 1 1 1 Indicates the presence of an ID register. ID register presence (0) Version number. Defines the type of SRAM. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-57825 Rev. *O Page 19 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-57825 Rev. *O Page 20 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Power Up Sequence in QDR II SRAM PLL Constraints QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL. ~ ~ Figure 4. Power Up Waveforms K K ~ ~ Unstable Clock > 20μs Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF Document Number: 001-57825 Rev. *O V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to VDDQ) Page 21 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Range Storage temperature ................................ –65 °C to +150 °C Commercial Ambient temperature with power applied ................................... –55 °C to +125 °C Industrial Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC input voltage VDD[19] VDDQ[19] 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to VDD –40 °C to +85 °C Neutron Soft Error Immunity DC applied to outputs in high Z ........ –0.5 V to VDDQ + 0.5 V [18] Ambient Temperature (TA) ........................... –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, M. 3015) ......................................... > 2001 V Latch-up current .................................................... > 200 mA Parameter Description Test Conditions Typ Max* Unit LSBU Logical single-bit upsets 25 °C 197 216 FIT/ Mb LMBU Logical Multi-Bit upsets 25 °C 0 0.01 FIT/ Mb Single event latchup 85 °C 0 0.1 FIT/ Dev SEL * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [20] Description VDD Power supply voltage Test Conditions Min Typ Max Unit 1.7 1.8 1.9 V VDDQ I/O supply voltage 1.4 1.5 VDD V VOH Output HIGH voltage Note 21 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOL Output LOW voltage Note 22 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOH(LOW) Output HIGH voltage IOH =0.1 mA, nominal impedance VDDQ – 0.2 – VDDQ V IOL = 0.1 mA, nominal impedance VOL(LOW) Output LOW voltage VSS – 0.2 V VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.3 V VIL Input LOW voltage –0.3 – VREF – 0.1 V IX Input leakage current GND  VI  VDDQ 5 – 5 A IOZ Output leakage current GND  VI  VDDQ, output disabled VREF Input reference voltage [23] Typical value = 0.75 V 5 – 5 A 0.68 0.75 0.95 V Notes 18. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 19. Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ  VDD. 20. All voltage referenced to Ground. 21. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175   RQ 350 . 22. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 . 23. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller. Document Number: 001-57825 Rev. *O Page 22 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Electrical Characteristics (continued) Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [20] IDD [24] ISB1 Description VDD operating supply Automatic power-down current Test Conditions Min Typ Max Unit VDD = Max, IOUT = 0 mA, 333 MHz (× 9) f = fMAX = 1/tCYC (× 18) – – 730 mA – – 750 (× 36) – – 910 300 MHz (× 9) – – 680 (× 18) – – 700 (× 36) – – 850 250 MHz (× 9) – – 590 (× 18) – – 610 (× 36) – – 730 333 MHz (× 9) – – 280 (× 18) – – 280 Max VDD, both ports deselected, VIN  VIH or VIN  VIL f = fMAX = 1/tCYC, Inputs Static (× 36) – – 280 300 MHz (× 9) – – 270 (× 18) – – 270 (× 36) – – 270 250 MHz (× 9) – – 260 (× 18) – – 260 (× 36) – – 260 mA mA mA mA mA Note 24. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-57825 Rev. *O Page 23 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 AC Electrical Characteristics Over the Operating Range Parameter [25] Description Test Conditions Min Typ Max Unit VIH Input HIGH voltage VREF + 0.2 – – V VIL Input LOW voltage – – VREF – 0.2 V Max Unit 4 pF 4 pF Capacitance Parameter [26] Description Test Conditions TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V CIN Input capacitance CO Output capacitance Thermal Resistance Parameter [26] JA (0 m/s) JA (1 m/s) Description 165-ball FBGA Unit Package Test Conditions Thermal resistance (junction to ambient) Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit board JA (3 m/s) 16.72 °C/W 15.67 °C/W 14.92 °C/W JB Thermal resistance (junction to board) 13.67 °C/W JC Thermal resistance (junction to case) 4.54 °C/W AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms VREF = 0.75 V VREF 0.75 V VREF OUTPUT DEVICE UNDER TEST ZQ Z0 = 50  RL = 50  VREF = 0.75 V R = 50  ALL INPUT PULSES 1.25 V 0.75 V OUTPUT DEVICE UNDER TEST ZQ RQ = 250  (a) 0.75 V INCLUDING JIG AND SCOPE 5 pF [27] 0.25 V SLEW RATE= 2 V/ns RQ = 250  (b) Notes 25. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 26. Tested initially and after any design or process change that may affect these parameters. 27. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5. Document Number: 001-57825 Rev. *O Page 24 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Switching Characteristics Over the Operating Range Parameters [28, 29] Cypress Consortium Parameter Parameter 333 MHz Description VDD(typical) to the first access [30] tPOWER 300 MHz 250 MHz Unit Min Max Min Max Min Max 1 – 1 – 1 – ms tCYC tKHKH K clock and C clock cycle time 3.0 8.4 3.3 8.4 4.0 8.4 ns tKH tKHKL Input clock (K/K; C/C) HIGH 1.20 – 1.32 – 1.6 – ns tKL tKLKH Input clock (K/K; C/C) LOW 1.20 – 1.32 – 1.6 – ns tKHKH tKHKH K clock rise to K clock rise and C to C rise (rising edge to rising edge) 1.35 – 1.49 – 1.8 – ns tKHCH tKHCH K/K clock rise to C/C clock rise (rising edge to rising edge) 0 1.30 0 1.45 0 1.8 ns Setup Times tSA tAVKH Address set-up to K clock rise 0.3 – 0.3 – 0.35 – ns tSC tIVKH Control set-up to K clock rise (RPS, WPS) 0.3 – 0.3 – 0.35 – ns tSCDDR tIVKH DDR control set-up to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.3 – 0.3 – 0.35 – ns tSD tDVKH D[X:0] set-up to clock (K/K) rise 0.3 – 0.3 – 0.35 – ns tHA tKHAX Address hold after K clock rise 0.3 – 0.3 – 0.35 – ns tHC tKHIX Control hold after K clock rise (RPS, WPS) 0.3 – 0.3 – 0.35 – ns tHCDDR tKHIX DDR control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.3 – 0.3 – 0.35 – ns tHD tKHDX D[X:0] hold after clock (K/K) rise 0.3 – 0.3 – 0.35 – ns Hold Times Notes 28. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 24. 29. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 30. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially before initiating a read or write operation. Document Number: 001-57825 Rev. *O Page 25 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Switching Characteristics (continued) Over the Operating Range Parameters [28, 29] Cypress Consortium Parameter Parameter 333 MHz Description 300 MHz 250 MHz Unit Min Max Min Max Min Max – 0.45 – 0.45 – 0.45 ns Output Times tCO tCHQV C/C clock rise (or K/K in single clock mode) to data valid tDOH tCHQX Data output hold after output C/C clock rise (active to active) –0.45 – –0.45 – –0.45 – ns tCCQO tCHCQV C/C clock rise to echo clock valid – 0.45 – 0.45 – 0.45 ns tCQOH tCHCQX Echo clock hold after C/C clock rise –0.45 – –0.45 – –0.45 – ns tCQD tCQHQV Echo clock high to data valid 0.27 – 0.30 ns tCQDOH tCQHQX Echo clock high to data invalid –0.25 – –0.27 – –0.30 – ns tCQH tCQHCQL Output clock (CQ/CQ) HIGH [31] 1.25 – 1.40 – 1.75 – ns tCQHCQH tCQHCQH CQ clock rise to CQ clock rise (rising edge to rising edge) [31] 1.25 – 1.40 – 1.75 – ns tCHZ tCHQZ Clock (C/C) rise to high Z (active to high Z) [32, 33] – 0.45 – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (C/C) rise to low Z [32, 33] –0.45 – –0.45 – –0.45 – ns tKC Var Clock phase jitter – 0.20 – 0.20 – 0.20 ns 20 – 20 – 20 – s 30 – 30 – 30 – ns 0.25 PLL Timing tKC Var tKC lock tKC lock PLL lock time (K, C) tKC Reset tKC Reset K static to PLL reset [34] Notes 31. These parameters are extrapolated from the input timing parameters (tCYC/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 32. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 24. Transition is measured  100 mV from steady state voltage. 33. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 34. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version. Document Number: 001-57825 Rev. *O Page 26 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Switching Waveforms Figure 6. Read/Write/Deselect Sequence [35, 36, 37] READ WRITE READ WRITE READ WRITE NOP WRITE NOP 1 2 3 4 5 6 7 8 9 10 K tKH tKL tKHKH tCYC K RPS tSC t HC WPS A D A1 A2 tSA tHA tSA tHA D11 D30 A0 D10 A3 A4 A5 D31 D50 D51 tSD Q00 t CLZ C tKL tKH tKHCH D60 D61 tSD tHD tHD Q tKHCH A6 Q01 tDOH tCO Q20 Q21 Q41 Q40 tCQDOH t CHZ tCQD t CYC tKHKH C tCQOH tCCQO CQ tCQOH tCCQO tCQH tCQHCQH CQ DON’T CARE UNDEFINED Notes 35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 36. Outputs are disabled (high Z) one clock cycle after a NOP. 37. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-57825 Rev. *O Page 27 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 333 Ordering Code CY7C1412KV18-333BZC Package Diagram Package Type 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Operating Range Commercial CY7C1414KV18-333BZC CY7C1425KV18-333BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free CY7C1412KV18-333BZXI Industrial CY7C1414KV18-333BZXI 300 CY7C1414KV18-300BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) CY7C1425KV18-300BZXC Commercial 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free CY7C1412KV18-300BZXC CY7C1414KV18-300BZXC CY7C1414KV18-300BZXI 250 CY7C1425KV18-250BZC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Industrial Commercial CY7C1412KV18-250BZC CY7C1414KV18-250BZC CY7C1425KV18-250BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free CY7C1412KV18-250BZXC CY7C1414KV18-250BZXC CY7C1425KV18-250BZI 165-ball FBGA (13 × 15 × 1.4 mm) Industrial CY7C1412KV18-250BZI CY7C1414KV18-250BZI CY7C1425KV18-250BZXI 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free CY7C1412KV18-250BZXI CY7C1414KV18-250BZXI Ordering Code Definitions CY 7 C 14XX K V18 - XXX BZ X X Temperature Range: X = C or I C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C X = Pb-free; X Absent = Leaded Package Type: BZ = 165-ball FBGA Speed Grade: XXX = 333 MHz or 300 MHz or 250 MHz V18 = 1.8 V VDD Process Technology K = 65 nm Part Identifier: 14XX = 1412 or 1414 or 1425 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-57825 Rev. *O Page 28 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-57825 Rev. *O Page 29 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Acronyms Acronym Document Conventions Description Units of Measure DDR Double Data Rate FBGA Fine-Pitch Ball Grid Array °C degree Celsius HSTL High-Speed Transceiver Logic MHz megahertz I/O Input/Output µA microampere JTAG Joint Test Action Group µs microsecond LSB Least Significant Bit mA milliampere mm millimeter ms millisecond ns nanosecond MSB Most Significant Bit PLL Phase Locked Loop QDR Quad Data Rate SRAM Static Random Access Memory TAP Test Access Port TCK Test Clock TDI Test Data-In TDO Test Data-Out TMS Test Mode Select Document Number: 001-57825 Rev. *O Symbol Unit of Measure  ohm % percent pF picofarad V volt W watt Page 30 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Document History Page Document Title: CY7C1425KV18/CY7C1412KV18/CY7C1414KV18, 36-Mbit QDR® II SRAM Two-Word Burst Architecture Document Number: 001-57825 Rev. ECN No. Orig. of Change Submission Date ** 2816620 VKN / AESA 11/27/2009 New data sheet. *A 2884865 VKN 02/26/2010 Updated Switching Characteristics (Changed the minimum value of tSA and tSC parameters from 0.7 ns to 0.5 ns for 167 MHz, from 0.6 ns to 0.4 ns for 200 MHz, from 0.5 ns to 0.35 ns for 250 MHz, and from 0.4 ns to 0.3 ns for 333 MHz and 300 MHz). *B 3018546 NJY 10/21/2010 Changed status from Preliminary to Final. Added Ordering Code Definitions. Minor edits. Updated to new template. *C 3155124 VIDB 01/27/2011 Updated Switching Characteristics: Added Note 34 and referred the same note in description of tKC lock parameter. *D 3165654 NJY 02/08/2011 Updated Switching Characteristics: Updated Note 34. Updated Ordering Information (Updated part numbers). Added Acronyms and Units of Measure. *E 3436284 PRIT 11/11/2011 Updated Ordering Information (Updated part numbers). *F 3549927 PRIT 03/13/2012 Updated Features (Removed CY7C1410KV18 part related information). Updated Configurations (Removed CY7C1410KV18 part related information). Updated Functional Description (Removed CY7C1410KV18 part related information). Updated Selection Guide (Removed 167 MHz and 200 MHz frequencies related information). Removed Logic Block Diagram – CY7C1410KV18. Updated Pin Configurations (Removed CY7C1410KV18 part related information). Updated Pin Definitions (Removed CY7C1410KV18 part related information). Updated Functional Overview (Removed CY7C1410KV18 part related information). Updated Truth Table (Removed CY7C1410KV18 part related information). Updated Write Cycle Descriptions (Removed CY7C1410KV18 part related information). Updated Identification Register Definitions (Removed CY7C1410KV18 part related information). Updated Electrical Characteristics (Updated DC Electrical Characteristics (Removed 167 MHz and 200 MHz frequencies related information)). Updated Switching Characteristics (Removed 167 MHz and 200 MHz frequencies related information, updated Note 29). Updated Ordering Information (Updated part numbers). Updated Package Diagram. *G 3789642 PRIT 10/22/2012 Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)). *H 3860026 PRIT 01/10/2013 Updated Ordering Information (Updated part numbers). *I 3905088 PRIT 03/20/2013 Updated Ordering Information: Updated part numbers. *J 4373734 PRIT 05/08/2014 Updated Application Example: Updated Figure 2. Updated Thermal Resistance: Updated values of JA parameter. Included JB parameter and its details. Updated to new template. Document Number: 001-57825 Rev. *O Description of Change Page 31 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Document History Page (continued) Document Title: CY7C1425KV18/CY7C1412KV18/CY7C1414KV18, 36-Mbit QDR® II SRAM Two-Word Burst Architecture Document Number: 001-57825 Rev. ECN No. Orig. of Change Submission Date *K 4567876 PRIT 11/12/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Updated part numbers. Description of Change *L 4621838 PRIT 01/13/2015 Updated Ordering Information (Updated part numbers). *M 5060318 PRIT 12/22/2015 Updated Package Diagram: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. *N 5522985 PRIT 11/16/2016 Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. *O 6012085 AESATP12 01/03/2018 Updated logo and copyright. Document Number: 001-57825 Rev. *O Page 32 of 33 CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). 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Document Number: 001-57825 Rev. *O Revised January 3, 2018 Page 33 of 33