CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C
May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality. Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.
Devices Affected
Density & Revision 9Mb - Ram9(90 nm) 9Mb - Ram9(90 nm) 18Mb - Ram9(90nm) Part Numbers CY7C130*DV25 CY7C129*DV18 CY7C130*BV18 CY7C130*BV25 CY7C132*BV25 CY7C131*BV18 CY7C132*BV18 CY7C139*BV18 CY7C191*BV18 CY7C141*AV18 CY7C142*AV18 CY7C151*V18 CY7C152*V18 Architecture QDRI/DDRI QDRII QDRI/DDRI
18Mb - Ram9(90nm)
QDRII/DDRII
36Mb - Ram9(90nm) 72Mb -Ram9(90nm) Table 1. List of Affected devices
QDRII/DDRII QDRII/DDRII
Product Status
All of the above densities and revisions are available in sample as well as production quantities.
QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata Summary
The following table defines the issues and the fix status for the different devices which are affected.
Item Issue Device Fix Status
1.
DOFF pin is used for enabling/disabling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K Ω . The value of the external pullup resistor should be 500 Ω or less in order to ensure DLL is enabled.
9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-II/DDR-II Devices
The fix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available.
Cypress Semiconductor Corporation Document #: 001-06217 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600 Revised:- May 02, 2007
Item
Issue
Device
Fix Status
2.
O/P Buffer enters a locked up undefined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed. The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode.
9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-I/DDR-I/ QDR-II/DDR-II Devices 9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-I/DDR-I/ QDR-II/DDR-II Devices
The fix has been implemented on the new revision and is now available.
3.
The fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available.
Table 2. Issue Definition and fix status for different devices
1. DOFF Pin Issue
• ISSUE DEFINITION This issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K Ω ) as an external pullup resistor to enable the DLL. If a 10K Ω or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL. • PARAMETERS AFFECTED The functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. • TRIGGER CONDITION(S) Having a 10K Ω or higher external pullup resistor for disabling the DOFF pin. • SCOPE OF IMPACT This issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled. • EXPLANATION OF ISSUE Figure 1 shows the DOFF pin circuit with an internal 5K Ω internal resistor. The fix planned is to disable the internal 5K Ω leaker.
Figure 1. DOFF pin with the 5K Ω internal resistor
• WORKAROUND
Document #: 001-06217 Rev. *C Page 2 of 8
The workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is
