CY7C142-55PC

CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 110 mA (max.) • Fully asynchronous operation • Automatic power-down • Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 • BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146 • INT flag for port-to-port communication (52-pin PLCC/PQFP versions) • Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146) • Pb-Free packages available Functional Description The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP. Logic Block Diagram R/WL CEL OEL R/WR CER OER Pin Configuration DIP Top View CEL R/WL BUSYL A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 2 3 4 5 6 7 8 9 10 11 12 7C132 13 7C142 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CER R/WR BUSYR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O0L I/O CONTROL I/O CONTROL I/O7R I/O0R [1] BUSYL A 10L A 0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER BUSYR A 10R A 0R [1] CEL OEL R/WL INTL[2] ARBITRA TION LOGIC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY) CER OER R/WR INTR [2] Notes: 1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required. Cypress Semiconductor Corporation Document #: 38-06031 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 1, 2005 CY7C132/CY7C136 CY7C142/CY7C146 Pin Configurations PLCC Top View BUSY R INTR A10R BUSYL R/W L CEL VCC CER R/W R A0L OEL A 10L INT L A0L OEL A 10L PQFP Top View INT L BUSYL R/W L CEL VCC BUSY R INTR A10R CER R/W R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L NC GND OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R 7C136 7C146 1415 16 17 18 19 20 21 22 23 24 25 26 NC GND I/O0R I/O1R Selection Guide 7C132-25[3] 7C136-25 7C136-15[3] 7C142-25 7C146-15 7C146-25 Maximum Access Time Maximum Operating Current Com’l/Ind Maximum Operating Current Military Maximum Standby Current Com’l/Ind Military Shaded areas contain preliminary information. Note: 3. 15 and 25-ns version available in PQFP and PLCC packages only. 7C132-30 7C136-30 7C142-30 7C146-30 30 170 65 7C132-35 7C136-35 7C142-35 7C146-35 35 120 170 45 65 7C132-45 7C136-45 7C142-45 7C146-45 45 120 170 45 65 I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L 7C132-55 7C136-55 7C142-55 7C146-55 55 110 120 35 45 Unit ns mA mA mA 15 190 75 25 170 65 Document #: 38-06031 Rev. *C Page 2 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State .....................................................−0.5V to +7.0V DC Input Voltage ................................................. −3.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Military[4] Ambient Temperature 0°C to +70°C –40°C to +85–C –55°C to +125°C 7C132-35,45 7C136-35,45 7C142-35,45 7C146-35,45 2.4 0.4 0.5 2.2 0.8 0.8 −5 −5 +5 +5 −350 170 65 115 −5 −5 +5 +5 –350 190 75 135 2.2 0.8 +5 +5 −350 120 170 45 65 90 115 15 15 15 15 125 105 85 105 −5 −5 0.4 0.5 2.2 0.8 +5 +5 VCC 5V ± 10% 5V ± 10% 5V ± 10% 7C132-55 7C136-55 7C142-55 7C146-55 2.4 0.4 0.5 V V µA µA V V Electrical Characteristics Over the Operating Range[5] 7C132-30[3] 7C136-25,30 7C136-15[3] 7C142-30 7C146-15 7C146-25,30 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 ISB3 Description Test Conditions Output HIGH voltage VCC = Min., IOH = –4.0 mA Output LOW voltage IOL = 4.0 mA IOL = 16.0 mA[6] Input HIGH voltage Input LOW voltage Input load current Output leakage current Output short circuit current[7] VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND CE = VIL, Outputs Open, f = Com’l fMAX[8] Mil Com’l Mil Com’l Mil Com’l Mil –5 –5 2.2 2.4 0.4 0.5 2.4 Min. Max. Min. Max. Min. Max. Min. Max. Unit −350 mA 110 mA 120 35 45 75 90 15 15 70 85 mA mA mA mA Standby current both CEL and CER > VIH, ports, TTL Inputs f = fMAX[8] Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs Standby Current One Port, CMOS Inputs CEL or CER > VIH, Active Port Outputs Open, f = fMAX[8] Both Ports CEL and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 ISB4 One Port CEL or CER > VCC – Com’l 0.2V, VIN > VCC – 0.2V or VIN < Mil 0.2V, Active Port Outputs Open, f = fMAX[8] Description Capacitance[9] Parameter CIN COUT Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF Input Capacitance Output Capacitance Shaded areas contain preliminary information. Notes: 4. TA is the “instant on” case temperature. 5. See the last page of this specification for Group A subgroup testing information. 6. BUSY and INT pins only. 7. Duration of the short circuit should not exceed 30 seconds. 8. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 9. This parameter is guaranteed but not tested. Document #: 38-06031 Rev. *C Page 3 of 18 CY7C132/CY7C136 CY7C142/CY7C146 AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 347Ω R1 893Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 347Ω R1 893Ω BUSY OR INT 5V 281Ω 30 pF (a) THÉVENIN EQUIVALENT 250Ω 1.4V (b) 3.0V GND 10% BUSY Output Load (CY7C132/CY7C136 Only) ALL INPUT PULSES 90% 90% 10% < 5 ns OUTPUT < 5 ns Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [5, 10] 7C136-15[3] 7C146-15 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[14] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start R/W Pulse Width Data Set-up to Write End Data Hold from Write End R/W LOW to High Z [9] 0 R/W HIGH to Low Z [9] 15 12 12 2 0 12 10 0 10 0 25 20 20 2 0 15 15 0 15 0 30 25 25 2 0 25 15 0 15 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid[11] 0 15 10 3 10 3 10 0 15 0 25 5 15 0 25 3 15 5 15 Data Hold from Address Change CE LOW to Data Valid[11] OE LOW to Data Valid[11] OE LOW to Low Z[9, 12] OE HIGH to High CE LOW to Low Z[9, 12, 13] Z[9, 12] 15 15 0 25 15 3 15 25 25 0 30 20 30 30 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. Unit CE HIGH to High Z[9, 12, 13] CE LOW to Power-Up[9] CE HIGH to Power-Down[9] Shaded areas contain preliminary information. Notes: 10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 11. AC test conditions use VOH = 1.6V and VOL = 1.4V. 12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-06031 Rev. *C Page 4 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) (continued)[5, 10] 7C136-15[3] 7C146-15 Parameter Busy/Interrupt Timing tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD Interrupt tWINS tEINS tINS tOINR tEINR tINR BUSY LOW from Address Match BUSY HIGH from Address Mismatch[15] BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set Up for Priority R/W LOW after BUSY LOW BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Timing[18] R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[15] CE to INTERRUPT Reset Time[15] Time[15] Address to INTERRUPT Reset 15 15 15 15 15 15 [5, 10] [16] [15] 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 20 20 20 20 5 0 20 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. 20 20 20 20 5 0 30 Unit ns ns ns ns ns ns ns 30 Note 17 Note 17 25 25 25 25 25 25 ns ns ns ns ns ns ns ns ns Description Min. Max. 15 15 15 15 5 0 13 15 Note 17 Note 17 R/W HIGH after BUSY HIGH 25 Note 17 Note 17 25 25 25 25 25 25 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) 7C132-35 7C136-35 7C142-35 7C146-35 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid[11] Data Hold from Address Change CE LOW to Data Valid[11] [9, 12] 7C132-45 7C136-45 7C142-45 7C146-45 Min. 45 Max. 7C132-55 7C136-55 7C142-55 7C146-55 Min. 55 Max. Unit ns 55 0 55 25 3 25 5 25 0 35 ns ns ns ns ns ns ns ns ns ns Description Min. 35 Max. 35 0 35 20 3 20 5 20 0 35 0 5 3 0 45 45 25 20 20 35 OE LOW to Data Valid[11] OE LOW to Low Z OE HIGH to High Z[9, 12, 13] CE LOW to Low Z[9, 12] CE HIGH to High Z CE HIGH to [9, 12, 13] CE LOW to Power-Up[9] Power-Down[9] Notes: 15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 16. CY7C142/CY7C146 only. 17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 18. 52-pin PLCC and PQFP versions only. Document #: 38-06031 Rev. *C Page 5 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) (continued)[5, 10] 7C132-35 7C136-35 7C142-35 7C146-35 Parameter Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD tWINS tEINS tINS tOINR tEINR tINR [14] 7C132-45 7C136-45 7C142-45 7C146-45 Min. 45 35 35 2 0 30 20 0 Max. 7C132-55 7C136-55 7C142-55 7C146-55 Min. 55 40 40 2 0 30 20 0 Max. Unit ns ns ns ns ns ns ns ns 25 0 ns ns 30 30 30 30 5 0 35 ns ns ns ns ns ns ns 45 Note 17 Note 17 45 45 45 45 45 45 ns ns ns ns ns ns ns ns ns Description Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start R/W Pulse Width Data Set-up to Write End Data Hold from Write End R/W LOW to High Z [9] R/W HIGH to Low Z [9] BUSY LOW from Address Match BUSY HIGH from Address Mismatch[15] BUSY LOW from CE LOW BUSY HIGH from CE HIGH[15] Port Set Up for Priority R/W LOW after BUSY LOW[16] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay [18] Min. 35 30 30 2 0 25 15 0 Max. 20 0 20 20 20 20 5 0 30 35 Note 17 Note 17 25 25 25 25 25 25 5 0 35 0 20 Busy/Interrupt Timing 25 25 25 25 45 Note 17 Note 17 35 35 35 35 35 35 Interrupt Timing R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[15] CE to INTERRUPT Reset Time Address to INTERRUPT Reset [15] Time[15] Document #: 38-06031 Rev. *C Page 6 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms Read Cycle No. 1 (Either Port-Address Access)[19, 20] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (Either Port-CE/OE)[19, 21] CE OE tLZOE tLZCE DATA OUT tPU ICC ISB DATA VALID tPD tACE tDOE tHZOE tHZCE Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136) tRC ADDRESSR R/WR DINR tPS ADDRESSL BUSYL tBLA DOUTL tWDD Notes: 19. R/W is HIGH for read cycle. 20. Device is continuously selected, CE = VIL and OE = VIL. 21. Address valid prior to or coincident with CE transition LOW. ADDRESS MATCH tPWE VALID ADDRESS MATCH tBHA tBDD VALID tDDD Document #: 38-06031 Rev. *C Page 7 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[14, 22] tWC ADDRESS tSCE CE tSA R/W tSD DATAIN OE tHZOE DOUT HIGH IMPEDANCE DATA VALID tHD tAW tPWE tHA Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[14, 23] tWC ADDRESS tSCE CE tSA R/W tSD DATAIN tHZWE DOUT tHD tAW tPWE tHA DATA VALID tLZWE HIGH IMPEDANCE Notes: 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state. Document #: 38-06031 Rev. *C Page 8 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESSL,R CEL tPS ADDRESS MATCH CER tBLC BUSYR tBHC CER Valid First: ADDRESSL,R CER tPS ADDRESS MATCH CEL tBLC BUSYL tBHC Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH tPS ADDRESSR tBLA BUSYR tBHA ADDRESS MISMATCH Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSYL tBHA ADDRESS MISMATCH Document #: 38-06031 Rev. *C Page 9 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) CE tPWE R/W tWB BUSY tWH Interrupt Timing Diagrams[18] Left Side Sets INTR: tWC ADDRESSL CEL R/WL tSA INTR tINS tEINS WRITE 7FF tHA tWINS Right Side Clears INTR: tRC ADDRESSR CER tEINR R/WR OER INTR tHA READ 7FF tINR tOINR Right Side Sets INTL: tWC ADDRESSR CER R/WR INTL tSA tINS tEINS WRITE 7FE tHA tWINS Document #: 38-06031 Rev. *C Page 10 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Interrupt Timing Diagrams[18] (continued) Right Side Clears INTL: tRC ADDRESSL CEL tEINR R/WL OEL tOINR INTL tHA READ 7FE tINR Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB3 5.5 6.0 NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZED ICC, ISB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 1.0 0.8 0.6 0.4 0.2 0.6 –55 25 VCC = 5.0V VIN = 5.0V ISB3 125 ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25°C ICC SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25°C AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 –55 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE OUTPUT SINK CURRENT (mA) 140 120 100 80 60 40 20 25 125 0 0.0 VCC = 5.0V TA = 25°C 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED tPC 2.5 2.0 1.5 1.0 0.5 0.0 0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 DELTA tAA (ns) 20.0 15.0 10.0 5.0 0 0 AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING OUTPUT VOLTAGE (V) NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25°C VIN = 0.5V 1.0 1.25 NORMALIZED ICC 0.75 VCC = 4.5V TA = 25°C 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CYCLE FREQUENCY (MHz) Document #: 38-06031 Rev. *C Page 11 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Ordering Information Speed (ns) 30 35 Ordering Code CY7C132-30PC CY7C132-30PI CY7C132-35PC CY7C132-35PI CY7C132-35DMB 45 CY7C132-45PC CY7C132-45PI CY7C132-45DMB 55 CY7C132-55PC CY7C132-55PI CY7C132-55DMB 15 25 CY7C136-15JC CY7C136-15NC CY7C136-25JC CY7C136-25JXC CY7C136-25NC CY7C136-25NXC 30 CY7C136-30JC CY7C136-30NC CY7C136-30JI 35 CY7C136-35JC CY7C136-35NC CY7C136-35JI CY7C136-35LMB 45 CY7C136-45JC CY7C136-45NC CY7C136-45JI CY7C136-45LMB 55 CY7C136-55JC CY7C136-55JXC CY7C136-55NC CY7C136-55NXC CY7C136-55JI CY7C136-55JXI CY7C136-55NI CY7C136-55NXI CY7C136-55LMB 30 35 CY7C142-30PC CY7C142-30PI CY7C142-35PC CY7C142-35PI CY7C142-35DMB Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 J69 N52 J69 J69 N52 N52 J69 N52 J69 J69 N52 J69 L69 J69 N52 J69 L69 J69 J69 N52 N52 J69 J69 N52 N52 L69 P25 P25 P25 P25 D26 Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Pb-Free Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Pb-Free Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Pin Pb-Free Plastic Quad Flatpack 52-Square Leadless Chip Carrier 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP Military Commercial Industrial Commercial Industrial Military Industrial Industrial Military Commercial Industrial Military Commercial Industrial Commercial Commercial Commercial Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Commercial Document #: 38-06031 Rev. *C Page 12 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Ordering Information (continued) Speed (ns) 45 Ordering Code CY7C142-45PC CY7C142-45PI CY7C142-45DMB 55 CY7C142-55PC CY7C142-55PI CY7C142-55DMB 15 25 CY7C146-15JC CY7C146-15NC CY7C146-25JC CY7C146-25JXC CY7C146-25NC 30 CY7C146-30JC CY7C146-30NC CY7C146-30JI 35 CY7C146-35JC CY7C146-35NC CY7C146-35JI CY7C146-35LMB 45 CY7C146-45JC CY7C146-45NC CY7C146-45JI CY7C146-45LMB 55 CY7C146-55JC CY7C146-55JXC CY7C146-55NC CY7C146-55JI CY7C146-55LMB Package Name P25 P25 D26 P25 P25 D26 J69 N52 J69 J69 N52 J69 N52 J69 J69 N52 J69 L69 J69 N52 J69 L69 J69 J69 N52 J69 L69 Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier Industrial Military Industrial Military Commercial Industrial Military Commercial Industrial Commercial Commercial Commercial Operating Range Commercial Industrial Military Commercial Industrial Military Commercial Document #: 38-06031 Rev. *C Page 13 of 18 CY7C132/CY7C136 CY7C142/CY7C146 MILITARY SPECIFICATIONS Group A Subgroup Testing—DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter Read Cycle tRC tAA tACE tDOE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD Busy/Interrupt Timing tBLA tBHA tBLC tBHC tPS tWINS tEINS tINS tOINR tEINR tINR BUSY TIMING tWB[24] tWH tBDD Note: 24. CY7C142/CY7C146 only. Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Document #: 38-06031 Rev. *C Page 14 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C 51-80044-** 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Pb-Free Plastic Leaded Chip Carrier J69 51-85004-*A Document #: 38-06031 Rev. *C Page 15 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams (continued) 52-Square Leadless Chip Carrier L69 51-80054-** 52-Lead Plastic Quad Flatpack N52 52-Lead Pb-Free Plastic Quad Flatpack N52 51-85042-** Document #: 38-06031 Rev. *C Page 16 of 18 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams (continued) 48-Lead (600-Mil) Molded DIP P25 51-85020-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06031 Rev. *C Page 17 of 18 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C132/CY7C136 CY7C142/CY7C146 Document History Page Document Title: CY7C132/CY7C136/CY7C142/CY7C146 2K x 8 Dual Port Static RAM Document Number: 38-06031 REV. ** *A *B *C ECN NO. 110171 128959 236748 393184 Orig. of Issue Date Change 10/21/01 09/03/03 See ECN See ECN SZV JFU YDT YIM Description of Change Change from Spec number: 38-06031 Added CY7C136-55NI to Order Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC, CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC Document #: 38-06031 Rev. *C Page 18 of 18