CY7C1427BV18-300BZXC

PRELIMINARY CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz for DDR-II • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • DDR-II operates with 1.5 cycle read latency when DLL is enabled • Operates like a DDR I device with 1 cycle read latency in DLL off mode • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (15 x 17 x 1.4 mm) • Offered in both in lead-free and non lead-free packages • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18 and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1416BV18 and two 9-bit words in the case of CY7C1427BV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1416BV18 and CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418BV18 and two 36-bit words in the case of CY7C1420BV18 sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1416BV18 – 4M x 8 CY7C1427BV18 – 4M x 9 CY7C1418BV18 – 2M x 18 CY7C1420BV18 – 1M x 36 Selection Guide 300 MHz Maximum Operating Frequency Maximum Operating Current (DDR-II) 300 825 278 MHz 278 775 250 MHz 250 700 200 MHz 200 600 167 MHz 167 500 Unit MHz mA Cypress Semiconductor Corporation Document Number: 001-07033 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 20, 2006 [+] [+] Feedback PRELIMINARY Logic Block Diagram (CY7C1416BV18) CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 A(20:0) 21 LD Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 8 Array Write Reg 2M x 8 Array 8 Output Logic Control K K DOFF CLK Gen. R/W C C CQ Read Data Reg. 16 Control Logic 8 Reg. 8 Reg. 8 Reg. VREF R/W NWS[1:0] 8 CQ DQ[7:0] Logic Block Diagram (CY7C1427BV18) A(20:0) 21 LD Write Add. Decode Read Add. Decode Address Register Write Reg 2M x 9 Array Write Reg 2M x 9 Array 9 Output Logic Control K K DOFF CLK Gen. R/W C C CQ Read Data Reg. 18 Control Logic 9 Reg. 9 Reg. 9 Reg. VREF R/W BWS[0] 9 CQ DQ[8:0] Document Number: 001-07033 Rev. *B Page 2 of 28 [+] [+] Feedback PRELIMINARY Logic Block Diagram (CY7C1418BV18) A0 21 A(20:0) LD 20 CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Burst Logic Write Add. Decode Read Add. Decode Address A(20:1) Register Write Reg Write Reg 18 Output Logic Control 2M x 18 Array K K DOFF CLK Gen. R/W C C CQ Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 18 Reg. VREF R/W BWS[1:0] CQ 18 DQ[17:0] Logic Block Diagram (CY7C1420BV18) Burst Logic 19 A0 20 A(19:0) LD Write Add. Decode Read Add. Decode Address A(19:1) Register Write Reg Write Reg 36 1M x 36 Array K K DOFF CLK Gen. Output Logic Control R/W C C CQ 36 Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 36 Reg. VREF R/W BWS[3:0] CQ 36 DQ[35:0] Document Number: 001-07033 Rev. *B Page 3 of 28 [+] [+] Feedback PRELIMINARY Pin Configurations 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1416BV18 (4M x 8) CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI CY7C1427BV18 (4M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI Document Number: 001-07033 Rev. *B Page 4 of 28 [+] [+] Feedback PRELIMINARY Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1418BV18 (2M x 18) CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI CY7C1420BV18 (1M x 36) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 A DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI Document Number: 001-07033 Rev. *B Page 5 of 28 [+] [+] Feedback PRELIMINARY Pin Definitions Pin Name DQ[x:0] I/O Pin Description CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically tri-stated. CY7C1416BV18 − DQ[7:0] CY7C1427BV18 − DQ[8:0] CY7C1418BV18 − DQ[17:0] CY7C1420BV18 − DQ[35:0] InputSynchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of 2 data. LD must meet the set-up and hold times around edge of K. InputNibble Write Select 0, 1 − active LOW (CY7C1416BV18 only). Sampled on the rising edge of Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. LD NWS0, NWS1 BWS0, BWS1, InputByte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and K clocks BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1427BV18 − BWS0 controls D[8:0] CY7C1418BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1420BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A, A0 InputAddress Inputs. These address inputs are multiplexed for both Read and Write operations. Synchronous Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1416BV18 and 4M x 9 (2 arrays each of 2M x 9) for CY7C1420BV18, a single 2M x 18 array for CY7C1427BV18, and a single array of 1M x 36 for CY7C1418BV18. CY7C1416BV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array. CY7C1420BV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array. CY7C1427BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. CY7C1418BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected. InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (Read Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K. InputClock InputClock InputClock InputClock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode. R/W C C K K Document Number: 001-07033 Rev. *B Page 6 of 28 [+] [+] Feedback PRELIMINARY Pin Definitions (continued) Pin Name CQ I/O OutputClock OutputClock Input Pin Description CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. For normal operation, this pin should be pulled HIGH through 10-Kohm or less pull-up resistor. More details on this operation can be found in the application note, “DLL Considerations in QDRII™/DDRII”. The device will behave in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167MHz with DDR-I timing. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Ground for the device. CQ ZQ DOFF Input TDO TCK TDI TMS NC NC/72M NC/144M NC/288M VREF VDD VSS VDDQ Output Input Input Input N/A N/A N/A N/A InputReference Ground Power Supply Power supply inputs to the core of the device. Power Supply Power supply inputs for the outputs of the device. CY7C1427BV18 is described in the following sections. The same basic descriptions apply to CY7C1416BV18, CY7C1420BV18, and CY7C1418BV18. Read Operations for DDR-II The CY7C1427BV18 is organized internally as a single array of 2M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C, or K and K when in single clock mode, 200-MHz and 250-MHz device). In order to maintain the internal logic, each read access must be allowed Functional Overview The CY7C1416BV18, CY7C1420BV18, CY7C1427BV18, and CY7C1418BV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behave in DDR-I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C or K/K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C or K/K when in single-clock mode). All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K). Document Number: 001-07033 Rev. *B Page 7 of 28 [+] [+] Feedback PRELIMINARY to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When Read access is deselected, the CY7C1427BV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When Write access is deselected, the device will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1427BV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1427BV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. DDR Operation The CY7C1427BV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1427BV18 CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 requires a single No Operation (NOP) cycle when transitioning from a Read to a Write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention. If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The Write information must be stored because the SRAM cannot perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write. If a Read is performed on the same address on which a Write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device will behave in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note “DLL Considerations in QDRII™/DDRII”. Document Number: 001-07033 Rev. *B Page 8 of 28 [+] Feedback PRELIMINARY Application Example[1] ZQ CQ/CQ# LD# R/W# C C# K K# CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 DQ A SRAM#1 R = 250ohms DQ A ZQ CQ/CQ# LD# R/W# C C# K K# SRAM#2 R = 250ohms DQ Addresses Cycle Start# R/W# Return CLK Source CLK Return CLK# Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 BUS MASTER (CPU or ASIC) Vterm = 0.75V R = 50ohms Vterm = 0.75V Truth Table for DDR-II [2, 3, 4, 5, 6, 7] Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L DQ D(A) at K(t + 1) ↑ DQ D(A + 1) at K(t + 1) ↑ L-H L H Q(A) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑ L-H Stopped H X X X High-Z Previous State High-Z Previous State Burst Address Table (CY7C1427BV18, CY7C1418BV18) First Address (External) X..X0 X..X1 Second Address (Internal) X..X1 X..X0 Notes: 1. The above application shows two DDR-II used. 2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. On CY7C1418BV18 and CY7C1420BV18, “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst. On CY7C1416BV18 and CY7C1427BV18 “A” represents A + ‘0’ and A2 represents A + ‘1’. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document Number: 001-07033 Rev. *B Page 9 of 28 [+] [+] Feedback PRELIMINARY Write Cycle Descriptions (CY7C1416BV18 and CY7C1427BV18)[2, 8] BWS0,NWS0 L BWS1,NWS1 L K L-H K – Comments CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 During the Data portion of a Write sequence: CY7C1416BV18 − both nibbles (D[7:0]) are written into the device, CY7C1427BV18 − both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence: CY7C1416BV18 − both nibbles (D[7:0]) are written into the device, CY7C1427BV18 − both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence: CY7C1416BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1427BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence: CY7C1416BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1427BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence: CY7C1416BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1427BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. During the Data portion of a Write sequence: CY7C1416BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1427BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. No data is written into the devices during this portion of a Write operation. No data is written into the devices during this portion of a Write operation. L L – L-H L H L-H – L H – L-H H L L-H – H L – L-H H H H H L-H – – L-H Write Cycle Descriptions (CY7C1420BV18) [2, 8] BWS0 L L H H K L-H – L-H – K – L-H – L-H Comments During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation. Note: 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document Number: 001-07033 Rev. *B Page 10 of 28 [+] [+] Feedback PRELIMINARY Write Cycle Descriptions (CY7C1418BV18) BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H – L-H – L-H – L-H – L-H – L-H – L-H – L-H K – L-H – L-H – L-H – L-H [2, 8] CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation. Document Number: 001-07033 Rev. *B Page 11 of 28 [+] Feedback PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document Number: 001-07033 Rev. *B CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 12 of 28 [+] [+] Feedback PRELIMINARY is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-07033 Rev. *B Page 13 of 28 [+] Feedback PRELIMINARY TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07033 Rev. *B Page 14 of 28 [+] [+] Feedback PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 Instruction Register 31 30 29 . . 2 1 0 1 0 CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Selection Circuitry TDO Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[10, 14, 16] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and OutputLoad Current GND ≤ VI ≤ VDD Test Conditions IOH = −2.0 mA IOH = −100 µA IOL = 2.0 mA IOL = 100 µA 0.65VDD –0.3 −5 Min. 1.4 1.6 0.4 0.2 VDD + 0.3 0.35VDD 5 Max. Unit V V V V V V µA TAP AC Switching Characteristics Over the Operating Range[11, 12] Parameter tTCYC tTF tTH tTL TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min. 50 20 Max. Unit ns MHz ns ns Notes: 10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 001-07033 Rev. *B Page 15 of 28 [+] [+] Feedback PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[11, 12] (continued) Parameter Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH tTDOV tTDOX TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 5 5 5 TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 5 5 5 Description CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Min. Max. Unit ns ns ns ns ns ns 10 0 ns ns Output Times TAP Timing and Test Conditions[12] 0.9V 50Ω TDO Z0 = 50Ω CL = 20 pF 0V ALL INPUT PULSES 1.8V 0.9V (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV tTDOX Document Number: 001-07033 Rev. *B Page 16 of 28 [+] [+] Feedback PRELIMINARY Identification Register Definitions Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) Value CY7C1416BV18 001 11010100010000111 00000110100 CY7C1420BV18 001 11010100010001111 00000110100 CY7C1427BV18 001 CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 CY7C1418BV18 001 Description Version number. 11010100010010111 11010100010100111 Defines the type of SRAM. 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicate the presence of an ID register. 1 1 1 1 Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 109 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Description Document Number: 001-07033 Rev. *B Page 17 of 28 [+] [+] Feedback PRELIMINARY Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Document Number: 001-07033 Rev. *B Page 18 of 28 [+] [+] Feedback PRELIMINARY Power-Up Sequence in DDR-II SRAM[13] DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power-Up Sequence • Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) — Apply VDD before VDDQ — Apply VDDQ before VREF or at the same time as VREF • Provide stable power and clock (K, K) for 1024 cycles to lock the DLL. DLL Constraints CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 • DLL uses K clock as its synchronizing input. The input should have low phase jitter, which is specified as tKC Var. • The DLL will function at frequencies down to 80 MHz. • If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency. Power-Up Waveforms ~ ~ K K ~ ~ Unstable Clock > 1024 Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ) Note: 13. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. Document Number: 001-07033 Rev. *B Page 19 of 28 [+] [+] Feedback PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .... –10°C to +85°C Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.3V DC Input Voltage[14] ...............................–0.5V to VDD + 0.3V CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch-up Current..................................................... >200 mA Operating Range Range Com’l Ind’l Ambient Temperature 0°C to +70°C –40°C to +85°C VDD[15] 1.8 ± 0.1V VDDQ[15] 1.4V to VDD Electrical Characteristics Over the Operating Range[16] DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Input Reference Voltage[19] VDD Operating Supply GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 200 MHz 250 MHz 278 MHz 300 MHz ISB1 Automatic Power-down Current Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH or 200 MHz VIN ≤ VIL f = fMAX = 250 MHz 1/tCYC, Inputs Static 278 MHz 300 MHz AC Input Requirements Over the Operating Range Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min. VREF + 0.2 – Typ. – – Max. – VREF – 0.2 Unit V V Note 17 Note 18 IOH = –0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 1.7 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 –5 –5 0.68 0.75 Typ. 1.8 1.5 Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 5 5 0.95 500 600 700 775 825 220 230 250 260 270 Unit V V V V V V V V µA µA V mA mA mA mA mA mA mA mA mA mA Notes: 14. Overshoot: VIH(AC) < VDD+0.85V (Pulse width less than tTCYC/2); Undershoot VIL(AC) > –1.5V (Pulse width less than tTCYC/2). 15. Power-up: Assumes a linear ramp from 0V to VDD(Min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. All voltage referenced to ground. 17. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω. 18. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω. 19. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. Document Number: 001-07033 Rev. *B Page 20 of 28 [+] [+] Feedback PRELIMINARY Capacitance[20] Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Max. 5 4 5 Unit pF pF pF Thermal Resistance[20] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 165 FBGA Package 17.2 3.2 Unit °C/W °C/W AC Test Loads and Waveforms VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50Ω RL = 50Ω VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50Ω ALL INPUT PULSES 1.25V 0.75V [21] ZQ RQ = 250Ω (a) RQ = 250Ω (b) INCLUDING JIG AND SCOPE Notes: 20. Tested initially and after any design or process change that may affect these parameters. 21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads. Document Number: 001-07033 Rev. *B Page 21 of 28 [+] [+] Feedback PRELIMINARY Switching Characteristics Over the Operating Range [21, 22] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH 300 MHz Description VDD(Typical) to the first Access[23] K Clock and C Clock Cycle Time Input Clock (K/K and C/C) HIGH Input Clock (K/K and C/C) LOW K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) Address Set-up to K Clock Rise Control Set-up to K Clock Rise (LD, R/W) Double Data Rate Control Set-up to Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Set-up to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise (LD, R/W) Double Data Rate Control Hold after Clock (K and K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K and K) Rise C/C Clock Rise (or K/K in single clock mode) to Data Valid Data Output Hold after Output C/C Clock Rise (Active to Active) C/C Clock Rise to Echo Clock Valid 1 3.30 1.32 1.32 1.49 – 5.25 – – – 278 MHz 1 3.6 1.4 1.4 1.6 – 5.25 – – – 250 MHz 1 4.0 1.6 1.6 1.8 6.3 – – – CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 200 MHz 1 5.0 2.0 2.0 2.2 7.9 – – – 167 MHz Unit ms 8.4 – – – ns ns ns ns 1 6.0 2.4 2.4 2.7 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tKHCH tKHCH 0 1.45 0 1.55 0 1.8 0 2.2 0 2.7 ns Set-up Times tSA tSC tSCDDR tAVKH tIVKH tIVKH 0.4 0.4 0.3 – – – 0.4 0.4 0.3 – – – 0.5 0.5 0.35 – – – 0.6 0.6 0.4 – – – 0.7 0.7 0.5 – – – ns ns ns tSD[24] Hold Times tHA tHC tHCDDR tDVKH 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns tKHAX tKHIX tKHIX 0.4 0.4 0.3 – – – 0.4 0.4 0.3 – – – 0.5 0.5 0.35 – – – 0.6 0.6 0.4 – – – 0.7 0.7 0.5 – – – ns ns ns tHD tKHDX 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns Output Times tCO tCHQV – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns tDOH tCHQX –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns tCCQO tCHCQV – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns Notes: 22. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 23. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 24. For DQ2 data signal on CY7C1427BV18 device, tSD is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies. Document Number: 001-07033 Rev. *B Page 22 of 28 [+] [+] Feedback PRELIMINARY Switching Characteristics Over the Operating Range (continued)[21, 22] Cypress Consortium Parameter Parameter tCQOH tCQD tCQDOH tCQH tCQHCQH tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH 300 MHz Description Echo Clock Hold after C/C Clock Rise Echo Clock High to Data Valid –0.45 – – 0.27 – – – 278 MHz –0.45 – –0.27 1.35 1.35 – 0.27 – – – 250 MHz –0.45 – –0.30 1.55 1.55 – 0.30 – – – CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 200 MHz –0.45 – –0.35 1.95 1.95 – 0.35 – – – 167 MHz Unit ns ns ns ns ns –0.50 – –0.40 2.45 2.45 – 0.40 – – – Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Echo Clock High to Data –0.27 Invalid Output Clock (CQ/CQ) HIGH[25] CQ Clock Rise to CQ Clock Rise[25] (rising edge to rising edge) Clock (C/C) Rise to High-Z (Active to High-Z)[26, 27] Clock (C/C) Rise to Low-Z[26, 27] Clock Phase Jitter DLL Lock Time (K, C) K Static to DLL Reset 1.24 1.24 tCHZ tCLZ DLL Timing tKC Var tKC lock tKC Reset tCHQZ tCHQX1 – –0.45 0.45 – – –0.45 0.45 – – –0.45 0.45 – – –0.45 0.45 – – –0.50 0.50 – ns ns tKC Var tKC lock tKC Reset – 1024 30 0.20 – – – 1024 30 0.20 – – – 1024 30 0.20 – – 1024 30 0.20 – – 1024 30 0.20 – ns Cycles ns Notes: 25. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) ia already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production. 26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. Document Number: 001-07033 Rev. *B Page 23 of 28 [+] [+] Feedback PRELIMINARY Switching Waveforms[28, 29, 30] Read/Write/Deselect Sequence NOP 1 K tKH K LD tSC tHC R/W A tSA A0 tHA A1 A2 tHD tSD DQ t KHCH t CLZ tCO C t KHCH C# tCQOH CQ tCQOH CQ# tCCQO tCQH tCCQO tKH tKL tCYC Q00 Q01 Q10 Q11 D20 D21 tSD D30 A3 A4 tHD tKL tCYC tKHKH CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 READ 2 READ 3 NOP 4 NOP 5 WRITE 6 WRITE 7 READ 8 9 10 D31 Q40 Q41 t CQDOH tDOH t CQD t CHZ tKHKH tCQHCQH DON’T CARE UNDEFINED Notes: 28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 29. Outputs are disabled (High-Z) one clock cycle after a NOP. 30. In this example, if address A2 = A1,then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-07033 Rev. *B Page 24 of 28 [+] [+] Feedback PRELIMINARY Ordering Information CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 300 Ordering Code CY7C1416BV18-300BZC CY7C1427BV18-300BZC CY7C1418BV18-300BZC CY7C1420BV18-300BZC 300 CY7C1416BV18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial CY7C1427BV18-300BZXC CY7C1418BV18-300BZXC CY7C1420BV18-300BZXC 300 CY7C1416BV18-300BZI CY7C1427BV18-300BZI CY7C1418BV18-300BZI CY7C1420BV18-300BZI 300 CY7C1416BV18-300BZXI CY7C1427BV18-300BZXI CY7C1418BV18-300BZXI CY7C1420BV18-300BZXI 278 CY7C1416BV18-278BZC CY7C1427BV18-278BZC CY7C1418BV18-278BZC CY7C1420BV18-278BZC 278 CY7C1416BV18-278BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial CY7C1427BV18-278BZXC CY7C1418BV18-278BZXC CY7C1420BV18-278BZXC 278 CY7C1416BV18-278BZI CY7C1427BV18-278BZI CY7C1418BV18-278BZI CY7C1420BV18-278BZI 278 CY7C1416BV18-278BZXI CY7C1427BV18-278BZXI CY7C1418BV18-278BZXI CY7C1420BV18-278BZXI 250 CY7C1416BV18-250BZC CY7C1427BV18-250BZC CY7C1418BV18-250BZC CY7C1420BV18-250BZC 250 CY7C1416BV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial CY7C1427BV18-250BZXC CY7C1418BV18-250BZXC CY7C1420BV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial Package Diagram Package Type Operating Range Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Document Number: 001-07033 Rev. *B Page 25 of 28 [+] [+] Feedback PRELIMINARY Ordering Information (continued) CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 250 Ordering Code CY7C1416BV18-250BZI CY7C1427BV18-250BZI CY7C1418BV18-250BZI CY7C1420BV18-250BZI 250 CY7C1416BV18-250BZXI CY7C1427BV18-250BZXI CY7C1418BV18-250BZXI CY7C1420BV18-250BZXI 200 CY7C1416BV18-200BZC CY7C1427BV18-200BZC CY7C1418BV18-200BZC CY7C1420BV18-200BZC 200 CY7C1416BV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial CY7C1427BV18-200BZXC CY7C1418BV18-200BZXC CY7C1420BV18-200BZXC 200 CY7C1416BV18-200BZI CY7C1427BV18-200BZI CY7C1418BV18-200BZI CY7C1420BV18-200BZI 200 CY7C1416BV18-200BZXI CY7C1427BV18-200BZXI CY7C1418BV18-200BZXI CY7C1420BV18-200BZXI 167 CY7C1416BV18-167BZC CY7C1427BV18-167BZC CY7C1418BV18-167BZC CY7C1420BV18-167BZC 167 CY7C1416BV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial CY7C1427BV18-167BZXC CY7C1418BV18-167BZXC CY7C1420BV18-167BZXC 167 CY7C1416BV18-167BZI CY7C1427BV18-167BZI CY7C1418BV18-167BZI CY7C1420BV18-167BZI 167 CY7C1416BV18-167BZXI CY7C1427BV18-167BZXI CY7C1418BV18-167BZXI CY7C1420BV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial Package Diagram Package Type Operating Range Industrial 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Document Number: 001-07033 Rev. *B Page 26 of 28 [+] [+] Feedback PRELIMINARY Package Diagram 165-ball FBGA (15 x 17 x 1.40 mm) (51-85195) CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 51-85195-*A QDR™ SRAMs and Quad Data Rate™ SRAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. Document Number: 001-07033 Rev. *B Page 27 of 28 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback PRELIMINARY Document History Page CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 Document Title: CY7C1416BV18/CY7C1427BV18/CY7C1418BV18/CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number: 001-07033 REV. ** *A ECN No. 433267 462004 Issue Date See ECN See ECN Orig. of Change NXR NXR New Data Sheet Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Minor change: Moved data sheet to web Description of Change *B 503690 See ECN VKN Document Number: 001-07033 Rev. *B Page 28 of 28 [+] [+] Feedback