THIS SPEC IS OBSOLETE
Spec No: 38-05383
Spec Title: CY7C1440AV33, 36-MBIT (1M X 36) PIPELINED SYNC SRAM
Replaced by:
None
CY7C1440AV33
36-Mbit (1M × 36) Pipelined Sync SRAM
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250 and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V/3.3 V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1440AV33 available in Pb-free 100-pin TQFP package,
Pb-free 165-ball FBGA package.
■
IEEE 1149.1 JTAG-compatible boundary scan
■
“ZZ” sleep mode option
The CY7C1440AV33 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
250 MHz
167 MHz
Unit
2.6
3.4
ns
Maximum operating current
475
375
mA
Maximum CMOS standby current
120
120
mA
Cypress Semiconductor Corporation
Document Number: 38-05383 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 2, 2016
CY7C1440AV33
Logic Block Diagram – CY7C1440AV33
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
GW
CE1
CE2
CE3
OE
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 38-05383 Rev. *N
Page 2 of 33
CY7C1440AV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
Document Number: 38-05383 Rev. *N
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Page 3 of 33
CY7C1440AV33
Pin Configurations
CY7C1440AV33
(1M × 36)
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
Document Number: 38-05383 Rev. *N
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 33
CY7C1440AV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1440AV33 (1M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
NC/576M
VDDQ
VDDQ
VSS
VDD
VSS
VDDQ
VSS
VSS
VSS
OE
VSS
VDD
A
NC
DQC
GW
VSS
VSS
ADSP
DQPC
DQC
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
Document Number: 38-05383 Rev. *N
A0
Page 5 of 33
CY7C1440AV33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK
synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[1]are sampled active. A1:A0 are fed to the
two-bit counter.
BWA, BWB,
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD synchronous on the rising edge of CLK.
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
GW
synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Inputclock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA.
Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when
a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
DQs,
DQPX
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.
VDD
Power supply Power supply inputs to the core of the device.
VSS
VSSQ
Ground
I/O ground
Ground for the core of the device.
Ground for the I/O circuitry.
Note
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05383 Rev. *N
Page 6 of 33
CY7C1440AV33
Pin Definitions (continued)
Name
I/O
VDDQ
I/O power
supply
MODE
Inputstatic
Description
Power supply for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
output
synchronous
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
synchronous
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
input
synchronous
TCK
JTAGclock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G
are address expansion pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
The CY7C1440AV33 supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed Write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Document Number: 38-05383 Rev. *N
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within 2.6 ns (250-MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
Page 7 of 33
CY7C1440AV33
HIGH, then the write operation is controlled by BWE and BWX
signals.
The CY7C1440AV33 provides byte write capability that is
described in the Write Cycle Descriptions table. Asserting the
byte write enable input (BWE) with the selected byte write (BWX)
input, will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the write operations.
Because CY7C1440AV33 is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Because CY7C1440AV33 is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Burst Sequences
The CY7C1440AV33 provides a two-bit wraparound counter, fed
by A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Asserting ADV LOW at clock rise will
automatically increment the burst counter to the next address in
the burst sequence. Both read and write burst operations are
supported.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
100
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05383 Rev. *N
Page 8 of 33
CY7C1440AV33
Truth Table
The truth table for CY7C1440AV33 follows. [2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H Tri-state
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H Tri-state
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H Tri-state
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-state
WRITE cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-state
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-state
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-state
WRITE cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
WRITE cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-state
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-state
WRITE cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
D
Q
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05383 Rev. *N
Page 9 of 33
CY7C1440AV33
Truth Table for Read/Write
The truth table for Read/Write for CY7C1440AV33 follows. [8, 9, 10]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function (CY7C1440AV33)
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05383 Rev. *N
Page 10 of 33
CY7C1440AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1440AV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with IEEE Standard
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
The CY7C1440AV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
Document Number: 38-05383 Rev. *N
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Page 11 of 33
CY7C1440AV33
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05383 Rev. *N
Page 12 of 33
CY7C1440AV33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05383 Rev. *N
Page 13 of 33
CY7C1440AV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
. 2 1 0
TDO
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05383 Rev. *N
UNDEFINED
Page 14 of 33
CY7C1440AV33
TAP AC Switching Characteristics
Over the operating Range
Parameter [11, 12]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Set-up Times
Hold Times
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels............................................... .VSS to 2.5 V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels.................. ........................1.5 V
Input timing reference levels.................. ......................1.25 V
Output reference levels .................. ...............................1.5 V
Output reference levels ................. ..............................1.25 V
Test load termination supply voltage ................ .............1.5 V
Test load termination supply voltage ................... ........1.25 V
3.3 V TAP AC Output Load Equivalent
1.5V
2.5 V TAP AC Output Load Equivalent
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
Notes
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05383 Rev. *N
Page 15 of 33
CY7C1440AV33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)
Parameter [13]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Test Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
Input HIGH voltage
Input LOW voltage
Input load current
GND < VIN < VDDQ
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
13. All voltages referenced to VSS (GND).
Document Number: 38-05383 Rev. *N
Page 16 of 33
CY7C1440AV33
Identification Register Definitions
CY7C1440AV33
(1M × 36)
Instruction Field
Revision number (31:29)
Device depth (28:24)
000
[14]
01011
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
Describes the version number.
Reserved for internal use
000000
Defines memory type and architecture
100111
Defines width and density
00000110100
ID register presence indicator (0)
Description
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary scan order (165-ball FBGA package)
89
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05383 Rev. *N
Page 17 of 33
CY7C1440AV33
Boundary Scan Order
165-ball FBGA [15, 16]
CY7C1440AV33 (1M × 36)
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
N10
27
D11
52
A2
77
N2
3
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
89
Internal
14
M11
39
C10
64
F2
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
J2
H10
48
A5
A4
72
23
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Notes
15. Balls that are NC (No Connect) are preset LOW.
16. Bit# 89 is preset HIGH.
Document Number: 38-05383 Rev. *N
Page 18 of 33
CY7C1440AV33
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.3 V to +4.6 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage on VDDQ relative to GND ...... –0.3 V to +VDD
Range
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0 °C to +70 °C
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Test Conditions
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH =4.0 mA
2.4
–
V
for 2.5 V I/O, IOH =1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
µA
Input current of MODE
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[17]
[17]
Input current of ZZ
IOZ
Output leakage current
GND VI VDDQ, output disabled
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
5
µA
4-ns cycle,
250 MHz
–
475
mA
6-ns cycle,
167 MHz
–
375
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
All speeds
–
225
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
120
mA
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ VDD.
Document Number: 38-05383 Rev. *N
Page 19 of 33
CY7C1440AV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
Test Conditions
Min
Max
Unit
ISB3
Automatic CE power-down
current – CMOS inputs
Description
VDD = Max, device deselected, or All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
–
200
mA
ISB4
Automatic CE Power-down
current – TTL Inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f=0
All speeds
–
135
mA
Capacitance
Parameter [19]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
6.5
7
pF
3
7
pF
5.5
6
pF
Thermal Resistance
Parameter [19]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
25.21
20.8
°C/W
2.28
3.2
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317
Z0 = 50
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
GND
R = 351
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1ns
1ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538
(b)
10%
90%
10%
90%
1ns
1ns
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05383 Rev. *N
Page 20 of 33
CY7C1440AV33
Switching Characteristics
Over the Operating Range
Parameter [20, 21]
tPOWER
Description
VDD(typical) to the first access [22]
-250
-167
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
6
–
ns
tCH
Clock HIGH
1.5
–
2.4
–
ns
tCL
Clock LOW
1.5
–
2.4
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.6
–
3.4
ns
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
ns
1.0
–
1.5
–
ns
tCLZ
Clock to low Z
[23, 24, 25]
[23, 24, 25]
tCHZ
Clock to high Z
tOEV
OE LOW to output valid
tOELZ
OE LOW to output low Z [23, 24, 25]
tOEHZ
OE HIGH to output high Z
[23, 24, 25]
–
2.6
–
3.4
ns
–
2.6
–
3.4
ns
0
–
0
–
ns
–
2.6
–
3.4
ns
Set-up Times
tAS
Address set-up before CLK rise
1.2
–
1.5
–
ns
tADS
ADSC, ADSP set-up before CLK rise
1.2
–
1.5
–
ns
tADVS
ADV set-up before CLK rise
1.2
–
1.5
–
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.2
–
1.5
–
ns
tCES
Chip enable set-up before CLK rise
1.2
–
1.5
–
ns
Hold Times
tAH
Address hold after CLK rise
0.3
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.3
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.3
–
0.5
–
ns
Notes
20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 3 on page 20. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 38-05383 Rev. *N
Page 21 of 33
CY7C1440AV33
Switching Waveforms
Figure 4. Read Cycle Timing [26]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05383 Rev. *N
Page 22 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 5. Write Cycle Timing [27, 28]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05383 Rev. *N
Page 23 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 6. Read/Write Cycle Timing [29, 30, 31]
tCYC
CLK
tCL
tCH
tADS
tADH
ADSP
ADSC
tAS
ADDRESS
A1
tAH
A2
A3
A4
tWES
tWEH
tDS
tDH
A5
A6
D(A5)
D(A6)
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tCO
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A4)
Q(A2)
Single WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
DON’T CARE
Back-to-Back
WRITEs
UNDEFINED
Notes
29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
30. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
31. GW is HIGH.
Document Number: 38-05383 Rev. *N
Page 24 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [32, 33]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t
ALL INPUTS
(except ZZ)
Outputs (Q)
RZZI
DESELECT or READ Only
High-Z
DON’T CARE
Notes
32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
33. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05383 Rev. *N
Page 25 of 33
CY7C1440AV33
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
167
CY7C1440AV33-167AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
250
CY7C1440AV33-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1440AV33-250AXI
CY7C1440AV33-250BZXI
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C
1440
A V33 - XXX XX
X
X
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: 167 MHz or 250 MHz
V33 = 3.3 V
Process Technology: A 90 nm
Part Identifier: 1440 = SCD, 1Mb × 36 (36Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05383 Rev. *N
Page 26 of 33
CY7C1440AV33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05383 Rev. *N
Page 27 of 33
CY7C1440AV33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 Ball Diameter) Package Outline, 51-85195
51-85195 *C
Document Number: 38-05383 Rev. *N
Page 28 of 33
CY7C1440AV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
ball grid array
CE
chip enable
°C
degree Celsius
CMOS
complementary metal oxide semiconductor
MHz
megahertz
EIA
electronic industries alliance
µA
microampere
FBGA
fine-pitch ball grid array
mA
milliampere
I/O
input/output
ms
millisecond
JEDEC
joint electron devices engineering council
mm
millimeter
JTAG
joint test action group
ns
nanosecond
LSB
least significant bit
ohm
MSB
most significant bit
%
percent
NoBL
No Bus Latency
pF
picofarad
OE
output enable
V
volt
SRAM
static random access memory
W
watt
TAP
test access port
TCK
test clock
TMS
test mode select
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
TTL
transistor-transistor logic
Document Number: 38-05383 Rev. *N
Symbol
Unit of Measure
Page 29 of 33
CY7C1440AV33
Document History Page
Document Title: CY7C1440AV33, 36-Mbit (1M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
124437
03/04/03
CJM
New data sheet.
*A
254910
See ECN
SYT
Updated Logic Block Diagram – CY7C1440AV33.
Updated Logic Block Diagram – CY7C1442AV33.
Updated Logic Block Diagram – CY7C1446AV33.
Updated Identification Register Definitions (Added Note 14 and referred the
same in Device Depth (28:24)).
Added Boundary Scan Order related information.
Updated Electrical Characteristics (Updated values of IDD, IX and ISB
parameters).
Updated Switching Characteristics (Added tPOWER parameter and its details).
Updated Switching Waveforms.
Updated Package Diagrams (Removed 119-ball PBGA package, changed
165-ball FBGA package from BB165C (15 × 17 × 1.20 mm) to BB165
(15 × 17 × 1.40 mm), changed 209-Lead PBGA BG209 (14 × 22 × 2.20 mm)
to BB209A (14 × 22 × 1.76 mm)).
*B
306335
See ECN
SYT
Updated Pin Configurations (Changed H9 pin from VSSQ to VSS for 209-ball
FBGA).
Updated Thermal Resistance (Replaced JA and JC values from TBD to
25.21 C/W and 2.58 C/W respectively for 100-pin TQFP Package, replaced
JA and JC values from TBD to respective Values for 165-ball FBGA and
209-ball FBGA Packages).
Updated Electrical Characteristics (Changed maximum value of IDD parameter
from 450 mA, 400 mA, and 350 mA to 475 mA, 425 mA, and 375 mA for
frequencies of 250 MHz, 200 MHz, and 167 MHz respectively, changed
maximum value of ISB1 parameter from 190 mA, 180 mA, and 170 mA to
225 mA for frequencies of 250 MHz, 200 MHz, and 167 MHz respectively,
changed maximum value of ISB2 from 80 mA to 100 mA, changed maximum
value of ISB3 from 180 mA, 170 mA, and 160 mA to 200 mA for frequencies of
250 MHz, 200 MHz, and 167 MHz respectively, changed maximum value of
ISB4 parameter from 100 mA to 110 mA).
Updated Switching Characteristics (Changed maximum value of tCO
parameter from 3.0 ns to 3.2 ns for 200 MHz frequency, changed minimum
value of tDOH parameter from 1.3 ns to 1.5 ns for 200 MHz frequency).
Updated Ordering Information (Added lead-free information for 100-pin TQFP,
165-ball FBGA and 209-ball FBGA Packages).
*C
332173
See ECN
SYT
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 165-ball FBGA and 209-ball FBGA Package as per JEDEC standards).
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters, changed maximum value of ISB2 and ISB4 parameters from
100 mA and 110 mA to 120 mA and 135 mA respectively).
Updated Capacitance (Changed value of CIN, CCLK and CI/O to 7 pF, 7 pF, and
6 pF from 5 pF, 5 pF, and 7 pF for 165-ball FBGA Package).
Updated Ordering Information (By Shading and Unshading MPNs as per
availability).
Updated Package Diagrams (Included 100-pin TQFP Package Diagram).
Document Number: 38-05383 Rev. *N
Page 30 of 33
CY7C1440AV33
Document History Page (continued)
Document Title: CY7C1440AV33, 36-Mbit (1M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*D
417547
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 18 (Changed test condition
from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE” in the description of
IX parameter, changed minimum value of IX corresponding to Input current of
MODE (Input = VSS) from –5 A to –30 A, changed maximum value of IX
corresponding to Input current of MODE (Input = VDD) from 30 A to 5 A
respectively, changed minimum value of IX corresponding to Input current of
ZZ (Input = VSS) from –30 A to –5 A, changed maximum value of IX
corresponding to Input current of ZZ (Input = VDD) from 5 A to 30 A).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams.
*E
473650
See ECN
VKN
Updated TAP AC Switching Characteristics (Changed minimum value of tTH,
tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*F
2897278
03/22/2010
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagrams.
*G
3044512
10/01/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*H
3055212
10/11/2010
NJY
Updated Ordering Information (Updated part numbers).
*I
3357006
08/29/2011
PRIT
Updated Package Diagrams.
Updated to new template.
*J
3424238
11/15/2011
PRIT
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Document Number: 38-05383 Rev. *N
Page 31 of 33
CY7C1440AV33
Document History Page (continued)
Document Title: CY7C1440AV33, 36-Mbit (1M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*K
3616631
05/14/2012
PRIT
Updated Features (Removed 200 MHz frequency related information, removed
CY7C1442AV33, CY7C1446AV33 related information, removed 209-ball
FBGA package related information).
Updated Functional Description (Removed CY7C1442AV33, CY7C1446AV33
related information, removed the Note “For best-practices recommendations,
please refer to the Cypress application note System Design Guidelines on
www.cypress.com.” and its reference).
Updated Selection Guide (Removed 200 MHz frequency related information).
Removed Logic Block Diagram – CY7C1442AV33.
Removed Logic Block Diagram – CY7C1446AV33.
Updated Pin Configurations (Updated Figure 1 (Removed CY7C1442AV33
related information), updated Figure 2 (Removed CY7C1442AV33 related
information), removed 209-ball FBGA package related information).
Updated Functional Overview (Removed CY7C1442AV33, CY7C1446AV33
related information).
Updated Truth Table (Removed CY7C1442AV33, CY7C1446AV33 related
information).
Removed Truth Table for Read/Write (Corresponding to CY7C1442AV33).
Removed Truth Table for Read/Write (Corresponding to CY7C1446AV33).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1442AV33, CY7C1446AV33 related information).
Updated Identification Register Definitions (Removed CY7C1442AV33,
CY7C1446AV33 related information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)”, “Bit Size (× 72)”
columns).
Updated Boundary Scan Order (Removed CY7C1442AV33 related
information).
Removed Boundary Scan Order (Corresponding to 209-ball FBGA package).
Updated Electrical Characteristics (Removed 200 MHz frequency related
information).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Switching Characteristics (Removed 200 MHz frequency related
information).
Updated Package Diagrams (Removed 209-ball FBGA Package related
information (spec 51-85167)).
*L
3749841
09/20/2012
PRIT
No technical updates.
Completing Sunset Review.
*M
4598634
12/16/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*N
5507288
11/02/2016
PRIT
Obsolete document.
Completing Sunset Review.
Document Number: 38-05383 Rev. *N
Page 32 of 33
CY7C1440AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05383 Rev. *N
Revised November 2, 2016
Page 33 of 33
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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