CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
36-Mbit (1 M × 36/2 M × 18/512 K × 72)
Pipelined Sync SRAM
36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync SRAM
Features
Functional Description[1]
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200 and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V/3.3 V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1440AV33, CY7C1442AV33 available in Pb-free 100-pin
TQFP package, Pb-free and non Pb-free 165-ball FBGA
package. CY7C1446AV33 available in Pb-free and non Pb-free
209-ball FBGA package
■
Also available in Pb-free packages
■
IEEE 1149.1 JTAG-compatible boundary scan
■
“ZZ” sleep mode option
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM
integrates 1 M × 36/2 M × 18 and 512 K × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
operates from a +3.3 V core power supply while all outputs may
operate with either a +2.5 or +3.3 V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05383 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 12, 2010
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Logic Block Diagram – CY7C1440AV33 (1 M × 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
GW
CE1
CE2
CE3
OE
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
BWA
BWE
MEMORY
ARRAY
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1442AV33 (2 M × 18)
A0, A1, A
ADDRESS
REGISTER
2 A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
BWA
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
E
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05383 Rev. *H
Page 2 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Logic Block Diagram – CY7C1446AV33 (512 K × 72)
A0, A1,A
ADDRESS
REGISTER
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BWH
DQH, DQPH
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
BWG
DQF, DQPF
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
BWF
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BWE
DQE, DQPE
WRITE DRIVER
DQ
E, DQP
BYTE
“a”E
WRITE DRIVER
BWD
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BWC
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
OUTPUT
BUFFERS
E
DQA, DQPA
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
SLEEP
CONTROL
Document Number: 38-05383 Rev. *H
Page 3 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Contents
Selection Guide ................................................................ 5
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table
(MODE = Floating or VDD) .............................................. 10
Linear Burst Address Table (MODE = GND) ................ 10
ZZ Mode Electrical Characteristics ............................... 10
Truth Table ..................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
TAP Controller State Diagram ....................................... 13
Test Access Port (TAP) ............................................. 13
TAP Controller Block Diagram ...................................... 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Timing ..................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
Document Number: 38-05383 Rev. *H
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
165-ball FBGA Boundary Scan Order .......................... 18
209-ball FBGA Boundary Scan Order .......................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read Cycle Timing .................................................... 23
Write Cycle Timing .................................................... 24
Read/Write Cycle Timing ........................................... 25
ZZ Mode Timing ........................................................ 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Page 4 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum access time
2.6
3.2
3.4
ns
Maximum operating current
475
425
375
mA
Maximum CMOS standby current
120
120
120
mA
Pin Configurations
Document Number: 38-05383 Rev. *H
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1442AV33
(2 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
50
CY7C1440AV33
(1 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 5 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Pin Configurations
(continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1440AV33 (1 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
NC/576M
VDDQ
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
A
NC
DQC
GW
VSS
VSS
ADSP
DQPC
DQC
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
A0
CY7C1442AV33 (2 M × 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
NC/144M
R
3
4
5
BWB
CE3
A
CE1
CE2
NC
6
NC
BWA
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VDDQ
NC
DQB
VDDQ
NC
DQB
VDDQ
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
DQB
NC
7
8
9
10
11
A
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC/1G
NC
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
A
NC/576M
DQPA
DQA
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 38-05383 Rev. *H
Page 6 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Pin Configurations
(continued)
209-ball FBGA (14 × 22 × 1.76 mm) Pinout
CY7C1446AV33 (512 K × 72)
1
2
3
A
DQG
DQG
B
DQG
DQG
BWSC
BWSG NC/288M BW
A
BWSB
C
DQG
DQG
BWSH
BWSD NC/144M CE1
NC/576M
D
DQG
DQG
VSS
NC
NC/1G
OE
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
F
DQC
DQC
VSS
VSS
VSS
G
DQC
H
DQC
J
DQC
DQC
VDDQ
VDDQ
VDD
K
NC
NC
CLK
NC
L
DQH
DQH
VDDQ
M
DQH
DQH
VSS
N
DQH
DQH
P
DQH
R
DQPD
T
A
4
CE2
5
ADSP
6
8
9
10
11
CE3
A
DQB
DQB
BWSF
DQB
DQB
BWSE
BWSA
DQB
DQB
NC
VSS
DQB
DQB
VDD
VDDQ
VDDQ
DQPF
DQPB
NC
VSS
VSS
VSS
DQF
DQF
VDDQ
VDDQ
DQF
DQF
ADSC
7
ADV
GW
DQC
VDDQ
VDDQ
VDD
NC
VDD
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
NC
VDD
VDDQ
VDDQ
DQF
DQF
VSS
VSS
VSS
NC
NC
NC
NC
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
V
DQD
DQD
W
DQD
DQD
DQPA
DQPE
A
A
A
A
A
A
DQE
DQE
A
A
A
A1
A
A
A
DQE
DQE
TMS
TDI
A
A0
A
TCK
DQE
DQE
NC/72M
TDO
Pin Definitions
Name
I/O
Description
A0, A1, A
Inputsynchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active.
A1: A0 are fed to the two-bit counter.
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
Inputsynchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Inputsynchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
Inputsynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Inputsynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
Note
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05383 Rev. *H
Page 7 of 34
[+] Feedback
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Pin Definitions (continued)
Name
I/O
Description
CE2
Inputsynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3
Inputsynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not
connected for BGA. Where referenced, CE3 is assumed active throughout this document
for BGA. CE3 is sampled only when a new external address is loaded.
OE
Inputasynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Inputsynchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Inputsynchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Inputsynchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
Inputasynchronous
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/Osynchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power supply
Power supply inputs to the core of the device.
VSS
VSSQ
VDDQ
MODE
Ground
I/O ground
Ground for the core of the device.
Ground for the I/O circuitry.
I/O power supply Power supply for the I/O circuitry.
Inputstatic
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode pin has an internal pull-up.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
synchronous
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAGclock
NC
–
No connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M
and NC/1G are address expansion pins are not internally connected to the die.
Document Number: 38-05383 Rev. *H
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
Page 8 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486 processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
Document Number: 38-05383 Rev. *H
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides byte write capability that is described in the Write
Cycle Descriptions table. Asserting the byte write enable input
(BWE) with the selected byte write (BWX) input, will selectively
write to only the desired bytes. Bytes not selected during a
byte write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
write operations.
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the output enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the Write operations.
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the output enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides a two-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the
burst sequence. Both read and write burst operations are
supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Page 9 of 34
[+] Feedback
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
guaranteed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
10
11
00
01
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
01
10
11
00
10
11
00
01
00
01
10
11
11
00
01
10
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
100
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05383 Rev. *H
Page 10 of 34
[+] Feedback
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Truth Table [3, 4, 5, 6, 7, 8]
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
Deselect cycle, power-down
Operation
None
H
X
X
L
X
L
X
WRITE OE CLK
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L-H Tri-state
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L-H Tri-state
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L-H Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L-H Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
X
X
DQ
L-H Tri-state
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L-H Tri-state
WRITE cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L-H Tri-state
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L-H
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L-H Tri-state
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L-H
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L-H Tri-state
WRITE cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-state
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L-H
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-state
WRITE cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Q
Q
Q
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05383 Rev. *H
Page 11 of 34
[+] Feedback
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Truth Table for Read/Write[9, 10, 11]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function (CY7C1440AV33)
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Truth Table for Read/Write[9, 10, 11]
GW
BWE
BWB
BWA
Read
Function (CY7C1442AV33)
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write bytes B, A
H
L
L
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Truth Table for Read/Write[9, 10, 11]
GW
BWE
BWX
Read
Function (CY7C1446AV33)
H
H
X
Read
H
L
All BW = H
Write byte x – (DQx and DQPx)
H
L
L
Write all bytes
H
L
All BW = L
Write all bytes
L
X
X
Notes
9. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
10. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be
enabled at the same time for any given write.
11. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05383 Rev. *H
Page 12 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with IEEE Standard 1149.1. The TAP
operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See TAP Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
1
2 1 0
TEST-LOGIC
RESET
TDI
Selection
Circuitry
0
0
RUN-TEST/
IDLE
Instruction Register
31 30 29 . . . 2 1 0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
0
SHIFT-IR
1
0
1
EXIT1-DR
1
TCK
EXIT1-IR
0
1
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
x . . . . . 2 1 0
Boundary Scan Register
0
SHIFT-DR
0
Identification Register
CAPTURE-IR
0
TDO
1
0
CAPTURE-DR
Selection
Circuitry
0
UPDATE-IR
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document Number: 38-05383 Rev. *H
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Page 13 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TAP Instruction Set
Overview
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
IDCODE
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Document Number: 38-05383 Rev. *H
BYPASS
EXTEST
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
Page 14 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
package). When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place the
output bus into a high Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Reserved
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05383 Rev. *H
UNDEFINED
Page 15 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
TAP AC Switching Characteristics
Over the operating Range[12, 13]
Parameter
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
Set-up Times
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Hold Times
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels............................................... .VSS to 2.5 V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels.................. ........................1.5 V
Input timing reference levels.................. ......................1.25 V
Output reference levels .................. ...............................1.5 V
Output reference levels ................. ..............................1.25 V
Test load termination supply voltage ................ .............1.5 V
Test load termination supply voltage ................... ........1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50
TDO
50
TDO
Z O= 50
20pF
Z O= 50
20pF
Notes
12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05383 Rev. *H
Page 16 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)[14]
Parameter
VOH1
Description
Test Conditions
Output HIGH voltage
VOH2
Output HIGH voltage
VOL1
Output LOW voltage
VOL2
Output LOW voltage
VIH
Input load current
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
Input LOW voltage
IX
Max
IOH = –1.0 mA, VDDQ = 2.5 V
Input HIGH voltage
VIL
Min
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
CY7C1440AV33
(1 M × 36)
Instruction Field
CY7C1442AV33
(2 M × 18)
CY7C1446AV33
(512 K × 72)
Description
Describes the version number.
Revision number (31:29)
000
000
000
Device depth (28:24)[15]
01011
01011
01011
Reserved for internal use
000000
000000
000000
Defines memory type and
architecture
Defines width and density
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
100111
010111
110111
00000110100
00000110100
00000110100
1
1
1
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x 36)
Bit Size (x 18)
Bit Size (x 72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary scan order (165-ball FBGA package)
89
89
–
Boundary scan order (209-ball FBGA package)
–
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
Notes
14. All voltages referenced to VSS (GND).
15. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05383 Rev. *H
Page 17 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Identification Codes (continued)
Instruction
Code
Description
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
165-ball FBGA Boundary Scan Order [16, 17]
CY7C1440AV33 (1 M × 36), CY7C1442AV33 (2 M × 18)
Bit #
ball ID
Bit #
ball ID
Bit #
ball ID
Bit #
ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
N10
27
D11
52
A2
77
N2
3
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
J2
H10
48
A5
A4
72
23
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Notes
16. Balls that are NC (No Connect) are preset LOW.
17. Bit# 89 is preset HIGH.
Document Number: 38-05383 Rev. *H
Page 18 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
209-ball FBGA Boundary Scan Order
[18, 19]
CY7C1446AV33 (512 K × 72)
Bit #
ball ID
Bit #
ball ID
Bit #
ball ID
Bit #
ball ID
1
W6
36
2
37
3
V6
U6
F6
71
K3
72
H6
C6
106
K8
107
K4
38
K9
73
B6
108
K6
4
W7
39
K10
74
A6
109
K2
5
V7
40
J11
75
A5
110
L2
6
U7
41
J10
76
B5
111
L1
7
T7
42
H11
77
C5
112
M2
8
V8
43
H10
78
D5
113
M1
9
U8
44
G11
79
D4
114
N2
10
T8
45
G10
80
C4
115
N1
11
V9
46
F11
81
A4
116
P2
12
U9
47
F10
82
B4
117
P1
13
P6
48
E10
83
C3
118
R2
14
W11
49
E11
84
B3
119
R1
15
W10
50
D11
85
A3
120
T2
16
V11
51
D10
86
A2
121
T1
17
V10
52
C11
87
A1
122
U2
18
U11
53
C10
88
B2
123
U1
19
U10
54
B11
89
B1
124
V2
20
T11
55
B10
90
C2
125
V1
21
T10
56
A11
91
C1
126
W2
22
R11
57
A10
92
D2
127
W1
23
R10
58
C9
93
D1
128
T6
24
P11
59
B9
94
E1
129
U3
25
P10
60
A9
95
E2
130
V3
26
N11
61
D7
96
F2
131
T4
27
N10
62
C8
97
F1
132
T5
28
M11
63
B8
98
G1
133
U4
29
M10
64
A8
99
G2
134
V4
30
L11
65
D8
100
H2
135
5W
31
L10
66
C7
101
H1
136
5V
32
K11
67
B7
102
J2
137
5U
33
M6
68
A7
103
J1
138
Internal
34
L6
69
D6
104
K1
35
J6
70
G6
105
N6
Notes
18. Balls that are NC (No Connect) are preset LOW.
19. Bit# 138 is preset HIGH.
Document Number: 38-05383 Rev. *H
Page 19 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Maximum Ratings
DC input voltage .................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND ........–0.3 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.3 V to +VDD
Range
DC voltage applied to outputs
in tri-state...........................................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0 °C to +70 °C
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range[20, 21]
Parameter
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
VDDQ
I/O supply voltage
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
VOH
Output HIGH voltage
for 2.5 V I/O
VOL
Output LOW voltage
VIH
Input HIGH voltage[20]
for 3.3 V I/O
VIL
Input LOW voltage[20]
for 2.5 V I/O
IX
Input leakage current
except ZZ and MODE
GND VI VDDQ
Input current of MODE
Input = VSS
Input = VDD
–
5
µA
Input current of ZZ
Input = VSS
–5
–
µA
2.375
2.625
V
for 3.3 V I/O, IOH =4.0 mA
2.4
–
V
for 2.5 V I/O, IOH =1.0 mA
2.0
–
V
–
0.4
V
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3V
V
for 2.5 V I/O
1.7
VDD + 0.3V
V
for 3.3 V I/O
–0.3
0.8
V
–0.3
0.7
V
–5
5
µA
–30
–
µA
Input = VDD
–
30
µA
–5
5
µA
4-ns cycle, 250 MHz
–
475
mA
5-ns cycle, 200 MHz
–
425
mA
6-ns cycle, 167 MHz
–
375
mA
All speeds
–
225
mA
VDD = Max, device deselected,
All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
120
mA
Automatic CE
power-down
current—CMOS inputs
VDD = Max, device deselected, or All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V
f = fMAX = 1/tCYC
–
200
mA
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f=0
–
135
mA
IOZ
Output leakage current GND VI VDDQ, output disabled
IDD
VDD operating supply
current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CE
power-down
current—TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
power-down
current—CMOS inputs
ISB3
ISB4
All speeds
Notes
20. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
21. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05383 Rev. *H
Page 20 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Capacitance[22]
Parameter
Test Conditions
100 TQFP
Max
TA = 25 C, f = 1 MHz,
VDD = 3.3 V
VDDQ = 2.5 V
6.5
7
5
pF
3
7
5
pF
5.5
6
7
pF
Test Conditions
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
165 FBGA 209 FBGA
Max
Max
Unit
Thermal Resistance[22]
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317
Z0 = 50
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
GND
R = 351
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1ns
1ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538
(b)
10%
90%
10%
90%
1ns
1ns
(c)
Note
22. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05383 Rev. *H
Page 21 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Switching Characteristics
Over the Operating Range [23, 24]
Description
Parameter
tPOWER
VDD(Typical) to the first access[25]
–250
–200
–167
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
5
–
6
–
ns
tCH
Clock HIGH
1.5
–
2.0
–
2.4
–
ns
tCL
Clock LOW
1.5
–
2.0
–
2.4
–
ns
–
2.6
–
3.2
–
3.4
ns
Output Times
tCO
Data output valid after CLK rise
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
1.5
–
ns
tCLZ
Clock to low Z[26, 27, 28]
1.0
–
1.3
–
1.5
–
ns
tCHZ
Clock to high
Z[26, 27, 28]
–
2.6
–
3.0
–
3.4
ns
tOEV
OE LOW to output valid
–
2.6
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
–
2.6
–
3.0
–
3.4
ns
1.2
–
1.4
–
1.5
–
ns
Z[26, 27, 28]
tOELZ
OE LOW to output low
tOEHZ
OE HIGH to output high Z[26, 27, 28]
Set-up Times
tAS
Address set-up before CLK rise
tADS
ADSC, ADSP set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tADVS
ADV set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCES
Chip enable set-up before CLK rise
1.2
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
Hold Times
Notes
23. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
25. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
26. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
27. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
28. This parameter is sampled and not 100% tested.
Document Number: 38-05383 Rev. *H
Page 22 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Switching Waveforms
Read Cycle Timing[29]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05383 Rev. *H
Page 23 of 34
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Switching Waveforms (continued)
Write Cycle Timing[30, 31]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
30. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05383 Rev. *H
Page 24 of 34
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Switching Waveforms (continued)
Read/Write Cycle Timing[32, 33, 34]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
32. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
33. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
34. GW is HIGH.
Document Number: 38-05383 Rev. *H
Page 25 of 34
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Switching Waveforms (continued)
ZZ Mode Timing[35, 36]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
35. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
36. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05383 Rev. *H
Page 26 of 34
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Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
250
Ordering Code
CY7C1440AV33-167AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
CY7C1440AV33-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
CY7C1440AV33-250AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Industrial
Ordering Code Definitions
CY7C 1440
A V33 - XXX XX
X
Temperature range: X = C or I
C = Commercial; I = Industrial
Package Type: XX = AX or BZ
AX = 100-pin TQFP (Pb-free)
BZ = 165-ball FPBGA
Speed Grade (167 MHz / 250 MHz)
V33 = 3.3 V
Process Technology 90 nm
1440 = SCD, 1 Mb × 36 (36 Mb)
CY7C = Cypress SRAMs
Document Number: 38-05383 Rev. *H
Page 27 of 34
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Package Diagrams
100-pin TQFP (14 × 20 × 1.4 mm), 51-85050
51-85050 *C
Document Number: 38-05383 Rev. *H
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Package Diagrams
(continued)
165-ball FBGA (15 × 17 × 1.4 mm), 51-85165
51-85165 *B
Document Number: 38-05383 Rev. *H
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Package Diagrams
(continued)
209-ball FBGA (14 × 22 × 1.76 mm), 51-85167
51-85167 *A
Document Number: 38-05383 Rev. *H
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Acronyms
Document Conventions
Acronym
Description
Units of Measure
CE
chip enable
CEN
clock enable
ns
nano seconds
CMOS
complementary metal oxide semiconductor
V
Volts
FPBGA
fine-pitch ball grid array
µA
micro Amperes
I/O
input/output
mA
milli Amperes
JTAG
Joint Test Action Group
ms
milli seconds
NoBL
No Bus Latency
mm
milli meter
OE
output enable
MHz
Mega Hertz
SRAM
static random access memory
pF
pico Farad
TCK
test clock
W
Watts
TMS
test mode select
°C
degree Celcius
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
WE
write enable
Document Number: 38-05383 Rev. *H
Symbol
Unit of Measure
Page 31 of 34
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Document History Page
Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync
SRAM
Document Number: 38-05383
REV.
ECN NO.
Issue Date
Orig. of
Change
**
124437
03/04/03
CJM
New data sheet
*A
254910
See ECN
SYT
Part number changed from previous revision. New and old part number differ
by the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Boundary scan information
Added Footnote #14 (32-Bit Vendor ID Code changed)
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA package
Changed 165 FBGA package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22
x 1.76 mm)
*B
306335
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA on Page # 6
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz
speed bin on the Switching Characteristics table on Page # 19
Changed JA and JC from TBD to 25.21 and 2.58 C/W respectively for
TQFP Package on Pg # 19
Replaced JA and JC from TBD to respective Values for 165 BGA and 209
FBGA Packages on the Thermal Resistance Table
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 FBGA
Packages
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for
frequencies of 250, 200 and 167 MHz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for frequencies of 250,
200 and 167 MHz respectively
Changed ISB2 from 80 to 100 mA
Changed ISB3 from 180, 170 and 160 mA to 200 mA for frequencies of 250,
200 and 167 MHz respectively
Changed ISB4 from 100 to 110 mA
*C
332173
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209
FBGA Package as per JEDEC standards
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Added Industrial Temperature Grade
Included the missing 100 TQFP Package Diagram
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
Document Number: 38-05383 Rev. *H
Description of Change
Page 32 of 34
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Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync
SRAM
Document Number: 38-05383
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
*D
417547
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 A to –30 & 5 A respectively and also Changed IX current value in ZZ from –30 & 5 A to –5 & 30
A respectively on page# 18
Modified test condition in note# 8 from VIH < VDD to VIH VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*E
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*F
2897278
03/22/2010
NJY
Removed obsolete part numbers from Ordering Information table and
updated package diagrams.
*G
3044512
10/01/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H
3055212
10/11/2010
NJY
Updated Ordering Information.
Document Number: 38-05383 Rev. *H
Page 33 of 34
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05383 Rev. *H
Revised October 12, 2010
Page 34 of 34
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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