CY7C1440KV25-250BZXIT

CY7C1440KV25 36-Mbit (1M × 36) Pipelined Sync SRAM 36-Mbit (1M × 36) Pipelined Sync SRAM Features Functional Description ■ Supports bus operation up to 250 MHz ■ Available speed grade is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ 2.5-V core power supply ■ 2.5-V I/O power supply ■ Fast clock-to-output times ❐ 2.5 ns (for 250-MHz device) ■ Provide high-performance 3-1-1-1 access rate ■ User-selectable burst counter supporting interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Single-cycle Chip Deselect ■ CY7C1440KV25 available in Pb-free 165-ball FBGA package. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode Option The CY7C1440KV25 SRAM integrates 1M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one, two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440KV25 operates from a +2.5 V core power supply while all outputs may operate with a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description Maximum access time Maximum operating current Cypress Semiconductor Corporation Document Number: 001-94719 Rev. *D × 36 • 198 Champion Court • San Jose, CA 95134-1709 250 MHz Unit 2.5 ns 240 mA • 408-943-2600 Revised June 30, 2016 CY7C1440KV25 Logic Block Diagram – CY7C1440KV25 A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE DRIVER BWC DQC ,DQPC BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD DQA ,DQPA BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY PIPELINED ENABLE INPUT REGISTERS SLEEP CONTROL Document Number: 001-94719 Rev. *D Page 2 of 30 CY7C1440KV25 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 7 Burst Sequences ......................................................... 7 Sleep Mode ................................................................. 7 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10 Disabling the JTAG Feature ...................................... 10 Test Access Port (TAP) ............................................. 10 PERFORMING A TAP RESET .................................. 10 TAP REGISTERS ...................................................... 10 TAP Instruction Set ................................................... 11 TAP Controller State Diagram ....................................... 12 TAP Controller Block Diagram ...................................... 13 TAP Timing ...................................................................... 13 TAP AC Switching Characteristics ............................... 14 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 TAP DC Electrical Characteristics and Operating Conditions ............................................. 15 Document Number: 001-94719 Rev. *D Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 16 Instruction Codes ........................................................... 16 Boundary Scan Order .................................................... 17 Maximum Ratings ........................................................... 18 Operating Range ............................................................. 18 Neutron Soft Error Immunity ......................................... 18 Electrical Characteristics ............................................... 18 DC Electrical Characteristics ..................................... 18 Capacitance .................................................................... 19 Thermal Resistance ........................................................ 19 AC Test Loads and Waveforms ..................................... 20 Switching Characteristics .............................................. 21 Switching Waveforms .................................................... 22 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Package Diagram ............................................................ 27 Acronyms ........................................................................ 28 Document Conventions ................................................. 28 Units of Measure ....................................................... 28 Document History Page ................................................. 29 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC®Solutions ....................................................... 30 Cypress Developer Community ................................. 30 Technical Support ..................................................... 30 Page 3 of 30 CY7C1440KV25 Pin Configurations Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) Pinout CY7C1440KV25 (1M × 36) 1 A B C D E F G H J K L M N P NC/288M R 2 A 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK DQPC DQC NC DQC VDDQ VSS VSS VSS VSS GW VSS VSS OE VSS VDD ADSP VDDQ VDDQ VSS VDD A NC/576M VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE A A A TMS TCK A A A A Document Number: 001-94719 Rev. *D A0 Page 4 of 30 CY7C1440KV25 Pin Definitions Name I/O Description A0, A1, A Input-Synchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit counter. BWA, BWB, BWC, BWD Input-Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW Input-Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE Input-Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input-Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP Input-Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ Input-Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPs VDD VSS I/O-Synchronous Power Supply Ground VSSQ I/O Ground VDDQ I/O Power Supply Document Number: 001-94719 Rev. *D Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the I/O circuitry. Power supply for the I/O circuitry. Page 5 of 30 CY7C1440KV25 Pin Definitions (continued) Name MODE I/O Description Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being utilized, this pin should be disconnected. TDI JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. TMS JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. TCK JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. NC – No Connects. Not internally connected to the die NC/72M, NC/144M, NC/288M, NC/576, NC/1G – No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are address expansion pins are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.5 ns (250-MHz device). The CY7C1440KV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. Document Number: 001-94719 Rev. *D At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.5 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tristate immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The CY7C1440KV25 provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1440KV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tristate the output drivers. As a safety precaution, DQs are automatically tristated whenever a Write cycle is detected, regardless of the state of OE. Page 6 of 30 CY7C1440KV25 Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because CY7C1440KV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tristate the output drivers. As a safety precaution, DQs are automatically tristated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1440KV25 provides a two-bit wraparound counter, fed by A1:A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 75 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-94719 Rev. *D Page 7 of 30 CY7C1440KV25 Truth Table The truth table for CY7C1440KV25 follows. [1, 2, 3, 4, 5, 6] Operation Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L–H Tristate Deselect Cycle, Power Down None L L X L L X X X X L–H Tristate Deselect Cycle, Power Down None L X H L L X X X X L–H Tristate Deselect Cycle, Power Down None L L X L H L X X X L–H Tristate Deselect Cycle, Power Down None L X H L H L X X X L–H Tristate Sleep Mode, Power Down None X X X H X X X X X X Tristate READ Cycle, Begin Burst External L H L L L X X X L L–H Q READ Cycle, Begin Burst External L H L L L X X X H L–H Tristate WRITE Cycle, Begin Burst External L H L L H L X L X L–H D READ Cycle, Begin Burst External L H L L H L X H L L–H Q READ Cycle, Begin Burst External L H L L H L X H H L–H Tristate READ Cycle, Continue Burst Next X X X L H H L H L L–H Q READ Cycle, Continue Burst Next X X X L H H L H H L–H Tristate READ Cycle, Continue Burst Next H X X L X H L H L L–H Q READ Cycle, Continue Burst Next H X X L X H L H H L–H Tristate WRITE Cycle, Continue Burst Next X X X L H H L L X L–H D WRITE Cycle, Continue Burst Next H X X L X H L L X L–H D READ Cycle, Suspend Burst Current X X X L H H H H L L–H Q READ Cycle, Suspend Burst Current X X X L H H H H H L–H Tristate READ Cycle, Suspend Burst Current H X X L X H H H L L–H Q READ Cycle, Suspend Burst Current H X X L X H H H H L–H Tristate WRITE Cycle, Suspend Burst Current X X X L H H H L X L–H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L–H D Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. BGA package has only two chip selects CE1 and CE2. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-94719 Rev. *D Page 8 of 30 CY7C1440KV25 Truth Table for Read/Write The Truth Table for Read/Write for CY7C1440KV25 follows. [7, 8, 9] Function (CY7C1440KV25) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) H L H H H L Write Byte B – (DQB and DQPB) H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes 7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 8. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled at the same time for any given write. 9. This table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document Number: 001-94719 Rev. *D Page 9 of 30 CY7C1440KV25 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1440KV25 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1.The TAP operates using JEDEC-standard 2.5 V I/O logic level. The CY7C1440KV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature At power-up, the TAP is reset internally to ensure that TDO comes up in a High Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Instruction Register Test Access Port (TAP) When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 12. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction Codes on page 16). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Document Number: 001-94719 Rev. *D Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order on page 17 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 16. Page 10 of 30 CY7C1440KV25 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes on page 16. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured Document Number: 001-94719 Rev. *D correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the clock captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required — that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tristate”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 30 CY7C1440KV25 TAP Controller State Diagram The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR Document Number: 001-94719 Rev. *D 1 0 PAUSE-DR 1 0 1 EXIT1-DR 0 1 0 UPDATE-IR 1 0 Page 12 of 30 CY7C1440KV25 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . Selection Circuitry . 2 1 0 TDO Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS TAP CONTROLLER TAP Timing Figure 2. TAP Timing 1 2 Test Clock (TCK) 3 tTH tTMSS tTMSH tTDIS tTDIH t TL 4 5 6 tCYC Test Mode Select (TMS) Test Data-In (TDI) tTDOV tTDOX Test Data-Out (TDO) DON’T CARE Document Number: 001-94719 Rev. *D UNDEFINED Page 13 of 30 CY7C1440KV25 TAP AC Switching Characteristics Over the Operating Range Parameter [10, 11] Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 – ns tTF TCK Clock Frequency – 20 MHz tTH TCK Clock HIGH time 20 – ns tTL TCK Clock LOW time 20 – ns tTDOV TCK Clock LOW to TDO Valid – 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 – ns tTMSS TMS Setup to TCK Clock Rise 5 – ns tTDIS TDI Setup to TCK Clock Rise 5 – ns tCS Capture Setup to TCK Rise 5 tTMSH TMS Hold after TCK Clock Rise 5 – ns tTDIH TDI Hold after Clock Rise 5 – ns tCH Capture Hold after Clock Rise 5 – ns Output Times Setup Times ns Hold Times Notes 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate). Document Number: 001-94719 Rev. *D Page 14 of 30 CY7C1440KV25 2.5 V TAP AC Test Conditions 2.5 V TAP AC Output Load Equivalent 1.25V Input pulse levels ...............................................VSS to 2.5 V Input rise and fall times (Slew Rate) ........................... 2 V/ns 50Ω Input timing reference levels ....................................... 1.25 V Output reference levels .............................................. 1.25 V TDO Test load termination supply voltage .......................... 1.25 V Z O= 50Ω 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted) Parameter [12] Min Max Unit VOH1 Output HIGH Voltage Description IOH = –1.0 mA Test Conditions VDDQ = 2.5 V 1.7 – V VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 2.5 V 2.1 – V VOL1 Output LOW Voltage IOL = 1.0 mA VDDQ = 2.5 V – 0.4 V VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 2.5 V – 0.2 V VIH Input HIGH Voltage – VDDQ = 2.5 V 1.7 VDD + 0.3 V VIL Input LOW Voltage – VDDQ = 2.5 V –0.3 0.7 V IX Input Load Current –5 5 µA GND < VIN < VDDQ Note 12. All voltages referenced to VSS (GND). Document Number: 001-94719 Rev. *D Page 15 of 30 CY7C1440KV25 Identification Register Definitions CY7C1440KV25 (1M × 36) Instruction Field Revision Number (31:29) 000 Device Depth (28:24) 01011 Description Describes the version number. Reserved for Internal Use Architecture/Memory Type (23:18) 000000 Defines memory type and architecture Bus Width/Density (17:12) 100111 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary Scan Order (165-ball FBGA package) 89 Instruction Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. BYPASS Document Number: 001-94719 Rev. *D Page 16 of 30 CY7C1440KV25 Boundary Scan Order 165-ball FBGA [13, 14] CY7C1440KV25 (1M × 36) Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 N10 27 D11 52 A2 77 N2 3 28 G10 53 B2 78 P1 4 P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39 C10 64 F2 89 Internal 15 L11 40 A8 65 G2 16 K11 41 B8 66 H1 17 J11 42 A7 67 H3 18 M10 43 B7 68 J1 19 L10 44 B6 69 K1 20 K10 45 A6 70 L1 21 J10 46 B5 71 M1 22 H9 47 J2 H10 48 A5 A4 72 23 73 K2 24 G11 49 B4 74 L2 25 F11 50 B3 75 M2 Notes 13. Balls which are NC (No Connect) are Pre-Set LOW. 14. Bit# 89 is Pre-Set HIGH. Document Number: 001-94719 Rev. *D Page 17 of 30 CY7C1440KV25 Maximum Ratings Operating Range Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature VDD VDDQ –40 °C to +85 °C 2.5 V+ 5% 2.5 V – 5% to VDD Range Industrial Ambient Temperature with Power Applied .................................. –55 °C to +125 °C Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD DC Voltage Applied to Outputs in Tristate ..........................................–0.5 V to VDDQ + 0.5 V Neutron Soft Error Immunity Parameter Description DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Latch-up Current ................................................... > 200 mA Test Conditions Typ Max* Unit LSBU Logical Single-Bit Upsets 25 °C –2 V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-94719 Rev. *D Page 18 of 30 CY7C1440KV25 Electrical Characteristics Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [15, 16] Min Max Unit IDD VDD Operating Supply Current Description VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC Test Conditions 4-ns cycle, 250 MHz – 240 mA ISB1 Automatic CE Power-down Current – TTL Inputs VDD = Max, Device Deselected, VIN  VIH or VIN  VIL, f = fMAX = 1/tCYC All speeds – 90 mA ISB2 Automatic CE Power-down Current – CMOS Inputs VDD = Max, Device Deselected, All speeds VIN  0.3 V or VIN > VDDQ – 0.3 V, f=0 – 80 mA ISB3 Automatic CE Power-down Current – CMOS Inputs VDD = Max, Device Deselected, All speeds VIN  0.3 V or VIN > VDDQ – 0.3 V, f = fMAX = 1/tCYC – 90 mA ISB4 Automatic CE Power-down Current – TTL Inputs VDD = Max, Device Deselected, VIN  VIH or VIN  VIL, f = 0 – 80 mA All speeds Capacitance Parameter [17] Description CIN Input capacitance CCLK CI/O Test Conditions TA = 25 °C, f = 1 MHz, VDD/VDDQ = 2.5 V 165-ball FBGA Unit Max 5 pF Clock input capacitance 5 pF Input/Output capacitance 5 pF Thermal Resistance Parameter [17] JA Description Thermal resistance (junction to ambient) Test Conditions Test conditions follow standard With Still Air (0 m/s) test methods and procedures for With Air Flow (1 m/s) measuring thermal impedance, per EIA/JESD51. With Air Flow (3 m/s) 165-ball FBGA Unit Package 14.24 °C/W 12.47 °C/W 11.40 °C/W JC Thermal resistance (junction to case) 3.92 °C/W JB Thermal resistance (junction to board) 7.19 °C/W Note 17. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-94719 Rev. *D Page 19 of 30 CY7C1440KV25 AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 2.5 V I/O Test Load R = 1667  2.5 V OUTPUT OUTPUT RL = 50  Z0 = 50  VT = 1.25 V (a) Document Number: 001-94719 Rev. *D ALL INPUT PULSES VDDQ GND 5 pF INCLUDING JIG AND SCOPE R = 1538  (b) 10% 90% 10% 90%  1 ns 2 V/ns (c) Page 20 of 30 CY7C1440KV25 Switching Characteristics Over the Operating Range Parameter [18, 19] tPOWER Description VDD(typical) to the first Access[20] -250 Unit Min Max 1 – ms Clock tCYC Clock Cycle Time 4.0 – ns tCH Clock HIGH 1.5 – ns tCL Clock LOW 1.5 – ns Output Times tCO Data Output Valid After CLK Rise – 2.5 ns tDOH Data Output Hold After CLK Rise 1.0 – ns 1.0 – ns – 2.6 ns – 2.6 ns 0 – ns – 2.6 ns [21, 22, 23] tCLZ Clock to Low Z tCHZ Clock to High Z [21, 22, 23] tOEV OE LOW to Output Valid tOELZ tOEHZ OE LOW to Output Low Z [21, 22, 23] OE HIGH to Output High Z [21, 22, 23] Setup Times tAS Address Setup Before CLK Rise 1.2 – ns tADS ADSC, ADSP Setup Before CLK Rise 1.2 – ns tADVS ADV Setup Before CLK Rise 1.2 – ns tWES GW, BWE, BWX Setup Before CLK Rise 1.2 – ns tDS Data Input Setup Before CLK Rise 1.2 – ns tCES Chip Enable Setup Before CLK Rise 1.2 – ns tAH Address Hold After CLK Rise 0.3 – ns tADH ADSP, ADSC Hold After CLK Rise 0.3 – ns tADVH ADV Hold After CLK Rise 0.3 – ns tWEH GW, BWE, BWX Hold After CLK Rise 0.3 – ns tDH Data Input Hold After CLK Rise 0.3 – ns tCEH Chip Enable Hold After CLK Rise 0.3 – ns Hold Times Notes 18. Timing reference level is 1.25 V when VDDQ = 2.5 V. 19. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted. 20. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 20. Transition is measured ± 200 mV from steady-state voltage. 22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 23. This parameter is sampled and not 100% tested. Document Number: 001-94719 Rev. *D Page 21 of 30 CY7C1440KV25 Switching Waveforms Figure 4. Read Cycle Timing [24] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BWx tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-94719 Rev. *D Page 22 of 30 CY7C1440KV25 Switching Waveforms (continued) Figure 5. Write Cycle Timing [25, 26] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 001-94719 Rev. *D Page 23 of 30 CY7C1440KV25 Switching Waveforms (continued) Figure 6. Read/Write Cycle Timing [27, 28, 29] tCYC CLK tCL tCH tADS tADH ADSP ADSC tAS ADDRESS A1 tAH A2 A3 A4 tWES tWEH tDS tDH A5 A6 D(A5) D(A6) BWE, BWX tCES tCEH CE ADV OE tCO tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) tOEHZ D(A3) Q(A4) Q(A2) Back-to-Back READs Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH. Document Number: 001-94719 Rev. *D Page 24 of 30 CY7C1440KV25 Switching Waveforms (continued) Figure 7. ZZ Mode Timing [30, 31] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-94719 Rev. *D Page 25 of 30 CY7C1440KV25 Ordering Information Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Ordering Information Speed (MHz) 250 Ordering Code CY7C1440KV25-250BZXI Package Diagram 51-85195 Part and Package Type 165-ball FBGA (15 × 17 × 1.4mm) Pb-free Operating Range Industrial Ordering Code Definitions CY 7 C 144X K V25 - 250 BZ X I Temperature range: I = Industrial = –40 °C to +85 °C Pb-free Package Type: BZ = 165-ball FBGA Speed grade: 250 MHz V25 = 2.5 V Process Technology: K = greater than or equal to 65 nm Part Identifier: 1440 = SCD 1Mb × 36 (36Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-94719 Rev. *D Page 26 of 30 CY7C1440KV25 Package Diagram Figure 8. 165-ball FBGA ((15 × 17 × 1.40 mm) 0.50 Ball Diameter) Package Outline, 51-85195 51-85195 *D Document Number: 001-94719 Rev. *D Page 27 of 30 CY7C1440KV25 Acronyms Document Conventions Table 2. Acronyms Used in this Document Units of Measure Acronym Description Table 3. Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius FBGA Fine-Pitch Ball Grid Array MHz megahertz I/O Input/Output µA microampere JTAG Joint Test Action Group µs microsecond LSB Least Significant Bit mA milliampere MSB Most Significant Bit mm millimeter OE Output Enable ms millisecond SRAM Static Random Access Memory mV millivolt TCK Test Clock ns nanosecond TDI Test Data-In % percent TDO Test Data-Out pF picofarad TMS Test Mode Select V volt TTL Transistor-Transistor Logic W watt WE Write Enable Document Number: 001-94719 Rev. *D Symbol Unit of Measure Page 28 of 30 CY7C1440KV25 Document History Page Document Title: CY7C1440KV25, 36-Mbit (1M × 36) Pipelined Sync SRAM Document Number: 001-94719 Revision ECN Orig. of Change Submission Date *B 4680529 PRIT 04/10/2015 Changed status from Preliminary to Final. *C 4757974 DEVM 05/07/2015 Updated Functional Overview: Updated ZZ Mode Electrical Characteristics: Changed maximum value of IDDZZ parameter from 89 mA to 75 mA. *D 5331734 PRIT 06/30/2016 Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU parameter. Updated to new template. Document Number: 001-94719 Rev. *D Description of Change Page 29 of 30 CY7C1440KV25 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/clocks cypress.com/interface cypress.com/powerpsoc cypress.com/memory PSoC Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2014-2016. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-94719 Rev. *D Revised June 30, 2016 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Page 30 of 30