CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
36-Mbit (1M × 36/2M × 18)
Pipelined Sync SRAM (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined Sync SRAM (With ECC)
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250 MHz and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V or 3.3 V I/O power supply
■
Fast clock-to-output time
❐ 2.5 ns (for 250 MHz device)
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting interleaved or linear
burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are
available in Pb-free 100-pin TQFP, and Pb-free and non Pb-free
165-ball FBGA packages.
■
IEEE 1149.1 JTAG-compatible boundary scan
■
“ZZ” sleep mode option
■
On-Chip error correction code (ECC) to reduce soft error rate
(SER)
The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM
integrate 1M × 36/2M × 18/1M × 36 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
250 MHz
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-66676 Rev. *G
•
198 Champion Court
•
167 MHz
Unit
2.5
3.4
ns
× 18
220
Not Offered
mA
× 36
240
190
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2016
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Logic Block Diagram – CY7C1440KV33
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
E
OUTPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
BWA
BWE
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1442KV33
A0, A1, A
ADDRESS
REGISTER
2 A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
BWA
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
E
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 001-66676 Rev. *G
Page 2 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Logic Block Diagram – CY7C1440KVE33
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
ECC
DECODER
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
GW
CE1
CE2
CE3
OE
MEMORY
ARRAY
PIPELINED
ENABLE
ECC
ENCODER
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 001-66676 Rev. *G
Page 3 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
On-Chip ECC .............................................................. 9
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
Document Number: 001-66676 Rev. *G
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC®Solutions ....................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 4 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Pin Configurations
Document Number: 001-66676 Rev. *G
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1442KV33
(2M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
CY7C1440KV33/CY7C1440KVE33 66
65
64
(1M × 36)
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP Pinout
Page 5 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Pin Configurations (continued)
Figure 2. 165-ball FBGA Pinout
CY7C1440KV33 (1M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
NC/576M
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
A
NC
DQC
GW
VSS
VSS
ADSP
DQPC
DQC
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
DQB
NC
DQA
DQB
DQB
ZZ
DQA
DQC
NC
DQD
VSS
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
Document Number: 001-66676 Rev. *G
A0
Page 6 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Pin Definitions
Name
A0, A1, A
I/O
Description
Input-synchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[1]are
sampled active. A1: A0 are fed to the two-bit counter.
BWA, BWB, BWC, BWD Input-synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (all bytes are written, regardless of the values on BWX
and BWE).
GW
Input-synchronous
BWE
Input-synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
Input-synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ
package version. Not connected for BGA. Where referenced, CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address
is loaded.
OE
Input-asynchronous Output enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
Input-asynchronous ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power supply
Power supply inputs to the core of the device.
Note
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 001-66676 Rev. *G
Page 7 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Pin Definitions (continued)
Name
I/O
Description
VSS
Ground
Ground for the core of the device.
VSSQ
I/O ground
Ground for the I/O circuitry.
VDDQ
I/O power supply
Power supply for the I/O circuitry.
MODE
Input-static
Selects burst order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode pin has an internal pull-up.
TDO
JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be disconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TMS
JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAG-clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M,
NC/1G
–
No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.5 ns (250-MHz
device).
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
support secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium processors. The burst order is user selectable,
and is determined by sampling the MODE input. Accesses can
be initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed Write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Document Number: 001-66676 Rev. *G
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within 2.5 ns (250-MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
Page 8 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
provide byte write capability that is described in the Write Cycle
Descriptions table. Asserting the byte write enable input (BWE)
with the selected byte write (BWX) input, will selectively write to
only the desired bytes. Bytes not selected during a byte write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the write operations.
Because CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
are common I/O devices, the output enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a Write cycle is
detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations.
Because CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
are common I/O devices, the output enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety precaution,
Document Number: 001-66676 Rev. *G
DQs are automatically tri-stated whenever a Write cycle is
detected, regardless of the state of OE.
Burst Sequences
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
provide a two-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The burst sequence is user
selectable through the MODE input. Asserting ADV LOW at
clock rise will automatically increment the burst counter to the
next address in the burst sequence. Both read and write burst
operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
On-Chip ECC
CY7C1440KVE33 SRAMs include an on-chip ECC algorithm
that detects and corrects all single-bit memory errors, including
Soft Error Upset (SEU) events induced by cosmic rays, alpha
particles etc. The resulting Soft Error Rate (SER) of these
devices
is
anticipated to be
VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-66676 Rev. *G
Page 10 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Truth Table
The truth table for CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 is as follows [2, 3, 4, 5, 6, 7].
Operation
Add. Used
CE1 CE2 CE3
ZZ
ADSP
ADSC
Deselect cycle, power-down
None
H
X
Deselect cycle, power-down
None
L
Deselect cycle, power-down
None
Deselect cycle, power-down
ADV WRITE
OE
CLK
DQ
X
L
X
L
X
X
X
L–H
Tri-state
L
X
L
L
X
X
X
X
L–H
Tri-state
L
X
H
L
L
X
X
X
X
L–H
Tri-state
None
L
L
X
L
H
L
X
X
X
L–H
Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tri-state
WRITE cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tri-state
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tri-state
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tri-state
WRITE cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
WRITE cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tri-state
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tri-state
WRITE cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-66676 Rev. *G
Page 11 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1440KV33/CY7C1440KVE33 is as follows. [8, 9, 10]
Function (CY7C1440KV33/CY7C1440KVE33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1442KV33 is as follows. [8, 9, 10]
Function (CY7C1442KV33)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write bytes B, A
H
L
L
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 001-66676 Rev. *G
Page 12 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Registers
The CY7C1440KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with IEEE Standard
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1440KV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram on page 15).
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram on page 15).
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 19 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Document Number: 001-66676 Rev. *G
Page 13 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in this section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable
results may not be possible.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the clock captured in the boundary scan
register.
Document Number: 001-66676 Rev. *G
Page 14 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
TAP Controller State Diagram
1
TAP Controller Block Diagram
TEST-LOGIC
RESET
0
Bypass Register
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
0
1
CAPTURE-DR
Instruction Register
31 30 29 .
CAPTURE-IR
0
x .
SHIFT-IR
1
.
. 2 1 0
Selection
Circuitry
TDO
Identification Register
0
SHIFT-DR
.
.
.
. 2 1 0
Boundary Scan Register
0
1
EXIT1-DR
1
1
EXIT1-IR
0
TCK
TMS
0
PAUSE-DR
0
PAUSE-IR
1
TAP CONTROLLER
0
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
Selection
Circuitry
TDI
0
1
0
0
2 1 0
1
SELECT
IR-SCAN
UPDATE-IR
1
0
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-66676 Rev. *G
UNDEFINED
Page 15 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
TAP AC Switching Characteristics
Over the operating Range
Parameter [11, 12]
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS set-up to TCK clock rise
5
–
ns
tTDIS
TDI set-up to TCK clock rise
5
–
ns
tCS
Capture set-up to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Output Times
Set-up Times
Hold Times
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels .............................................. .VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ................. ........................1.5 V
Input timing reference levels ................. ......................1.25 V
Output reference levels ................. ...............................1.5 V
Output reference levels ................ ..............................1.25 V
Test load termination supply voltage ............... .............1.5 V
Test load termination supply voltage .................. ........1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
Notes
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).
Document Number: 001-66676 Rev. *G
Page 16 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)
Parameter [13]
VOH1
Description
Output HIGH voltage
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
Test Conditions
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
VDDQ = 3.3 V
2.9
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW voltage
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VOL2
Output LOW voltage
VIH
Input HIGH voltage
VIL
Input LOW voltage
IX
Input load current
–
–
GND < VIN < VDDQ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
13. All voltages referenced to VSS (GND).
Document Number: 001-66676 Rev. *G
Page 17 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Identification Register Definitions
Instruction Field
CY7C1440KV33 (1M × 36)
Revision number (31:29)
000
Device depth (28:24)[14]
01011
Description
Describes the version number.
Reserved for internal use.
Architecture/memory type (23:18)
000000
Defines memory type and architecture.
Bus width/density(17:12)
100111
Defines width and density.
Cypress JEDEC ID code (11:1)
00000110100
ID register presence indicator (0)
1
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary scan order (165-ball FBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-66676 Rev. *G
Page 18 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Boundary Scan Order
165-ball FBGA [15, 16]
CY7C1440KV33 (1M × 36)
Bit #
Ball ID
Bit #
Ball ID
Bit #
ball ID
Bit #
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
N10
27
D11
52
A2
77
N2
3
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
J2
H10
48
A5
A4
72
23
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Notes
15. Balls that are NC (No Connect) are preset LOW.
16. Bit# 89 is preset HIGH.
Document Number: 001-66676 Rev. *G
Page 19 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Operating Range
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient
Temperature
Range
Commercial
0 °C to +70 °C
–40 °C to +85 °C
VDD
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Industrial
Supply voltage on VDD relative to GND .......–0.3 V to +4.6 V
Neutron Soft Error Immunity
Supply voltage on VDDQ relative to GND ...... –0.3 V to +VDD
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Parameter
Description
VDDQ
Test
Conditions Typ Max* Unit
LSBU (Device Logical
without ECC) Single-Bit
LSBU (Device Upsets
25 °C
LMBU (All
Devices)
Logical
Multi-Bit
Upsets
SEL (All
Devices)
Single Event
Latch up
–2 V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-66676 Rev. *G
Page 20 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
IDD
ISB1
ISB2
ISB3
ISB4
Description
VDD operating supply current
Test Conditions
Min
Max
Unit
mA
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
–
220
× 36
–
240
6-ns cycle,
167 MHz
× 36
–
190
mA
VDD = Max,
device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
–
85
mA
× 36
–
90
6-ns cycle,
167 MHz
× 36
–
90
mA
Automatic CE power-down
current – CMOS inputs
VDD = Max,
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f=0
All speeds
× 18
–
75
mA
× 36
–
80
Automatic CE power-down
current – CMOS inputs
VDD = Max,
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
–
85
6-ns cycle,
167 MHz
× 36
–
90
mA
VDD = Max,
device deselected,
VIN VIH or VIN VIL,
f=0
All speeds
×18
–
75
mA
× 36
–
80
Automatic CE power-down
current – TTL inputs
Automatic CE Power-down
Current – TTL Inputs
Document Number: 001-66676 Rev. *G
× 36
mA
90
Page 21 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Capacitance
Parameter [19]
Description
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
5
5
pF
5
5
pF
5
5
pF
Thermal Resistance
Parameter [19]
JA
Description
Test
conditions With Still Air (0 m/s)
follow standard test
With Air Flow (1 m/s)
methods
and
procedures
for With Air Flow (3 m/s)
measuring thermal
–
impedance,
per
EIA/JESD51.
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
JB
Thermal resistance
(junction to board)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
35.36
14.24
°C/W
31.30
12.47
°C/W
28.86
11.40
°C/W
7.52
3.92
°C/W
28.89
7.19
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317
Z0 = 50
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
GND
R = 351
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1ns
2 V/ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538
(b)
10%
90%
10%
90%
1ns
2 V/ns
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66676 Rev. *G
Page 22 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Switching Characteristics
Over the Operating Range
Parameter [20, 21]
tPOWER
Description
VDD(Typical) to the first access[22]
–250
–167
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
6
–
ns
tCH
Clock HIGH
1.5
–
2.4
–
ns
tCL
Clock LOW
1.5
–
2.4
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.5
–
3.4
ns
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
ns
Z[23, 24, 25]
tCLZ
Clock to low
1.0
–
1.5
–
ns
tCHZ
Clock to high Z[23, 24, 25]
–
2.6
–
3.4
ns
tOEV
OE LOW to output valid
–
2.6
–
3.4
ns
0
–
0
–
ns
–
2.6
–
3.4
ns
tOELZ
tOEHZ
OE LOW to output low
Z[23, 24, 25]
OE HIGH to output high
Z[23, 24, 25]
Set-up Times
tAS
Address set-up before CLK rise
1.2
–
1.5
–
ns
tADS
ADSC, ADSP set-up before CLK rise
1.2
–
1.5
–
ns
tADVS
ADV set-up before CLK rise
1.2
–
1.5
–
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
–
1.5
–
ns
tDS
Data input set-up before CLK rise
1.2
–
1.5
–
ns
tCES
Chip enable set-up before CLK rise
1.2
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.3
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.3
–
0.5
–
ns
Hold Times
Notes
20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 3 on page 22. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-66676 Rev. *G
Page 23 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Switching Waveforms
Figure 4. Read Cycle Timing [26]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-66676 Rev. *G
Page 24 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Switching Waveforms (continued)
Figure 5. Write Cycle Timing [27, 28]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-66676 Rev. *G
Page 25 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Switching Waveforms (continued)
Figure 6. Read/Write Cycle Timing [29, 30, 31]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
tOEHZ
D(A3)
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
30. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
31. GW is HIGH.
Document Number: 001-66676 Rev. *G
Page 26 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [32, 33]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
33. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-66676 Rev. *G
Page 27 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed (MHz)
250
167
Ordering Code
Package Diagram
Part and Package Type
Operating Range
CY7C1440KV33-250AXC
51-85050
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1440KV33-250BZXI
51-85195
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Industrial
CY7C1442KV33-250AXC
51-85050
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1440KV33-167AXC
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1440KVE33-167AXC
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C
14XX KV E
33 - XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 250 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: KV = 65 nm
Part Identifier: 14XX = 1440 or 1442
1440 = SCD, 1M × 36 (36-Mbit)
1442 = SCD, 2M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66676 Rev. *G
Page 28 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-66676 Rev. *G
Page 29 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195
51-85195 *D
Document Number: 001-66676 Rev. *G
Page 30 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 3. Units of Measure
CE
Chip Enable
CEN
Clock Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
FBGA
Fine-Pitch Ball Grid Array
µA
microampere
I/O
Input/Output
mA
milliampere
JTAG
Joint Test Action Group
mm
millimeter
NoBL
No Bus Latency
ms
millisecond
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory
%
percent
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
WE
Write Enable
ECC
Error Correcting Code
Document Number: 001-66676 Rev. *G
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 31 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Document History Page
Document Title: CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33, 36-Mbit (1M × 36/2M × 18) Pipelined Sync SRAM (With
ECC)
Document Number: 001-66676
Rev.
ECN
Issue Date
Orig. of
Change
*E
4680535
04/10/2015
PRIT
*F
4757974
05/07/2015
DEVM
*G
5338013
07/05/2016
PRIT
Document Number: 001-66676 Rev. *G
Description of Change
Changed status from Preliminary to Final.
Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
Updated Truth Table.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
Updated to new template.
Page 32 of 33
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66676 Rev. *G
Revised July 5, 2016
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
Page 33 of 33
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