CY7C1444KV33
CY7C1445KV33
36-Mbit (1M × 36/2M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades is 250 MHz
■
Registered inputs and outputs for pipelined operation
■
Optimal for performance (double-cycle deselect)
■
Depth expansion without wait state
■
3.3-V core power supply
■
2.5-V or 3.3-V I/O power supply
■
Fast clock-to-output times
❐ 2.5 ns (for 250-MHz device)
The CY7C1444KV33/CY7C1445KV33 SRAMs integrate
1M × 36/2M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock (CLK) input. The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth-expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting interleaved or linear
burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
CY7C1444KV33,
CY7C1445KV33
available
JEDEC-standard Pb-free 100-pin TQFP packages
■
“ZZ” sleep mode option
in
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444KV33/CY7C1445KV33 SRAMs operate from a
+3.3 V core power supply while all outputs operate with a +3.3 V
or a +2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description
250 MHz
Unit
2.5
ns
× 18
220
mA
× 36
240
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-66678 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2016
CY7C1444KV33
CY7C1445KV33
Logic Block Diagram – CY7C1444KV33
ADDRESS
REGISTER
A0,A1,A
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWD
DQD,DQPD
BYTE
WRITE REGISTER
DQD,DQPD
BYTE
WRITE DRIVER
BWC
DQc,DQPC
BYTE
WRITE REGISTER
DQc,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE DRIVER
BWB
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
E
DQA,DQPA
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE REGISTER
BWA
BWE
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
ZZ
CONTROL
Logic Block Diagram – CY7C1445KV33
ADDRESS
REGISTER
A0, A1, A
2
MODE
ADV
CLK
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB , DQPB
BYTE
WRITE DRIVER
DQB, DQPB
BYTE
WRITE REGISTER
BWB
DQA, DQPA
BYTE
WRITE DRIVER
DQA , DQPA
BYTE
WRITE REGISTER
BWA
BWE
GW
ENABLE
REGISTER
CE1
CE2
CE3
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs,
DQPA
DQPB
E
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 001-66678 Rev. *G
Page 2 of 22
CY7C1444KV33
CY7C1445KV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Document Number: 001-66678 Rev. *G
Capacitance .................................................................... 12
Thermal Resistance ........................................................ 12
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 3 of 22
CY7C1444KV33
CY7C1445KV33
Pin Configurations
NC
NC
NC
CY7C1445KV33
(2M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1444KV33
(1M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP Pinout
Document Number: 001-66678 Rev. *G
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
Page 4 of 22
CY7C1444KV33
CY7C1445KV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-synchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter..
BWA, BWB, BWC, BWD
Input-synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (all bytes are written, regardless of the values on BWX
and BWE).
BWE
Input-synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
Input-synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
Output enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins
Input-asynchronous
are tristated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Input-synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
Input-asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
ADSP
DQs, DQPs
I/O-synchronous
VDD
Power supply
VSS
Ground
VSSQ
I/O ground
Document Number: 001-66678 Rev. *G
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Page 5 of 22
CY7C1444KV33
CY7C1445KV33
Pin Definitions (continued)
Name
I/O
VDDQ
I/O power supply
MODE
Input-static
Description
Power supply for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode pin has an internal pull-up.
NC
–
No Connects. Not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M, and 1G
are address expansion pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1444KV33/CY7C1445KV33 support secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium
processors. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tristate control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The CY7C1444KV33/CY7C1445KV33 are double-cycle
deselect part. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tristate immediately after the next clock rise.
Document Number: 001-66678 Rev. *G
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BWX) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals. The CY7C1444KV33/CY7C1445KV33 provide byte
write capability that is described in the Write Cycle Description
table. Asserting the byte write enable input (BWE) with the
selected byte write input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1444KV33/CY7C1445KV33 are common I/O
devices, the output enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tristate the
output drivers. As a safety precaution, DQ are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BWX) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Page 6 of 22
CY7C1444KV33
CY7C1445KV33
Because the CY7C1444KV33/CY7C1445KV33 are common I/O
devices, the output enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so will tristate
the output drivers. As a safety precaution, DQX are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Burst Sequences
00
01
10
11
The CY7C1444KV33/CY7C1445KV33 provide a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The burst sequence is user selectable through the
MODE input. Both read and write burst operations are
supported.
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1: A0
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Linear Burst Address Table
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ inactive to exit sleep current
Document Number: 001-66678 Rev. *G
Min
Max
Unit
–
75
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 7 of 22
CY7C1444KV33
CY7C1445KV33
Truth Table
The Truth Table for CY7C1444KV33/CY7C1445KV33 is as follows. [1, 2, 3, 4, 5, 6]
Operation
Add. Used
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-66678 Rev. *G
Page 8 of 22
CY7C1444KV33
CY7C1445KV33
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1444KV33 is as follows [7, 8].
Function (CY7C1444KV33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1445KV33 is as follows [7, 8].
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Function (CY7C1445KV33)
Notes
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document Number: 001-66678 Rev. *G
Page 9 of 22
CY7C1444KV33
CY7C1445KV33
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0 °C to +70 °C
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on
VDD relative to GND ....................................–0.5 V to +4.6 V
Supply voltage on
VDDQ relative to GND ................................... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ
Max*
Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
–2 V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-66678 Rev. *G
Page 10 of 22
CY7C1444KV33
CY7C1445KV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [9, 10]
IDD
ISB1
ISB2
ISB3
ISB4
Description
VDD operating supply current
Test Conditions
Min
Max
Unit
mA
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
–
220
× 36
–
240
Automatic CE power-down
current – TTL inputs
VDD = Max,
device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
–
85
× 36
–
90
Automatic CE power-down
current – CMOS inputs
VDD = Max,
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f=0
4-ns cycle,
250 MHz
× 18
–
75
Automatic CE power-down
current – CMOS inputs
VDD = Max,
device deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
Automatic CE power-down
current – TTL inputs
VDD = Max,
device deselected,
VIN VIH or VIN VIL,
f=0
4-ns cycle,
250 MHz
×18
–
75
×36
–
80
Document Number: 001-66678 Rev. *G
× 36
mA
mA
80
–
× 36
85
mA
90
mA
Page 11 of 22
CY7C1444KV33
CY7C1445KV33
Capacitance
Parameter [11]
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test With Still Air (0 m/s)
methods and procedures for
With Air Flow (1 m/s)
measuring thermal impedance, per
EIA/JESD51.
With Air Flow (3 m/s)
35.36
°C/W
31.30
°C/W
Description
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
Thermal Resistance
Parameter [11]
JA
Description
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
JB
Thermal resistance
(junction to board)
–
28.86
°C/W
7.52
°C/W
28.89
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
10%
5 pF
R = 351
90%
10%
90%
GND
2 V/ns
1 ns
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
2 V/ns
(c)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66678 Rev. *G
Page 12 of 22
CY7C1444KV33
CY7C1445KV33
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
tPOWER
Description
VDD(Typical) to the first access[14]
-250
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
ns
tCH
Clock HIGH
1.5
–
ns
tCL
Clock LOW
1.5
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.5
ns
tDOH
Data output hold after CLK rise
1.0
–
ns
Z[15, 16, 17]
tCLZ
Clock to low
1.0
–
ns
tCHZ
Clock to high Z[15, 16, 17]
–
2.6
ns
tOEV
OE LOW to output valid
–
2.6
ns
0
–
ns
–
2.6
ns
tOELZ
tOEHZ
OE LOW to output low
Z[15, 16, 17]
OE HIGH to output high
Z[15, 16, 17]
Set-up Times
tAS
Address set-up before CLK rise
1.2
–
ns
tADS
ADSC, ADSP set-up before CLK rise
1.2
–
ns
tADVS
ADV set-up before CLK rise
1.2
–
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
–
ns
tDS
Data input set-up before CLK rise
1.2
–
ns
tCES
Chip Enable set-up before CLK rise
1.2
–
ns
tAH
Address hold after CLK rise
0.3
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
ns
tADVH
ADV hold after CLK rise
0.3
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
ns
tDH
Data input hold after CLK rise
0.3
–
ns
tCEH
Chip Enable hold after CLK rise
0.3
–
ns
Hold Times
Notes
12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
13. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document Number: 001-66678 Rev. *G
Page 13 of 22
CY7C1444KV33
CY7C1445KV33
Switching Waveforms
Figure 3. Read Cycle Timing [18]
tCYC
CLK
tCH
tCL
tADS tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
A3
Burst continued with
new base address
tWES tWEH
GW, BWE,BW
X
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-66678 Rev. *G
Page 14 of 22
CY7C1444KV33
CY7C1445KV33
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [19, 20]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
t
DS DH
Data in (D)
High-Z
t
OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-66678 Rev. *G
Page 15 of 22
CY7C1444KV33
CY7C1445KV33
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [21, 22, 23]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
Data In (D)
tOELZ
High-Z
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
BURST READ
Single WRITE
DON’T CARE
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Document Number: 001-66678 Rev. *G
Page 16 of 22
CY7C1444KV33
CY7C1445KV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [24, 25]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
25. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-66678 Rev. *G
Page 17 of 22
CY7C1444KV33
CY7C1445KV33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed (MHz)
250
Ordering Code
Package Diagram
CY7C1444KV33-250AXC
51-85050
Part and Package Type
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating Range
Commercial
CY7C1445KV33-250AXC
Ordering Code Definitions
CY
7
C
14XX K V33 - 250
A
X
C
Temperature range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 250 MHz
V33 = 3.3 V
Process Technology: K =65 nm
1444 = DCD, 1Mb × 36 (36Mb); 1445 = DCD, 2Mb × 18(36Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66678 Rev. *G
Page 18 of 22
CY7C1444KV33
CY7C1445KV33
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-66678 Rev. *G
Page 19 of 22
CY7C1444KV33
CY7C1445KV33
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 3. Units of Measure
CE
Chip Enable
I/O
Input/Output
°C
degree Celsius
NoBL
No Bus Latency
MHz
megahertz
OE
Output Enable
µA
microampere
SRAM
Static Random Access Memory
mA
milliampere
TQFP
Thin Quad Flat Pack
ms
millisecond
WE
Write Enable
ns
nanosecond
Document Number: 001-66678 Rev. *G
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 20 of 22
CY7C1444KV33
CY7C1445KV33
Document History Page
Document Title: CY7C1444KV33/CY7C1445KV33, 36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM
Document Number: 001-66678
Rev.
ECN No.
Submission
Date
Orig. of
Change
*E
4680529
04/09/2015
PRIT
*F
4757974
05/07/2015
DEVM
*G
5337537
07/05/2016
PRIT
Document Number: 001-66678 Rev. *G
Description of Change
Changed status from Preliminary to Final.
Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU parameter.
Updated to new template.
Page 21 of 22
CY7C1444KV33
CY7C1445KV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66678 Rev. *G
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation.
Revised July 5, 2016
Page 22 of 22
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