CY7C144AV

CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 8K/16K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3V 8K/16K x 8 Dual-Port Static RAM Features ■ ■ ■ ■ ■ True dual-ported memory cells which allow simultaneous access of the same memory location 8K/16K x 8 organizations (CY7C144AV/006AV) 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power High-speed access: 25 ns Low operating power — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 A (typical) ■ ■ ■ ■ ■ ■ ■ ■ Expandable data bus to 16 bits or more using Master/ Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flag for port-to-port communication Pin select for Master or Slave Commercial and industrial temperature ranges Available in 64-pin thin quad flat pack (TQFP) (7C006AV & 7C144AV) Pb-free packages available ■ ■ Fully asynchronous operation Automatic power-down Logic Block Diagram R/WL CEL OEL R/WR CER OER I/O0L–I/O7L [1] 8 8 [1] I/O Control I/O Control I/O0R–I/O7R A0L–A12–13L [2] 13–14 Address Decode 13–14 True Dual-Ported RAM Array Address Decode 13–14 13–14 A0R–A12–13R [2] A0L–A12–13L CEL OEL R/WL SEML BUSYL INTL [3] [2] Interrupt Semaphore Arbitration A0R–A12–13R CER OER R/WR SEMR [3] [2] BUSYR INTR M/S Notes 1. I/O0–I/O7 for x8 devices 2. A0–A12 for 8K devices; A0–A13 for 16K devices 3. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06051 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 4, 2011 [+] Feedback CY7C144AV CY7C006AV Contents Pin Definitions .................................................................. 4 Architecture ...................................................................... 5 Functional Description ..................................................... 5 Read and Write Operations ......................................... 5 Interrupts ..................................................................... 5 Busy ............................................................................ 5 Master/Slave ............................................................... 5 Semaphore Operation ................................................. 5 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 Electrical Characteristics ................................................. 7 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 8 Switching Characteristics ................................................ 8 Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Switching Waveforms .................................................... 11 Ordering Information ...................................................... 18 Ordering Code Definition ........................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC Solutions ......................................................... 21 Document #: 38-06051 Rev. *E Page 2 of 21 [+] Feedback CY7C144AV CY7C006AV Pin Configurations 64-Pin TQFP Top View SEML R/WL I/O1L I/O0L A12L A11L A10L OEL CEL NC VCC A9L A8L 52 A7L A6L A5L 49 64 63 62 61 60 59 58 57 56 55 54 53 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R 51 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R CY7C144AV (8K x 8) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A7R R/WR SEMR CER NC I/O6R GND A9R A8R OER A12R Document #: 38-06051 Rev. *E I/O7R A11R A10R A6R A5R 32 16 Page 3 of 21 [+] Feedback CY7C144AV CY7C006AV Pin Configurations (continued) 64-Pin TQFP Top View SEML R/WL I/O1L I/O0L CEL A13L A12L A11L A10L OEL VCC A9L A8L 52 A7L A6L A5L 49 64 63 62 61 60 59 58 57 56 55 54 53 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R 51 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R CY7C006AV (16K x 8) 41 40 39 38 37 36 35 34 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A7R R/WR SEMR CER A13R I/O6R GND A9R A8R OER A12R Selection Guide CY7C144AV CY7C006AV -25 Maximum access time (ns) Typical operating current (mA) Typical standby current for ISB1 (mA) (Both ports TTL level) Typical standby current for ISB3 (A) (Both ports CMOS level) 25 115 30 10 A Pin Definitions Left Port CEL R/WL OEL A0L–A12/13L I/O0L–I/O7L SEML INTL BUSYL M/S VCC GND NC Right Port CER R/WR OER A0R–A12/13R I/O0R–I/O7R SEMR INTR BUSYR Chip enable Read/Write enable Output enable Address (A0–A12 for 8K devices; A0–A13 for 16K devices) Data bus input/output (I/O0–I/O7 for x8 devices) Semaphore Enable Interrupt flag Busy flag Master or Slave select Power Ground No connect Page 4 of 21 Description Document #: 38-06051 Rev. *E I/O7R A11R A10R A6R A5R 32 16 33 [+] Feedback CY7C144AV CY7C006AV Architecture The CY7C144AV and CY7C006AV and consist of an array of 8K and 16K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the device can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The device also has an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (1FFF for the CY7C144AV and 3FFF for the CY7C006AV) is the mailbox for the right port and the second-highest memory location (1FFE for the CY7C144AV and 3FFE for the CY7C006AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Functional Description The CY7C144AV and CY7C006AV are low-power CMOS 8K/16K x 8 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. Busy The CY7C144AV and CY7C006AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Read and Write Operations When writing data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is Document #: 38-06051 Rev. *E Semaphore Operation The CY7C144AV and CY7C006AV provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and Page 5 of 21 [+] Feedback CY7C144AV CY7C006AV continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Document #: 38-06051 Rev. *E Page 6 of 21 [+] Feedback CY7C144AV CY7C006AV Maximum Ratings[4] (Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Storage temperature ................................ –65 C to +150 C Ambient temperature with Power applied........................................... –55 C to +125 C Supply voltage to ground potential ...............–0.5 V to +4.6 V DC voltage applied to Outputs in High Z state .......................... –0.5 V to VCC+0.5 V DC input voltage ................................. –0.5 V to VCC+0.5 V [5] . Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... >2001 V Latch-up current ..................................................... >200 mA Operating Range Range Commercial Industrial[12] Ambient Temperature 0 C to +70 C –40 C to +85 C VCC 3.3 V  300 mV 3.3 V  300 mV Electrical Characteristics Over the Operating Range CY7C144AV CY7C006AV Parameter Description Min VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Output HIGH voltage (VCC = 3.3 V) Output LOW voltage Input HIGH voltage Input LOW voltage Output leakage current Operating current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby current (Both p TTL level) CEL & CER  VIH, f = fMAX[6] Standby current (One port TTL level) CEL | CER  VIH, f = fMAX[6] Standby current (Both ports CMOS level) CEL & CER  VCC – 0.2 V, f = 0[6] Standby current (One port CMOS level) CEL | CER  VIH, f = fMAX[6] [7] -25 Typ – 0.4 2.0 –10 Com’l Ind Com’l Ind Com’l Ind Com’l Ind Com’l Ind 60 – 10 – 80 65 – 500 30 – 95 115 – 40 – 0.8 10 165 Max 2.4 Unit V V V V A mA mA mA mA mA mA A A mA mA Capacitance CIN COUT Parameter Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 10 10 Unit pF pF Notes 4. The Voltage on any input or I/O pin can not exceed the power pin during power-up. 5. Pulse width < 20 ns. 6. fMAX = 1/tRC. All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06051 Rev. *E Page 7 of 21 [+] Feedback CY7C144AV CY7C006AV AC Test Loads and Waveforms 3.3 V R1 = 590  OUTPUT C = 30 pF R2 = 435  OUTPUT C = 30 pF VTH = 1.4 V RTH = 250 OUTPUT C = 5 pF R2 = 435  3.3 V R1 = 590  (a) Normal Load (Load 1) 3.0V GND (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 10%  3 ns 90% 90% 10%  3 ns (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE & tLZWE including scope and jig) Switching Characteristics Over the Operating Range[8] Parameter Description Min READ CYCLE tRC tAA tOHA tACE[9] tDOE tLZOE [10, 11, 12] . CY7C144AV CY7C006AV -25 Max – 25 – 25 13 – 15 – 15 – 25 – – – – – – – Unit Read cycle time Address to data valid Output hold from address change CE LOW to data valid OE LOW to data valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to power-up CE HIGH to power-down Write cycle time CE LOW to write end Address valid to write end Address hold from write end Address set-up to write start Write pulse width Data set-up to write end 25 – 3 – – 3 – 3 – 0 – 25 20 20 0 0 20 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tHZOE[10, 11, 12] tLZCE[10, 11, 12] tHZCE[10, 11, 12] tPU[12] tPD[12] WRITE CYCLE tWC tSCE[9] tAW tHA tSA[9] tPWE tSD Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 9. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 11. Test conditions used are Load 3. 12. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06051 Rev. *E Page 8 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Characteristics Over the Operating Range[8] (continued) Parameter Description Min tHD tHZWE[13, 14] tLZWE[13, 14] tWDD[15] tDDD[15] BUSY TIMING tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[17] tINS tINR tSOP tSWRD tSPS tSAA [16] CY7C144AV CY7C006AV -25 Max 0 – 3 – – – – – – 5 0 17 – – – 12 5 5 – 15 – 50 35 20 20 20 17 – – – 25 20 20 – – – 25 Unit Data hold from write end R/W LOW to High Z R/W HIGH to Low Z Write pulse to data delay Write data valid to read data valid BUSY LOW from address match BUSY HIGH from address mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port set-up for priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to data valid INT set time INT reset time SEM flag update pulse (OE or SEM) SEM flag write to read time SEM flag contention window SEM address access time ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns INTERRUPT TIMING[16] SEMAPHORE TIMING Notes 13. Test conditions used are Load 3. 14. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. Test conditions used are Load 2. 17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document #: 38-06051 Rev. *E Page 9 of 21 [+] Feedback CY7C144AV CY7C006AV Data Retention Mode The CY7C144AV and CY7C006AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts). Timing Data Retention Mode VCC 3.0 V VCC 2.0 V 3.0 V tRC V IH CE VCC to VCC – 0.2 V Parameter ICCDR1 Test Conditions[18] @ VCCDR = 2 V Max 50 Unit A Notes 18. CE = VCC, Vin = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested. Document #: 38-06051 Rev. *E Page 10 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms Figure 1. Read Cycle No. 1 Either Port Address Access[19, 20, 21] tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA PREVIOUS DATA VALID Figure 2. Read Cycle No. 2 Either Port CE/OE Access[19, 22, 23] CE tACE tDOE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tHZCE tHZOE OE Figure 3. Read Cycle No. 3 Either Port[19, 21, 22, 23] tRC ADDRESS tAA tOHA tLZCE tABE CE tACE tLZCE DATA OUT tHZCE Notes 19. R/W is HIGH for read cycles. 20. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 21. OE = VIL. 22. Address valid prior to or coincident with CE transition LOW. 23. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document #: 38-06051 Rev. *E Page 11 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms (continued) Figure 4. Write Cycle No. 1: R/W Controlled Timing[24, 25, 26, 27] tWC ADDRESS tHZOE [28] OE tAW CE [29] tSA R/W tHZWE[28] DATA OUT Note 30 tPWE[27] tHA tLZWE Note 30 tSD tHD DATA IN Figure 5. Write Cycle No. 2: CE Controlled Timing[24, 25, 26, 31] tWC ADDRESS tAW CE [29] tSA R/W tSCE tHA tSD DATA IN tHD Notes 24. R/W must be HIGH during all address transitions. 25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 28. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 29. To access RAM, CE = VIL, SEM = VIH. 30. During this period, the I/O pins are in the output state, and input signals must not be applied. 31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06051 Rev. *E Page 12 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms (continued) Figure 6. Semaphore Read After Write Timing, Either Side[32] tSAA A 0–A 2 VALID ADRESS tAW SEM tSCE tSD I/O 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATAIN VALID tPWE tHD DATAOUT VALID tHA tSOP VALID ADRESS tACE tOHA Figure 7. Timing Diagram of Semaphore Contention[33, 34, 35] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 32. CE = HIGH for the duration of the above timing (both write and read cycle). 33. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 34. Semaphores are reset (available to both ports) at cycle start. 35. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document #: 38-06051 Rev. *E Page 13 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms (continued) Figure 8. Timing Diagram of Read with BUSY (M/S=HIGH)[36] tWC ADDRESSR R/WR MATCH tPWE tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATA OUTL tWDD VALID VALID tHD tBHA tBDD Figure 9. Write Timing with Busy Input (M/S=LOW) R/W tWB tPWE BUSY tWH Note 36. CEL = CER = LOW. Document #: 38-06051 Rev. *E Page 14 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms (continued) Figure 10. Busy Timing Diagrfam No.1 (CE Arbitration)[37] CELValid First: ADDRESS L,R CEL tPS ADDRESS MATCH CER tBLC BUSYR tBHC CER Valid First: ADDRESS L,R CER tPS ADDRESS MATCH CE L tBLC BUSY L tBHC Figure 11. Busy Timing Diagram No.2 (Address Arbitration)[37] Left Address Valid First tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L tBHA ADDRESS MISMATCH Note 37. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document #: 38-06051 Rev. *E Page 15 of 21 [+] Feedback CY7C144AV CY7C006AV Switching Waveforms (continued) Figure 12. Interrupt Timing Diagrams Left Side Sets INTR : ADDRESSL CE L R/W L INT R tINS [39] tWC WRITE 1FFF/3FFF (See Functional Description) tHA[38] Right Side Clears INT R : ADDRESSR CE R tINR [39] R/WR OE R INTR tRC READ 1FFF/3FFF (See Functional Description) Right Side Sets INT L: tWC ADDRESSR CE R R/W R INT L tINS[39] WRITE 1FFE/3FFE (See Functional Description) tHA[38] Left Side Clears INT L: ADDRESSR CE L tINR[39] R/W L OE L INT L Notes 38. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 39. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. tRC (See Functional Description) READ 1FFE/3FFE Document #: 38-06051 Rev. *E Page 16 of 21 [+] Feedback CY7C144AV CY7C006AV Table 1. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L Outputs I/O0–I/O7 High Z Data out High Z Data in Data out Data in Deselected: Power-down Read data in semaphore flag I/O lines disabled Write into semaphore flag Read Write Not allowed Operation Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) Left Port Function Set Right INTR flag Reset Right INTR flag Set Left INTL flag Reset Left INTL flag R/WL L X X X CEL L X X L OEL X X X L A0L–13L 1FFF/3FFF[40] X X 1FFE/3FFE[40] INTL X X L[42] H[41] R/WR X X L X CER X L L X Right Port OER X L X X A0R–13R X 1FFF/3FFF[40] 1FFE/3FFE[40] X INTR L[41] H[42] X X Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0–I/O7 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0–I/O7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status Notes 40. See Functional Description for specific addresses by device part number. 41. If BUSYL = L, then no change. 42. If BUSYR = L, then no change. Document #: 38-06051 Rev. *E Page 17 of 21 [+] Feedback CY7C144AV CY7C006AV Ordering Information 8K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 25 Ordering Code CY7C144AV–25AC CY7C144AV-25AXC Package Name A65 A65 Package Type 64-Pin Thin Quad Flat Pack 64-Pin Pb-free Thin Quad Flat Pack Operating Range Commercial 16K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 25 Ordering Code CY7C006AV-25AXC Package Name A65 Package Type 64-Pin Pb-free Thin Quad Flat Pack Operating Range Commercial Ordering Code Definition CY 7C XXX XX XX A XX Operating Range: C = Commercial X:Pb-free (RoHS compliant) Package: TQFP Speed grade: 25ns V/AV : 3.3 V Part Identifier Dual port SRAM Company Id: CY=Cypress Document #: 38-06051 Rev. *E Page 18 of 21 [+] Feedback CY7C144AV CY7C006AV Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack (14 x 14 x 1.4mm) A65 51-85046 *E Acronyms Acronym CMOS I/O SRAM TQFP input/output static random access memory Thin Quad Flat Pack Description complementary metal oxide semiconductor Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06051 Rev. *E Page 19 of 21 [+] Feedback CY7C144AV CY7C006AV Document History Page Document Title: CY7C144AV/CY7C006AV 3.3V 8K/16K x 8 Dual-Port Static RAM Document Number: 38-06051 REV. ** *A *B *C ECN NO. 110203 122301 237623 373615 Issue Date 12/02/01 12/27/02 See ECN See ECN Orig. of Change SZV RBI YDT PCX Description of Change Change from Spec number: 38-00837 to 38-06051 Power up requirements added to Maximum Ratings Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C144AV-25AXC, CY7C144AV-25JXC, CY7C006AV-25AXC Updated Ordering Information Updated Package Diagrams Removed CY7C145AV-20JC Removed information for parts: CY7C138AV, CY7C139AV, CY7C145AV ,CY7C016AV,CY7C007AV, CY7C017AV Updated package diagram *D *E 2896210 3161515 03/22/2010 02/04/2011 RAME ADMU Document #: 38-06051 Rev. *E Page 20 of 21 [+] Feedback CY7C144AV CY7C006AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06051 Rev. *E Revised February 4, 2011 Page 21 of 21 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback