CY7C144E
8K × 8 Dual-Port Static RAM
with SEM, INT, BUSY
8K × 8 Dual-Port Static RAM with SEM, INT, BUSY
Features
Functional Description
■
True dual-ported memory cells that enable simultaneous reads
of the same memory location
■
8K × 8 organization (CY7C144E)
■
0.35-micron CMOS for optimum speed and power
■
High-speed access: 15 ns
■
Low operating power: ICC = 180 mA (typical),
standby ISB3 = 0.05 mA (typical)
■
Fully asynchronous operation
■
Automatic power-down
■
TTL compatible
■
Master / slave select pin enables bus width expansion to 16-bits
or more
■
Busy arbitration scheme provided
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Available in 68-pin PLCC and 64-pin TQFP
■
Pb-free packages available
The CY7C144E is a high speed CMOS 8K × 8 dual port static
RAM. Various arbitration schemes are included on the
CY7C144E to handle situations when multiple processors
access the same piece of data. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. The CY7C144E can be used as a
standalone 64-Kbit dual-port static RAM or multiple devices can
be combined in order to function as a 16-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video / graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
For a complete list of related documentation, click here.
Logic Block Diagram
R/W L
R/W R
CE L
OE L
CE R
OE R
I/O7L
I/O
CONTROL
I/O0L
I/O 7R
I/O
CONTROL
I/O 0R
BUSYL[1, 2]
BUSY R [1, 2]
A 12L
A 12R
ADDRESS
DECODER
A 0L
CEL
OEL
MEMORY
ARRAY
ADDRESS
DECODER
INTERRUPT
SEMAPHORE
ARBITRATION
R/W L
A 0R
CE R
OE R
R/W R
SEMR
INTR [2]
SEM L
INT L [2]
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document Number: 001-63982 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2017
CY7C144E
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Architecture ...................................................................... 4
Functional Overview ........................................................ 5
Write Operation ........................................................... 5
Read Operation ........................................................... 5
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 6
Semaphore Operation ................................................. 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 8
AC Test Loads and Waveforms ....................................... 8
Document Number: 001-63982 Rev. *D
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Typical DC and AC Characteristics .............................. 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 2 of 23
CY7C144E
Selection Guide
Description
7C144E-15
7C144E-25
7C144E-55
Unit
Maximum access time
15
25
55
ns
Typical operating current
190
180
180
mA
Typical Standby Current for ISB1
(both ports TTL level)
50
45
45
mA
Typical Standby Current for ISB3
(both ports CMOS level)
0.05
0.05
0.05
mA
Pin Configuration
A 1 1L
A 1 0L
A9 L
A8 L
A7 L
A6 L
A5 L
55
54
53
52
51
50
49
NC
58
V CC
CE L
59
26
27
28
29
30
A1 1 R
A1 0 R
A9 R
A8 R
A7 R
32
25
A1 2 R
31
24
A 1L
A 0L
INTL
BUSYL
GND
M/S
BUSYR
38
37
INTR
A 0R
36
35
34
A 1R
A 2R
A 3R
33
A 4R
A5 R
A6 R
R/ WR
SE MR
A3R
A4R
O ER
A8R
A7R
A6R
A5R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
G ND
IO 5R
A2R
23
A1R
46
45
44
A 3L
A 2L
40
39
NC
47
24
25
26
CY7C144E
8
9
10
11
12
13
14
15
16
A 4L
47
46
45
42
41
22
VCC
IO 3R
IO 4R
IO 2R
6
7
CE R
22
23
INTR
A0R
R/WR
SEM
R
CER
NC
NC
GND
A12R
A11R
A10R
A9R
A 12L
S E ML
60
21
49
48
VCC
GND
IO 0R
IO 1R
48
44
43
21
M/S
BUSYR
NC
OER
56
R/ W L
61
51
50
IO 7R
57
O EL
62
19
20
4
5
20
BUSYL
GND
IO 5L
GND
IO 6L
IO 7L
19
53
52
CY7C144E
2
3
18
A0L
INTL
17
18
0L
IO
A9L
A8L
A7L
A6L
55
54
1
IO 3L
IO 4L
17
IO 3R
IO 4R
IO 5R
IO 6R
15
16
A3L
A2L
A1L
IO 2L
7R
VCC
GND
IO 0R
IO 1R
IO 2R
VCC
A5L
A4L
6R
GND
IO 6L
IO 7L
60
59
58
57
56
IO
IO 4L
IO 5L
5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
IO
9 8 7 6
IO 2L
IO 3L
NC
NC
VCC
A12 L
A1 1L
A1 0L
IO 1 L
IO 0 L
NC[3]
OE L
R/ WL
SEM
L
CEL
1L
IO
63
Figure 2. 64-pin TQFP pinout (Top View)
64
Figure 1. 68-pin PLCC pinout (Top View)
Note
3. This pin is NC.
Document Number: 001-63982 Rev. *D
Page 3 of 23
CY7C144E
Pin Definitions
Left Port
Right Port
Description
I/O0L-7L
I/O0R-7R
Data bus I/O
A0L-12L
A0R-12R
Address lines
CEL
CER
Chip enable
OEL
OER
Output enable
R/WL
R/WR
Read / write enable
SEML
SEMR
Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant
bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing
to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads location
1FFE. INTR is set when left port writes location 1FFF[4] and is cleared when right port reads location 1FFF[4].
BUSYL
BUSYR
Busy flag
M/S
Master or slave select
VCC
Power
GND
Ground
Architecture
The CY7C144E consists of a an array of 8K words of 8 bits each
of dual-port RAM cells, I/O, address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads/writes to any location in memory. To handle
simultaneous writes or reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be used
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the CY7C144E can function as a Master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The CY7C144E has an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Note
4. 8K x 8 (CY7C144E): 1FFE(left port) and 1FFF(right port).
Document Number: 001-63982 Rev. *D
Page 4 of 23
CY7C144E
Functional Overview
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R / W to guarantee a valid write. A write operation is controlled
by either the OE pin (see Figure 7 on page 12) or the R/W pin
(see Figure 8 on page 12). Data can be written to the device
tHZOE after the OE is deasserted or tHZWE after the falling edge
of R/W. Required inputs for non-contention operations are
summarized in Table 1.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE are
asserted. If the user of the CY7C144E wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE pin.
Table 1. Non-Contending Read/Write
Inputs
CE
Outputs
Operation
R/W
OE
SEM
H
X
X
H
High Z
H
H
L
L
Data out
X
X
H
X
High Z
I/O lines disabled
X
L
Data in
Write to semaphore
H
I/O07
Power-down
Read data in semaphore
L
H
L
H
Data out
Read
L
L
X
H
Data in
Write
L
X
X
L
Illegal condition
Interrupts
(INTL) is accomplished when the right port writes to location
1FFE. This flag is cleared when the left port reads the specified
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See Table 2 for input requirements for INT. INTR and INTL are
push-pull outputs and do not require pull-up resistors to operate.
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right port
reads that same location. Setting the left port’s interrupt flag
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Function
Left Port
R/W
CE
OE
Right Port
A012 (CY7C144E)
INT
R/W
CE
OE
A012 (CY7C144E)
INT
Set left INT
X
X
X
X
L
L
L
X
1FFE
X
Reset left INT
X
L
L
1FFE
H
X
L
L
X
X
Set right INT
L
L
X
1FFF
X
X
X
X
X
L
Reset right INT
X
X
X
X
X
X
L
L
1FFF
H
Busy
The CY7C144E provides on-chip arbitration to alleviate
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other the Busy logic determines which port has access. If
Document Number: 001-63982 Rev. *D
tPS is violated, one port will definitely gain permission to the
location, but it is not guaranteed which one. BUSY will be
asserted tBLA after an address match or tBLC after CE is taken
LOW. BUSYL and BUSYR in master mode are push-pull outputs
and do not require pull-up resistors to operate.
Page 5 of 23
CY7C144E
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This enables the device to interface to a master device with no
external components.Writing of slave devices must be delayed
until after the BUSY input has settled. Otherwise, the slave chip
may begin a write cycle during a contention situation.When
presented a HIGH input, the M/S pin allows the device to be used
as a master and therefore the BUSY line is an output. BUSY can
then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C144E provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shared resource,
otherwise (reads a 1) it assumes the right port has control and
continues to poll the semaphore.When the right side has
relinquished control of the semaphore (by writing a 1), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a 1 is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access.When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a 0 is written
to the left port of an unused semaphore, a 1 appears at the same
semaphore address on the right port. That semaphore can now
only be modified by the side showing 0 (the left port in this case).
If the left port now relinquishes control by writing a 1 to the
semaphore, the semaphore will be set to 1 for both sides.
However, if the right port had requested the semaphore (written
a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it.
Table 3 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore. Initialization of the semaphore is
not automatic and must be reset during initialization program at
power-up. All Semaphores on both sides should have a one
written into them at initialization from both sides to assure that
they are free when needed.
Table 3. Semaphore Operation Example
Function
I/O0-7 Left
I/O0-7 Right
Status
No action
1
1
Semaphore free
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
Document Number: 001-63982 Rev. *D
Page 6 of 23
CY7C144E
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings [5] may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current .................................................... >200 mA
Ambient temperature
with power applied ................................... –55 C to +125 C
Operating Range
Range
Supply voltage to ground potential ..............–0.3 V to +7.0 V
DC input voltage
VCC
0 C to +70 C
5 V 10%
–40 C to +85 C
5 V 10%
Commercial
DC voltage applied to outputs
in High Z state ..............................................–0.5 V to +7.0 V
[6]
Ambient Temperature
Industrial
......................................–0.5 V to +7.0 V
Electrical Characteristics
Over the operating range
Parameter
Description
Test Conditions
VOH
Output HIGH
voltage
VCC = Min, IOH = 4.0 mA
VOL
Output LOW
voltage
VCC = Min, IOL = 4.0 mA
VIH
7C144E-15
7C144E-25
7C144E-55
Min Typ Max Min Typ Max Min Typ Max
Unit
2.4
–
–
2.4
–
–
2.4
–
–
–
0.4
–
–
0.4
–
–
Input HIGH
voltage
2.2
–
–
2.2
–
–
2.2
–
VIL
Input LOW
voltage
–
–
0.8
–
–
0.8
–
–
0.8
V
IIX
Input leakage
current
GND < VI < VCC
10
–
+10 10
–
+10 10
–
+10
A
IOZ
Output leakage
current
Outputs disabled, GND < VO < VCC
10
–
+10 10
–
+10 10
–
+10
A
ICC
Operating current VCC = Max,
IOUT = 0 mA,
Outputs disabled
Commercial
–
190 280
–
180 275
–
180 275 mA
Industrial
–
215 305
–
215 305
–
215 305
Standby current
(Both ports TTL
levels)
CEL and CER > VIH,
f = fMAX[7]
Commercial
–
50
70
–
45
65
–
45
65
Industrial
–
65
95
–
65
95
–
65
95
Standby current
(One port TTL
level)
CEL or CER > VIH,
f = fMAX[7]
Commercial
–
120 180
–
110 160
–
110 160 mA
Industrial
–
135 205
–
135 205
–
135 205
Standby current
(Both ports
CMOS levels)
Both ports,
Commercial
CE and CER > VCC – 0.2 V,
Industrial
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0[7]
–
0.05 0.5
–
0.05 0.5
–
0.05 0.5
–
0.05 0.5
–
0.05 0.5
–
0.05 0.5
–
110 160
–
100 140
–
100 140 mA
–
125 175
–
125 175
–
125 175
ISB1
ISB2
ISB3
ISB4
Standby current One port,
Commercial
(One port CMOS CEL or CER > VCC – 0.2 V,
Industrial
level)
VIN > VCC – 0.2 V or
VIN < 0.2 V,
Active Port outputs,
f = fMAX[7]
V
0.4
V
V
mA
mA
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
Document Number: 001-63982 Rev. *D
Page 7 of 23
CY7C144E
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = 5.0 V
Max
Unit
10
pF
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
5V
R1 = 893
R1 = 893
RTH = 250
OUTPUT
OUTPUT
OUTPUT
C = 30 pF
C = 5 pF
C = 30pF
R2 = 347
R = 347
VTH = 1.4V
(b) Thévenin Equivalent (Load 1)
(a) Normal Load (Load1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPUT
3.0V
C = 30 pF
GND
10%
3 ns
90%
90%
10%
3 ns
Load (Load 2)
Document Number: 001-63982 Rev. *D
Page 8 of 23
CY7C144E
Switching Characteristics
Over the operating range
Parameter [8]
Description
7C144E-15
7C144E-25
7C144E-55
Min
Max
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
15
–
25
–
55
–
ns
tAA
Address to data valid
–
15
–
25
–
55
ns
tOHA
Output hold from address change
3
–
3
–
3
–
ns
tACE
CE LOW to data valid
–
15
–
25
–
55
ns
tDOE
OE LOW to data valid
–
10
–
15
–
25
ns
[9, 10]
OE Low to Low Z
3
–
3
–
3
–
ns
[9, 10]
OE HIGH to High Z
–
10
–
15
–
25
ns
[9, 10]
CE LOW to Low Z
3
–
3
–
3
–
ns
CE HIGH to High Z
–
10
–
15
–
25
ns
tPU
[10]
CE LOW to power-up
0
–
0
–
0
–
ns
tPD
[10]
CE HIGH to power-down
–
15
–
25
–
55
ns
tWC
Write cycle time
15
–
25
–
55
–
ns
tSCE
CE LOW to write end
12
–
20
–
45
–
ns
tAW
Address setup to write end
12
–
20
–
45
–
ns
tHA
Address hold from write end
0
–
2
–
2
–
ns
tSA
Address setup to write start
0
–
0
–
0
–
ns
tPWE
Write pulse width
12
–
20
–
40
–
ns
tSD
Data setup to write end
10
–
15
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE[10]
R/W LOW to High Z
–
10
–
15
–
25
ns
[10]
tLZOE
tHZOE
tLZCE
tHZCE[9, 10]
Write Cycle
tLZWE
R/W HIGH to Low Z
3
–
3
–
3
–
ns
[11]
Write pulse to data delay
–
30
–
50
–
70
ns
[11]
Write data valid to read data valid
–
25
–
30
–
40
ns
tWDD
tDDD
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30-pF load capacitance.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3. This parameter is guaranteed but not tested.
11. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
Document Number: 001-63982 Rev. *D
Page 9 of 23
CY7C144E
Switching Characteristics (continued)
Over the operating range
Parameter [8]
Description
7C144E-15
7C144E-25
7C144E-55
Min
Max
Min
Max
Min
Max
Unit
Busy Timing [12]
tBLA
BUSY LOW from address match
–
15
–
20
–
30
ns
tBHA
BUSY HIGH from address
mismatch
–
15
–
20
–
30
ns
tBLC
BUSY LOW from CE LOW
–
15
–
20
–
30
ns
tBHC
BUSY HIGH from CE HIGH
–
15
–
20
–
30
ns
tPS
Port setup for priority
5
–
5
–
5
–
ns
tWB
R/W LOW after BUSY LOW
0
–
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH
13
–
20
–
30
–
ns
–
15
–
25
–
55
ns
tBDD
BUSY HIGH to data
Interrupt Timing
valid[13]
[12]
tINS
INT Set time
–
15
–
25
–
35
ns
tINR
INT Reset time
–
15
–
25
–
35
ns
Semaphore Timing
tSOP
SEm flag update pulse (OE or
SEM)
10
–
10
–
20
–
ns
tSWRD
SEm flag write to read time
5
–
5
–
5
–
ns
tSPS
SEm flag contention window
5
–
5
–
5
–
ns
tSAA
SEM Address Access Time
–
15
–
20
–
20
ns
Note
12. Test conditions used are Load 2.
13. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
Document Number: 001-63982 Rev. *D
Page 10 of 23
CY7C144E
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [14, 15]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [14, 16, 17]
SEM or CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Figure 6. Read Timing with Port-to-port Delay (M/S = L) [18, 19]
tWC
ADDRESSR
MATCH
t
R/WR
PWE
t
DATAIN R
ADDRESSL
t
SD
HD
VALID
MATCH
tDDD
DATA OUTL
VALID
tWDD
Notes
14. R/W is HIGH for read cycle.
15. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
16. Address valid prior to or coincident with CE transition LOW.
17. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
18. BUSY = HIGH for the writing port.
19. CEL = CER = LOW.
Document Number: 001-63982 Rev. *D
Page 11 of 23
CY7C144E
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (OE Three-state Data I/Os (Either Port)) [20, 21, 22]
tWC
ADDRESS
tSCE
SEM OR CE
tHA
tAW
tPWE
R/W
tSA
tSD
DATA IN
tHD
DATA VALID
OE
t
tHZOE
LZOE
HIGH IMPEDANCE
DATA OUT
Figure 8. Write Cycle No. 2 (R/W Three-state Data I/Os (Either Port)) [20, 22, 23]
tWC
ADDRESS
tSCE
tHA
SEM OR CE
R/W
tSA
tAW
tPWE
tSD
DATAVALID
DATA IN
tHZWE
DATA OUT
tHD
tLZWE
HIGH IMPEDANCE
Notes
20. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
21. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
be as short as the specified tPWE.
22. R/W must be HIGH during all address transitions.
23. Data I/O pins enter high impedance when OE is held LOW during write.
Document Number: 001-63982 Rev. *D
Page 12 of 23
CY7C144E
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side [24]
tOHA
tAA
A0A 2
VALID ADDRESS
VALID ADDRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O0
DATA IN VALID
tSA
DATA OUT VALID
tHD
tPWE
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Semaphore Contention [25, 26, 27]
A0LA 2L
MATCH
R/WL
SEML
tSPS
A0RA 2R
MATCH
R/WR
SEM R
Notes
24. CE = HIGH for the duration of the above timing (both write and read cycle).
25. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH
26. Semaphores are reset (available to both ports) at cycle start.
27. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Document Number: 001-63982 Rev. *D
Page 13 of 23
CY7C144E
Switching Waveforms (continued)
Figure 11. Read with BUSY (M/S = HIGH) [28]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATAINR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
28. CEL = CER = LOW.
Document Number: 001-63982 Rev. *D
Page 14 of 23
CY7C144E
Switching Waveforms (continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) [29]
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [29]
Left Address Valid First:
tRC or tWC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Note
29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Document Number: 001-63982 Rev. *D
Page 15 of 23
CY7C144E
Switching Waveforms (continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR
tWC
ADDRESS L
WRITE 1FFF
[30
tHA [31]
CE L
R/W L
INT R
tINS [32]
Right Side Clears INTR
tRC
ADDRESS R
READ 1FFF
[30]
CER
tINR [32]
R/WR
OE R
INTR
Right Side Sets INTL
tWC
ADDRESS R
WRITE 1FFE
[30]
tHA [31]
CE R
R/W R
INT L
tINS [32]
Left Side Clears INTL
tRC
ADDRESS R
READ 1FFE
[30]
CEL
tINR[32]
R/WL
OEL
INTL
Notes
30. 8K × 8 (CY7C144E): 1FFE(left port) and 1FFF(right port).
31. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
32. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document Number: 001-63982 Rev. *D
Page 16 of 23
CY7C144E
Typical DC and AC Characteristics
Figure 16. Typical DC and AC Characteristics
ISB3
0.8
0.6
0.4
0.2
0.0
4.0
4.5
5.0
5.5
1.0
ISB3
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
0.2
0.6
55
6.0
125
1.6
1.3
1.4
Normalized tAA
1.4
1.2
1.1
TA = 25°C
5.0
40
0
0
5.5
1.0
VCC = 5.0V
0.6
55
6.0
25
30.0
60
40
VCC = 5.0V
TA = 25°C
20
0
0.0
1.0
15.0
0.0
VCC = 4.5V
TA = 25°C
5.0
0
1.0
2.0
3.0
4.0
Supply Voltage (V)
Document Number: 001-63982 Rev. *D
5.0
0
3.0
4.0
5.0
1.25
Normalized Icc Vs. Cycle Time
1.0
VCC = 5.0V
TA = 25°C
VIN = 5.0V
0.75
10.0
0.25
2.0
Output Voltage (V)
Normalized ICC
Delta tAA (ns)
Normalized tPC
20.0
0.50
5.0
4.0
80
25.0
0.75
3.0
100
125
Typical Access Time Change
Vs. Output Loading
1.00
2.0
Output Sink Current
Vs. Output Voltage
Ambient Temperature (°C)
Supply Voltage (V)
Typical Power-on Current
Vs. Supply Voltage
1.0
120
1.2
0.9
4.5
VCC = 5.0V
TA = 25°C
80
140
0.8
0.8
4.0
120
Output Voltage (V)
Normalized Access Time
Vs. Ambient Temperature
Normalized Access Time
Vs. Supply Voltage
Normalized tAA
25
160
Ambient Temperature (°C)
Supply Voltage (V)
1.0
200
ICC
Output Source Current (mA)
ICC
1.0
Output Source Current
Vs. Output Voltage
Output Sink Current (mA)
Normalized ICC, ISB
1.2
1.2
NORMALIZED ICC, ISB
1.4
Normalized Supply Current
Vs. Ambient Temperature
Normalized Supply Current
Vs. Supply Voltage
0
200 400 600 800 1000
CAPACITANCE (pF)
0.50
10
28
40
66
Cycle Frequency (MHz)
Page 17 of 23
CY7C144E
Ordering Information
Speed
(ns)
15
Package
Diagram
Ordering Code
Package Type
Operating
Range
CY7C144E-15AXC
51-85046
64-pin TQFP (Pb-free)
Commercial
CY7C144E-15JXI
51-85005
68-pin PLCC (Pb-free)
Industrial
CY7C144E-15AXI
51-85046
64-pin TQFP (Pb-free)
Industrial
25
CY7C144E-25AXC
51-85046
64-pin TQFP (Pb-free)
Commercial
55
CY7C144E-55AXC
51-85046
64-pin TQFP (Pb-free)
Commercial
CY7C144E-55JXC
51-85005
68-pin PLCC (Pb-free)
Commercial
Ordering Code Definitions
CY 7 C 144 E - XX X
X
X
Temperature Grade: X = C or I
C = Commercial; I = Industrial
X = Pb-free
Package Type: X = A or J
A = 64-pin TQFP; J = 68-pin PLCC
Speed Grade: XX = 15 ns or 25 ns or 55 ns
Process Version: E = R4
Part Number Identifier
Technology: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-63982 Rev. *D
Page 18 of 23
CY7C144E
Package Diagrams
Figure 17. 64-pin TQFP (14.0 × 14.0 × 1.4 mm) Package Outline, 51-85046
ș1
ș
ș2
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
D
15.75 16.00 16.25
D1
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.30 0.35 0.40
L
0.45 0.60 0.75
L2
L3
e
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.20
c
L1
NOTE:
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Document Number: 001-63982 Rev. *D
Page 19 of 23
CY7C144E
Package Diagrams (continued)
Figure 18. 68-pin PLCC (0.958 × 0.958 Inches) Package Outline, 51-85005
51-85005 *D
Document Number: 001-63982 Rev. *D
Page 20 of 23
CY7C144E
Acronyms
Document Conventions
Table 4. Acronyms
Units of Measure
Acronym
Description
Table 5. Units of Measure
CMOS
complementary metal oxide semiconductor
CE
chip enable
°C
I/O
input/output
µA
microampere
OE
output enable
mA
milliampere
SRAM
static random access memory
ns
nanosecond
TSOP
thin small outline package
pF
picofarad
WE
write enable
V
volt
W
watt
Document Number: 001-63982 Rev. *D
Symbol
Unit of Measure
degree Celsius
Page 21 of 23
CY7C144E
Document History Page
Document Title: CY7C144E, 8K × 8 Dual-Port Static RAM with SEM, INT, BUSY
Document Number: 001-63982
Revision
ECN
Orig. of
Change
Submission
Date
**
3038037
ADMU
09/24/2010
New data sheet.
*A
3395887
ADMU
10/05/2011
Updated Document Title to read as “CY7C144E, 8K × 8 Dual-Port Static RAM
with SEM, INT, BUSY”.
Changed status from Preliminary to Final.
Removed CY7C138E and related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*B
3403147
ADMU
10/12/2011
No technical updates.
Post to external web.
*C
4559526
ADMU
11/07/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *E to *F.
*D
5633658
NILE
02/16/2017
Updated Package Diagrams:
spec 51-85046 – Changed revision from *F to *H.
spec 51-85005 – Changed revision from *C to *D.
Removed Reference Documents.
Updated to new template.
Document Number: 001-63982 Rev. *D
Description of Change
Page 22 of 23
CY7C144E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
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Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2010–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-63982 Rev. *D
Revised February 16, 2017
Page 23 of 23
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