CY7C1460AV33

CY7C1460AV33 CY7C1462AV33 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1460AV33/CY7C1462AV33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects (BWa–BWd for CY7C1460AV33 and BWa–BWb for CY7C1462AV33) and a write enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Pin compatible and functionally equivalent to ZBT Supports 250 MHz bus operations with zero wait states ❐ Available speed grades are 250, 200 and 167 MHz Internally self timed output buffer control to eliminate the need to use asynchronous OE Fully registered (inputs and outputs) for pipelined operation Byte write capability 3.3 V power supply 3.3 V/2.5 V I/O power supply Fast clock-to-output times ❐ 2.6 ns (for 250 MHz device) Clock enable (CEN) pin to suspend operation Synchronous self timed writes CY7C1460AV33, CY7C1462AV33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. IEEE 1149.1 JTAG-compatible boundary scan Burst capability—linear or interleaved burst order “ZZ” sleep mode option and stop clock option ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram – CY7C1460AV33 (1 M × 36) A0, A1, A MODE C LK C EN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BW a BW b BW c BW d WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E DQ s DQ Pa DQ Pb DQ Pc DQ Pd E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL Cypress Semiconductor Corporation Document Number: 38-05353 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 28, 2011 [+] Feedback CY7C1460AV33 CY7C1462AV33 Logic Block Diagram – CY7C1462AV33 (2 M × 18) A0, A1, A MODE C LK C EN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BW a BW b WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S DQ s DQ Pa DQ Pb E E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Document Number: 38-05353 Rev. *I Page 2 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Contents Selection Guide ................................................................ 4 Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Single Read Accesses ................................................ 7 Burst Read Accesses .................................................. 7 Single Write Accesses ................................................. 7 Burst Write Accesses .................................................. 8 Sleep Mode ................................................................. 8 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................. 8 Linear Burst Address Table (MODE = GND) .................. 8 ZZ Mode Electrical Characteristics ................................. 8 Truth Table ........................................................................ 9 Partial Write Cycle Description ..................................... 10 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11 Disabling the JTAG Feature ...................................... 11 TAP Controller State Diagram ....................................... 11 Test Access Port (TAP) ............................................. 11 TAP Controller Block Diagram ...................................... 11 PERFORMING A TAP RESET .................................. 11 TAP REGISTERS ...................................................... 11 TAP Instruction Set ................................................... 12 TAP Timing Diagram ...................................................... 13 TAP AC Switching Characteristics ............................... 13 3.3 V TAP AC Test Conditions ....................................... 14 2.5 V TAP AC Test Conditions ....................................... 14 TAP DC Electrical Characteristics and Operating Conditions .................................................. 14 Identification Register Definitions ................................ 14 Scan Register Sizes ....................................................... 15 Identification Codes ....................................................... 15 165-ball FBGA Boundary Scan Order .......................... 16 Maximum Ratings ........................................................... 17 Operating Range ............................................................. 17 Neutron Soft Error Immunity ......................................... 17 Electrical Characteristics ............................................... 17 Capacitance .................................................................... 18 Thermal Resistance ........................................................ 18 Switching Characteristics .............................................. 19 Switching Waveforms .................................................... 20 Ordering Information ...................................................... 22 Ordering Code Definitions ......................................... 22 Package Diagrams .......................................................... 23 Acronyms ........................................................................ 25 Document Conventions ................................................. 25 Units of Measure ....................................................... 25 Document History Page ................................................. 26 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ......................................................... 28 Document Number: 38-05353 Rev. *I Page 3 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current 250 MHz 2.6 475 120 200 MHz 3.2 425 120 167 MHz 3.4 375 120 Unit ns mA mA Pin Configurations Figure 1. 100-pin TQFP Pinout A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPb DQb DQb VDDQ VSS A A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC CY7C1460AV33 (1 M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQb DQb DQb DQb VSS VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC CY7C1462AV33 (2 M × 18) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC/288M NC/144M NC/288M NC/144M MODE A A A A A1 A0 MODE A A A A A1 A0 VSS VDD NC/72M A A A A A A A A NC/72M Document Number: 38-05353 Rev. *I VSS VDD A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Pin Configurations (continued) Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) CY7C1460AV33 (1 M × 36) 1 A B C D E F G H J K L M N P R NC/576M NC/1G DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE 8 ADV/LD 9 A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC/288M A OE A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A NC/144M NC/72M A A CY7C1462AV33 (2 M × 18) 1 A B C D E F G H J K L M N P R NC/576M NC/1G NC NC NC NC NC NC DQb DQb DQb DQb DQPb MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE VSS VSS 8 ADV/LD 9 A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC/288M A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 OE VSS VDD A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VDD VDD VDD VDD VDD VDD VDD VDD VSS A NC/144M NC/72M A A Document Number: 38-05353 Rev. *I Page 5 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Pin Definitions Pin Name A0 A1 A BWa BWb BWc BWd BWe BWf BWg BWh WE ADV/LD I/O Type Inputsynchronous Inputsynchronous Pin Description Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. Inputsynchronous Inputsynchronous Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW to load a new address. Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE defaults HIGH, to an interleaved burst order. CLK CE1 CE2 CE3 OE Inputclock Inputsynchronous Inputsynchronous Inputsynchronous Inputasynchronous CEN Inputsynchronous I/Osynchronous DQa DQb DQc DQd DQe DQf DQg DQh DQPa,DQPb, DQPc,DQPd DQPe,DQPf DQPg,DQPh MODE I/Osynchronous Input strap pin TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. synchronous Document Number: 38-05353 Rev. *I Page 6 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Pin Definitions (continued) Pin Name TDI TMS TCK VDD VDDQ VSS NC NC/72M I/O Type Pin Description JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. synchronous Test mode select This pin controls the test access port state machine. Sampled on the rising edge of synchronous TCK. JTAG-clock Power supply Ground N/A N/A N/A N/A N/A N/A Inputasynchronous Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ pin has an internal pull-down. logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250 MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW for the device to drive out the requested data. During the second clock, a subsequent operation (read/write/deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output tristates following the next clock rise. I/O power supply Power supply for the I/O circuitry. NC/144M NC/288M NC/576M NC/1G ZZ Functional Overview The CY7C1460AV33/CY7C1462AV33 are synchronous-pipelined burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the write enable (WE). BW[x] can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD should be driven LOW after the device has been deselected to load a new address for the next operation. Burst Read Accesses The CY7C1460AV33/CY7C1462AV33 have an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Accesses section earlier. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, (3) the write enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory core and control Document Number: 38-05353 Rev. *I Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) the write signal WE is Page 7 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 asserted LOW. The address presented to the address inputs is loaded into the address register. The write signals are latched into the control logic block. On the subsequent clock rise the data lines are automatically tristated regardless of the state of the OE input signal. This enables the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33). In addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the write operation is controlled by BW (BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The CY7C1460AV33/CY7C1462AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the write enable input (WE) with the selected byte write select (BW) input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1460AV33/CY7C1462AV33 are common I/O devices, data should not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) inputs. Doing so tristates the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are automatically tristated during the data portion of a write cycle, regardless of the state of OE. address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Accesses section earlier. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Burst Write Accesses The CY7C1460AV33/CY7C1462AV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ inactive to exit sleep current Test Conditions ZZ  VDD 0.2 V ZZVDD  0.2 V ZZ  0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 100 2tCYC – 2tCYC – Unit mA ns ns ns ns Document Number: 38-05353 Rev. *I Page 8 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Truth Table The Truth Table for CY7C1460AV33/CY7C1462AV33 follows. [1, 2, 3, 4, 5, 6, 7] Operation Deselect cycle Continue deselect cycle Read cycle (begin burst) Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) Write cycle (continue burst) NOP/WRITE ABORT (begin burst) WRITE ABORT (continue burst) IGNORE CLOCK EDGE (stall) SLEEP MODE Address Used None None External Next External Next External Next None Next Current None CE H X L X L X L X L X X X ZZ L L L L L L L L L L L H ADV/LD L H L H L H L H L H X X WE X X H X H X L X L X X X BWx X X X X X X L L H H X X OE X X L L H H X X X X X X CEN L L L L L L L L L L H X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X DQ Tri-state Tri-state Data out (Q) Data out (Q) Tri-state Tri-state Data in (D) Data in (D) Tri-state Tri-state – Tri-state Notes 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tristated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tristate when OE is inactive or when the device is deselected, and DQs=data when OE is active. Document Number: 38-05353 Rev. *I Page 9 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Partial Write Cycle Description The Partial Write Cycle Description for CY7C1460AV33/CY7C1462AV33 follows. [8, 9, 10, 11] Function (CY7C1460AV33) Read Write – no bytes written Write byte a – (DQa and DQPa) Write byte b – (DQb and DQPb) Write bytes b, a Write byte c – (DQc and DQPc) Write bytes c, a Write bytes c, b Write bytes c, b, a Write byte d – (DQd and DQPd) Write bytes d, a Write bytes d, b Write bytes d, b, a Write bytes d, c Write bytes d, c, a Write bytes d, c, b Write all bytes Function (CY7C1462AV33)[9, 11] Read Write – no bytes written Write byte a – (DQa and DQPa) Write byte b – (DQb and DQPb) Write both bytes WE H L L L L L L L L L L L L L L L L BWd X H H H H H H H H L L L L L L L L WE H L L L L BWc X H H H H L L LL L H H H H L L L L BWb x H H L L BWb X H H L L H H L L H H L L H H L L BWa X H L H L H L H L H L H L H L H L BWa x H L H L Notes 8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 9. Write is defined by WE and BWX. See Write Cycle Description table for details. 10. When a write cycle is detected, all I/Os are tristated, even during byte writes. 11. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active. Document Number: 38-05353 Rev. *I Page 10 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV33/CY7C1462AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic level. The CY7C1460AV33/CY7C1462AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. TAP Controller Block Diagram 0 Bypass Register 210 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TM S TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Document Number: 38-05353 Rev. *I Page 11 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The length of the boundary scan register for the SRAM in different packages is listed in the Scan Register Sizes table. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The 165-ball FBGA Boundary Scan Order [16] on page 16 and show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 14 The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions described in detail are as follows. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. Document Number: 38-05353 Rev. *I Page 12 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #89 (for 165-ball FBGA package) or bit #138 (for 209-ball FBGA package). When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing Diagram 1 Test Clock (TCK ) t TM SS 2 3 4 5 6 t TH t TM SH t TL t CY C T est M ode Select (TM S) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[12, 13] Parameter Description Clock tTCYC TCK clock cycle time TCK clock frequency tTF TCK clock HIGH time tTH tTL TCK clock LOW time Output Times TCK clock LOW to TDO valid tTDOV tTDOX TCK clock LOW to TDO invalid Setup Times TMS setup to TCK clock rise tTMSS tTDIS TDI setup to TCK clock rise Capture setup to TCK rise tCS Hold Times tTMSH TMS hold after TCK clock rise TDI hold after clock rise tTDIH tCH Capture hold after clock rise Notes 12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Min 50 – 20 20 – 0 5 5 5 5 5 5 Max – 20 – – 10 – – – – – – – Unit ns MHz ns ns ns ns ns ns ns ns ns ns Document Number: 38-05353 Rev. *I Page 13 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 3.3 V TAP AC Test Conditions Input pulse levels................................................VSS to 3.3 V Input rise and fall times....................................................1 ns Input timing reference levels.......................................... 1.5 V Output reference levels ................................................. 1.5 V Test load termination supply voltage ............................. 1.5 V Figure 3. 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Test Conditions Input pulse levels ............................................... VSS to 2.5 V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ 1.25 V Output reference levels ............................................... 1.25 V Test load termination supply voltage ........................... 1.25 V Figure 4. 2.5 V TAP AC Output Load Equivalent 1.5V 50 Ω TDO Z O= 50 Ω 20pF 1.25V 50 Ω TDO Z O= 50 Ω 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)[14] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH voltage Output HIGH voltage Output LOW voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input load current GND < VIN < VDDQ Test Conditions IOH = –4.0 mA, VDDQ = 3.3 V IOH = –1.0 mA, VDDQ = 2.5 V IOH = –100 µA IOL = 8.0 mA IOL = 1.0 mA IOL = 100 µA VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V Min 2.4 2.0 2.9 2.1 – – – – 2.0 1.7 –0.3 –0.3 –5 Max – – – – 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Unit V V V V V V V V V V V V µA Identification Register Definitions Instruction Field Revision number (31:29) Device depth (28:24)[15] Architecture/memory type(23:18) Bus width/density(17:12) Cypress JEDEC ID code (11:1) ID register presence indicator (0) CY7C1460AV33 (1 M × 36) 000 01011 001000 100111 00000110100 1 CY7C1462AV33 (2 M × 18) 000 01011 001000 010111 00000110100 1 Description Describes the version number. Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Notes 14. All voltages referenced to VSS (GND). 15. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05353 Rev. *I Page 14 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Scan Register Sizes Register Name Instruction Bypass ID Boundary scan order (165-ball FBGA package) Bit Size (× 36) 3 1 32 89 Bit Size (× 18) 3 1 32 89 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 38-05353 Rev. *I Page 15 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 165-ball FBGA Boundary Scan Order [16] CY7C1460AV33 (1 M × 36), CY7C1462AV33 (2 M × 18) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ball ID N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 Bit# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ball ID E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 Bit# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 Bit# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Note 16. Bit# 89 is preset HIGH. Document Number: 38-05353 Rev. *I Page 16 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on VDD relative to GND ........–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD DC to outputs in tri-state ....................–0.5 V to VDDQ + 0.5 V DC input voltage .................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, method 3015) Latch-up current .................................................... > 200 mA SEL Neutron Soft Error Immunity Parameter LSBU Description Logical single bit upsets Logical multi bit upsets Single event latch-up Test Conditions Typ 25 °C 361 Max* 394 Unit FIT/ Mb FIT/ Mb FIT/ Dev LMBU 25 °C 0 0.01 85 °C 0 0.1 * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Operating Range Range Industrial Ambient Temperature –40 °C to +85 °C VDD 3.3 V – 5% / + 10% VDDQ 2.5 V – 5% to VDD Commercial 0 °C to +70 °C Electrical Characteristics Over the Operating Range[17, 18] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power supply voltage I/O supply voltage Output HIGH voltage Output LOW voltage Input HIGH voltage[17] Input LOW voltage[17] Input leakage current except ZZ and MODE Input current of MODE Test Conditions for 3.3 V I/O for 2.5 V I/O for 3.3 V I/O, IOH =4.0 mA for 2.5 V I/O, IOH = 1.0 mA for 3.3 V I/O, IOL =8.0 mA for 2.5 V I/O, IOL =1.0 mA for 3.3 V I/O for 2.5 V I/O for 3.3 V I/O for 2.5 V I/O GND  VI  VDDQ Min 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 –30 – –5 – –5 Max Unit 3.6 V VDD V 2.625 V – V – V 0.4 V 0.4 V VDD + 0.3 V V VDD + 0.3 V V 0.8 V 0.7 V 5 A – 5 – 30 5 A A A A A IOZ Input = VSS Input = VDD Input current of ZZ Input = VSS Input = VDD Output leakage current GND  VI  VDDQ, output disabled Notes 17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2 V (Pulse width less than tCYC/2). 18. Tpower up: Assumes a linear ramp from 0 V to VDD (Min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05353 Rev. *I Page 17 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Electrical Characteristics (continued) Over the Operating Range[17, 18] Parameter IDD Description VDD operating supply Test Conditions VDD = Max, IOUT = 0 mA, 4 ns cycle, 250 MHz f = fMAX = 1/tCYC 5 ns cycle, 200 MHz 6 ns cycle, 167 MHz Max VDD, device deselected, All speed grades VIN  VIH or VIN  VIL, f = fMAX = 1/tCYC Max VDD, device deselected, All speed grades VIN  0.3 V or VIN > VDDQ 0.3 V, f=0 Max VDD, device deselected, All speed grades VIN  0.3 V or VIN > VDDQ 0.3 V, f = fMAX = 1/tCYC Max VDD, device deselected, All speed grades VIN  VIH or VIN  VIL, f=0 Min – – – – Max 475 425 375 225 Unit mA mA mA mA ISB1 ISB2 ISB3 ISB4 Automatic CE power-down current—TTL inputs Automatic CE power-down current—CMOS inputs Automatic CE power-down current—CMOS inputs Automatic CE power-down current—TTL inputs – 120 mA – 200 mA – 135 mA Capacitance[19] Parameter CIN CCLK CI/O Description Input capacitance Clock input capacitance Input/output capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 2.5 V, VDDQ = 2.5 V 100 TQFP Max 165 FBGA Max 6.5 7 3 7 5.5 6 Unit pF pF pF Thermal Resistance[19] Parameters JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 25.21 2.28 165 FBGA Package 20.8 3.2 Unit C/W C/W Figure 5. AC Test Loads and Waveforms 3.3 V I/O Test Load OUTPUT Z0 = 50  3.3 V OUTPUT RL = 50  R = 317  VDDQ 5 pF GND R = 351  10% ALL INPUT PULSES 90% 90% 10%  1 ns VT = 1.5 V (a) INCLUDING JIG AND SCOPE 2.5 V  1 ns (b) R = 1667  VDDQ GND R =1538  10% (c) ALL INPUT PULSES 90% 90% 10%  1 ns 2.5 V I/O Test Load OUTPUT Z0 = 50  OUTPUT RL = 50  VT = 1.25 V (a) 5 pF INCLUDING JIG AND SCOPE  1 ns (b) (c) Note 19. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05353 Rev. *I Page 18 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Switching Characteristics Over the Operating Range [20, 21] Parameter tPower[22] Clock tCYC FMAX tCH tCL Output Times tCO tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Setup Times tAS tDS tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Address hold after CLK rise Data input hold after CLK rise CEN hold after CLK rise WE, BWx hold after CLK rise ADV/LD hold after CLK rise Chip select hold after CLK rise 0.3 0.3 0.3 0.3 0.3 0.3 – – – – – – 0.4 0.4 0.4 0.4 0.4 0.4 – – – – – – 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – ns ns ns ns ns ns Address setup before CLK rise Data input setup before CLK rise CEN setup before CLK rise WE, BWx setup before CLK rise ADV/LD setup before CLK rise Chip select setup 1.2 1.2 1.2 1.2 1.2 1.2 – – – – – – 1.4 1.4 1.4 1.4 1.4 1.4 – – – – – – 1.5 1.5 1.5 1.5 1.5 1.5 – – – – – – ns ns ns ns ns ns Data output valid after CLK rise OE LOW to output valid Data output hold after CLK rise Clock to high Clock to low Z[23, 24, 25] Z[23, 24, 25] Z[23, 24, 25] – – 1.0 – 1.0 – 0 2.6 2.6 – 2.6 – 2.6 – – – 1.5 – 1.3 – 0 3.2 3.0 – 3.0 – 3.0 – – – 1.5 – 1.5 – 0 3.4 3.4 – 3.4 – 3.4 – ns ns ns ns ns ns ns Clock cycle time Maximum operating frequency Clock HIGH Clock LOW 4.0 – 1.5 1.5 – 250 – – 5.0 – 2.0 2.0 – 200 – – 6.0 – 2.4 2.4 – 167 – – ns MHz ns ns Description VCC (typical) to the first access read or write –250 Min 1 Max – Min 1 –200 Max – Min 1 –167 Max – Unit ms OE HIGH to output high Z[23, 24, 25] OE LOW to output low Notes 20. Timing reference is 1.5 V when VDDQ=3.3 V and is 1.25 V when VDDQ=2.5 V. 21. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 22. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 24. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 25. This parameter is sampled and not 100% tested. Document Number: 38-05353 Rev. *I Page 19 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Switching Waveforms Figure 6. Read/Write/Timing[26, 27, 28] 1 CLK t CENS t CENH 2 t CYC 3 4 5 6 7 8 9 10 t CH t CL CEN t CES t CEH CE ADV/LD WE BW x ADDRESS t AS A1 t AH A2 t DS t DH A3 A4 t CO t CLZ t DOH A5 t OEV A6 t CHZ A7 Data I n-Out (DQ) OE WRITE D(A1) WRITE D(A2) D(A1) D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ Q(A4+1) D(A5) Q(A6) t DOH t OELZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT DON’T CARE UNDEFINED Notes 26. For this waveform ZZ is tied low. 27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 38-05353 Rev. *I Page 20 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Switching Waveforms 1 CLK CEN CE ADV/LD WE BWx ADDRESS A1 A2 A3 A4 A5 t CHZ (continued) Figure 7. NOP, STALL and DESELECT Cycles[29, 30, 31] 2 3 4 5 6 7 8 9 10 Data In-Out (DQ) WRITE D(A1) READ Q(A2) STALL D(A1) Q(A2) Q(A3) D(A4) Q(A5) READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT DON’T CARE UNDEFINED Figure 8. ZZ Mode Timing[32, 33] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only A LL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 29. For this waveform ZZ is tied low. 30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 33. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05353 Rev. *I Page 21 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) 167 Ordering Code CY7C1460AV33-167AXC CY7C1462AV33-167AXC CY7C1460AV33-167BZC CY7C1460AV33-167AXI 200 250 CY7C1460AV33-200AXC CY7C1460AV33-250AXC CY7C1460AV33-250AXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Industrial Commercial Commercial Industrial Package Diagram Part and Package Type Operating Range Commercial 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Ordering Code Definitions CY 7C 14XX A V33 - 167 XX X Temperature range: X = C or I C = Commercial; I = Industrial Package Type: XX = AX or BZ or BG AX = 100-pin TQFP (Pb-free) BZ = 165-ball FPBGA Speed Grade (167 MHz / 200 MHz / 250 MHz) V33 = 3.3 V Process Technology  90 nm 14XX = 1460 or 1462 1460 = PL, 1 Mb × 36 (36 Mb) 1462 = PL, 2 Mb × 18 (36 Mb) Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document Number: 38-05353 Rev. *I Page 22 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) 51-85050 *D Document Number: 38-05353 Rev. *I Page 23 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Package Diagrams (continued) Figure 10. 165-ball FBGA (15 × 17 × 1.4 mm) 51-85165 *B Document Number: 38-05353 Rev. *I Page 24 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Acronyms Acronym CE CEN CMOS FPBGA I/O JTAG NoBL OE SRAM TCK TMS TDI TDO TQFP WE chip enable clock enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable V µA mA ms mm MHz pF W °C Description Document Conventions Units of Measure Symbol ns nanoseconds volts microamperes milliamperes milliseconds millimeter megahertz picofarads watts degrees Celcius Unit of Measure Document Number: 38-05353 Rev. *I Page 25 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Document History Page Document Title: CY7C1460AV33/CY7C1462AV33, 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 Revision ** ECN 254911 Orig. of Change SYT Submission Date See ECN Description of Change New Data sheet Part number changed from previous revision. New and old part number differ by the letter “A” Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on Page # 5 Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical Characteristics table Replaced JA and JC from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for 250, 200 and 167 MHz respectively Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167 MHz respectively Changed ISB2 from 80 mA to 100 mA for all frequencies Changed ISB3 from 180, 170 and 160 mA to 200 mA for 250, 200 and 167 MHz respectively Changed ISB4 from 100 mA to 110 mA for all frequencies Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz Speed Bin Added Pb-Free information for 100-pin TQFP and 165 FBGA and 209 BGA packages Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by Shading and Unshading MPNs as per availability Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from –5 and 30 A to –30 and 5 A respectively and also Changed IX current value in ZZ from –30 and 5 A to –5 and 30 A respectively on page# 18 Modified test condition from VIH < VDD to VIH VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. Page 26 of 28 *A 303533 SYT See ECN *B 331778 SYT See ECN *C 417509 RXU See ECN *D 473229 NXR See ECN Document Number: 38-05353 Rev. *I [+] Feedback CY7C1460AV33 CY7C1462AV33 Document History Page (continued) Document Title: CY7C1460AV33/CY7C1462AV33, 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 Revision *E ECN 2756998 Orig. of Change VKN Submission Date 08/28/09 Description of Change Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram for spec 51-85165. Added CY7C1460AV33-167AXI part in Ordering Information Updated links in Sales, Solutions, and Legal Information Updated 100-pin TQFP and 209-Ball FBGA package diagrams. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Removed all mention of CY7C1464 and 209-Ball FBGA: part pruned. Corrected typos in Units of Measure on page 25. Updated Ordering Information. Updated Package Diagrams. *F 2900822 NJY 03/29/2010 *G 3043005 09/30/2010 NJY *H *I 3051765 3207715 10/07/2010 03/28/2011 NJY NJY Document Number: 38-05353 Rev. *I Page 27 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05353 Rev. *I QDR is the registered trademark and NoBL the trademarks of their respective holders. ® TM Revised March 28, 2011 TM Page 28 of 28 and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be [+] Feedback