CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
36 Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin compatible and functionally equivalent to ZBT
■
Supports 250 MHz Bus Operations with Zero Wait States
❐ Available speed grades are 250, 200 and 167 MHz
■
Internally self timed Output Buffer Control to eliminate the need
to use Asynchronous OE
■
Fully registered (inputs and outputs) for Pipelined Operation
■
Byte Write Capability
■
3.3V Power Supply
■
3.3V/2.5V I/O Power Supply
■
Fast Clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■
Clock Enable (CEN) Pin to suspend operation
■
Synchronous self timed Writes
■
CY7C1460AV33, CY7C1462AV33 available in
JEDEC-standard Pb-Free 100-pin TQFP, Pb-Free and
non-Pb-Free 165-ball FBGA package. CY7C1464AV33
available in Pb-Free and non-Pb-Free 209-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
Burst Capability—Linear or Interleaved Burst Order
■
“ZZ” Sleep Mode Option and Stop Clock Option
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The CY7C1460AV33/
CY7C1462AV33/CY7C1464AV33 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous self
timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Logic Block Diagram – CY7C1460AV33 (1M x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
MEMORY
ARRAY
WRITE
DRIVERS
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05353 Rev. *F
E
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2010
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Logic Block Diagram – CY7C1462AV33 (2M x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
ADV/LD
C
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
MEMORY
ARRAY
WRITE
DRIVERS
O
U
T
P
U
T
S
E
N
S
E
R
E
G
I
S
T
E
R
S
A
M
P
S
BW b
WE
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
E
INPUT
REGISTER 0
E
DQ s
DQ Pa
DQ Pb
E
READ LOGIC
Sleep
Control
ZZ
Logic Block Diagram – CY7C1464AV33 (512K x 72)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
BW b
BW c
BW d
BW e
BW f
BW g
BW h
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WE
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby
Current
Document #: 38-05353 Rev. *F
250 MHz
200 MHz
167 MHz
Unit
2.6
475
120
3.2
425
120
3.4
375
120
ns
mA
mA
Page 2 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Contents
Features............................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram – CY7C1460AV33 (1M x 36)......... 1
Logic Block Diagram – CY7C1462AV33 (2M x 18)......... 2
Logic Block Diagram – CY7C1464AV33 (512K x 72) ..... 2
Selection Guide ................................................................ 2
Contents ............................................................................ 3
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Sleep Mode ................................................................. 9
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................... 9
Linear Burst Address Table (MODE = GND) .................. 9
ZZ Mode Electrical Characteristics................................. 9
Truth Table ...................................................................... 10
Partial Write Cycle Description ..................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
TAP Controller State Diagram ....................................... 12
Test Access Port (TAP)............................................. 12
TAP Controller Block Diagram ...................................... 12
PERFORMING A TAP RESET.................................. 12
TAP REGISTERS...................................................... 12
TAP Instruction Set ................................................... 13
TAP Timing Diagram ...................................................... 14
TAP AC Switching Characteristics
Over the Operating Range ................................................ 14
3.3V TAP AC Test Conditions........................................ 15
Document #: 38-05353 Rev. *F
2.5V TAP AC Test Conditions........................................ 15
TAP DC Electrical Characteristics And
Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to
3.6V unless otherwise noted) ............................................ 15
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
165-ball FBGA Boundary Scan Order........................... 17
209-ball BGA Boundary Scan Order .............................. 18
Maximum Ratings........................................................... 19
Operating Range............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics
Over the Operating Range ............................................................ 19
DC Electrical Characteristics
Over the Operating Range ........................................ 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
Switching Characteristics
Over the Operating Range ............................................................ 21
Ordering Information...................................................... 25
Package Diagrams.......................................................... 25
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Page 3 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1462AV33
(2M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
NC/144M
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
NC/144M
NC/288M
MODE
A
A
A
A
A1
A0
Document #: 38-05353 Rev. *F
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
DQa
NC
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC/288M
CY7C1460AV33
(1M × 36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-Pin TQFP Pinout
Page 4 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm)
CY7C1460AV33 (1M × 36)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
NC/1G
A
CE1
BWc
A
CE2
BWb
CE3
BWa
VSS
CEN
WE
VDDQ
BWd
VSS
VDD
CLK
DQPc
DQc
NC
DQc
VDDQ
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
DQc
DQc
NC
DQd
DQc
VDDQ
VDDQ
NC
VDDQ
VDD
DQc
NC
DQd
VDD
VDD
VDD
DQd
DQd
VDDQ
DQd
DQd
DQd
DQPd
DQd
NC
R
MODE
NC/144M NC/72M
A
9
10
11
ADV/LD
A
A
NC
OE
A
A
NC
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
DQb
DQPb
DQb
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
VSS
VSS
VSS
DQb
NC
DQa
DQb
DQb
ZZ
DQa
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
9
10
11
CY7C1462AV33 (2M × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
NC/576M
NC/1G
A
CE1
A
CE2
BWb
NC
NC
NC
NC
DQb
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
NC
DQb
VDDQ
VDD
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
DQb
NC
VDDQ
DQb
NC
VDDQ
DQb
DQPb
NC
NC
NC/144M NC/72M
MODE
A
Document #: 38-05353 Rev. *F
6
7
8
NC
CE3
CEN
ADV/LD
A
A
A
BWa
CLK
WE
VSS
VSS
OE
VSS
VDD
A
A
NC
VDDQ
VDDQ
NC
NC
DQPa
DQa
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
ZZ
NC
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
NC/288M
A
Page 5 of 28
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Configurations (continued)
Figure 3.
209-ball FBGA (14 x 22 x 1.76 mm)
CY7C1464AV33 (512K x 72)
1
2
A
DQg
DQg
B
DQg
DQg
C
DQg
D
3
4
5
6
7
8
9
10
11
ADV/LD
A
CE3
A
DQb
DQb
WE
A
BWSb
BWSf
DQb
DQb
CE1
NC
BWSe
BWSa
DQb
DQb
OE
NC
NC
VSS
DQb
DQb
DQPf
DQPb
CE2
A
BWSc
BWSg
NC
DQg
BWSh
BWSd NC/576M
DQg
DQg
VSS
NC
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQd
DQd
VSS
NC
NC
MODE
NC
NC
DQe
DQe
U
DQd
DQd
NC/144M
A
A
A
A
NC/288M
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TCK
DQe
DQe
A
NC/1G
NC/72M
TDO
VSS
DQPa
DQf
DQPe
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
InputSynchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising
edge of the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
InputSynchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and
DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and
DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and
DQPh.
WE
InputSynchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Document #: 38-05353 Rev. *F
Page 6 of 28
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
ADV/LD
InputSynchronous
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New
Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, Active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
I/OSynchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by AX during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate
condition. The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPa,DQPb,
DQPc,DQPd
DQPe,DQPf
DQPg,DQPh
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0].
During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is
controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is
controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE defaults HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial Data-out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of
Synchronous
TCK.
TCK
JTAG-Clock
Clock Input to the JTAG Circuitry.
Power Supply Inputs to the Core of the Device.
VDD
Power Supply
VDDQ
I/O Power Supply Power Supply for the I/O Circuitry.
VSS
NC
NC/72M
Ground
N/A
N/A
Ground for the Device. Should be connected to ground of the system.
No Connects. This pin is not connected to the die.
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
Document #: 38-05353 Rev. *F
Page 7 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
NC/576M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/1G
N/A
Not Connected to the Die. Can be tied to any voltage level.
ZZ
InputAsynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected
to VSS or left floating. ZZ pin has an internal pull down.
Functional Overview
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.6 ns
(250 MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the Write Enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core and
control logic. The control logic determines that a read access is
in progress and allows the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tristates following the next clock rise.
Document #: 38-05353 Rev. *F
Burst Read Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have an
on-chip burst counter that enables the user the ability to supply
a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load a new address into the SRAM, as described in the
Single Read Access section earlier. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst
counter regardless of the state of chip enables inputs or WE. WE
is latched at the beginning of a burst cycle. Therefore, the type
of access (Read or Write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
enables the external logic to present the data on DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for
CY7C1462AV33). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
for
CY7C1464AV33,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for
CY7C1462AV33) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d,e,f,g,h
for
CY7C1464AV33,
BWa,b,c,d
for
CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with the
selected Byte Write Select (BW) input selectively writes to only
the desired bytes. Bytes not selected during a byte write
operation remains unaltered. A synchronous self timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
Page 8 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Read/Modify/Write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE) can
be deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for
CY7C1462AV33) inputs. Doing so tristates the output drivers. As
a
safety
precaution,
DQ
and
DQP
for
CY7C1464AV33,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for
CY7C1462AV33) are automatically tristated during the data
portion of a write cycle, regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Write Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the Single Write
Access section earlier. When ADV/LD is driven HIGH on the
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d
for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must
be driven in each cycle of the burst write in order to write the
correct bytes of data.
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document #: 38-05353 Rev. *F
Min
ZZ > VDD − 0.2V
Max
Unit
100
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 9 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Truth Table
The Truth Table for CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Continue
Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK
EDGE
(Stall)
SLEEP MODE
Address
Used
None
None
CE
ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
H
X
L
L
L
H
X
X
X
X
X
X
L
L
L-H
L-H
Tristate
Tristate
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
External
L
L
L
H
X
H
L
L-H
Tristate
Next
X
L
H
X
X
H
L
L-H
Tristate
External
L
L
L
L
L
X
L
L-H
Data In (D)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
None
L
L
L
L
H
X
L
L-H
Tristate
Next
X
L
H
X
H
X
L
L-H
Tristate
Current
X
L
X
X
X
X
H
L-H
-
None
X
H
X
X
X
X
X
X
Tristate
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tristate when OE
is inactive or when the device is deselected, and DQs=data when OE is active.
Document #: 38-05353 Rev. *F
Page 10 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 follows. [1, 2, 3, 8]
Function (CY7C1460AV33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
LL
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1462AV33)[2,8]
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Function (CY7C1464AV33)[2,8]
WE
BWx
Read
H
x
Write – No Bytes Written
L
H
Write Byte X − (DQx and DQPx)
L
L
Write All Bytes
L
All BW = L
Note
8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active.
Document #: 38-05353 Rev. *F
Page 11 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incorporates a serial boundary scan test access port (TAP). This part
is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic level.
The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO should be
left unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any
register. (See TAP Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0
TAP Controller State Diagram
1
Bypass Register
2 1 0
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
TDI
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
x . . . . . 2 1 0
0
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-DR
0
TM S
PAUSE-IR
1
TAP CONTROLLER
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05353 Rev. *F
TDO
Boundary Scan Register
SHIFT-IR
1
Selection
Circuitry
Identification Register
0
SHIFT-DR
Instruction Register
31 30 29 . . . 2 1 0
CAPTURE-IR
0
1
1
0
1
CAPTURE-DR
0
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the Tap Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Page 12 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in the
Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Table , “165-ball FBGA Boundary Scan Order [13],” on
page 17 and Table , “209-ball BGA Boundary Scan Order [13,
14],” on page 18 show the order in which the bits are connected.
Each bit corresponds to one of the bumps on the SRAM
package. The MSB of the register is connected to TDI, and the
LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32 bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Table , “Identification Register
Definitions,” on page 15
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
described in detail are as follows.
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
BYPASS
IDCODE
EXTEST
The IDCODE instruction causes a vendor-specific, 32 bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Document #: 38-05353 Rev. *F
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Page 13 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing Diagram
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Clock
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
tTF
tTH
TCK Clock HIGH time
TCK Clock LOW time
tTL
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
tTDOX
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
tTDIS
tCS
Capture Setup to TCK Rise
Hold Times
TMS Hold after TCK Clock Rise
tTMSH
tTDIH
TDI Hold after Clock Rise
Capture Hold after Clock Rise
tCH
Min
Max
50
20
20
20
10
Unit
ns
MHz
ns
ns
0
ns
ns
5
5
5
ns
ns
ns
5
5
5
ns
ns
ns
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05353 Rev. *F
Page 14 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 3.3V
Input pulse levels ................................................ VSS to 2.5V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................... 1.5V
Input timing reference levels......................................... 1.25V
Output reference levels .................................................. 1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage .............................. 1.5V
Test load termination supply voltage ............................ 1.25V
Figure 4. 3.3V TAP AC Output Load Equivalent
Figure 5. 2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Test Conditions
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3V
2.4
V
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
V
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
IOL = 100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Min
VDDQ = 3.3V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
Description
(1M ×36)
(2M ×18)
(512K ×72)
Revision Number (31:29)
000
000
000
Describes the version number.
Device Depth (28:24)[12]
01011
01011
01011
Reserved for Internal Use
Architecture/Memory Type(23:18)
001000
001000
001000
Defines memory type and
architecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100 Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register.
Instruction Field
Notes
11. All voltages referenced to VSS (GND).
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05353 Rev. *F
Page 15 of 28
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CY7C1462AV33
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Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Bit Size (×72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order (165-ball FBGA package)
89
89
-
Boundary Scan Order (209-ball FBGA package)
-
-
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05353 Rev. *F
Page 16 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
165-ball FBGA Boundary Scan Order [13]
CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18)
Bit#
ball ID
Bit#
ball ID
Bit#
ball ID
Bit#
ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
27
D11
52
A2
77
N2
3
10N
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
A5
72
J2
23
H10
48
A4
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Note
13. Bit# 89 is preset HIGH.
Document #: 38-05353 Rev. *F
Page 17 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
209-ball BGA Boundary Scan Order [13, 14]
CY7C14604V33 (512K x 72)
Bit#
Ball ID
Bit#
ball ID
Bit#
ball ID
Bit#
ball ID
1
W6
36
6F
71
6H
106
3K
2
V6
U6
37
8K
72
6C
107
4K
3
38
9K
73
6B
108
6K
4
W7
39
10K
74
6A
109
2K
5
V7
40
11J
75
5A
110
2L
6
U7
41
10J
76
5B
111
1L
7
T7
42
11H
77
5C
112
2 Mbit
8
V8
43
10H
78
5D
113
1 Mbit
9
U8
44
11G
79
4D
114
2N
10
T8
45
10G
80
4C
115
1N
11
V9
46
11F
81
4A
116
2P
12
U9
47
10F
82
4B
117
1P
13
P6
48
10E
83
3C
118
2R
14
W11
49
11E
84
3B
119
1R
15
W10
50
11D
85
3A
120
2T
16
V11
51
10D
86
2A
121
1T
17
V10
52
11C
87
1A
122
2U
18
U11
53
10C
88
2B
123
1U
19
U10
54
11B
89
1B
124
2V
20
T11
55
10B
90
2C
125
1V
21
T10
56
11A
91
1C
126
2W
22
R11
57
10A
92
2D
127
1W
23
R10
58
9C
93
1D
128
6T
24
P11
59
9B
94
1E
129
3U
25
P10
60
9A
95
2E
130
3V
26
N11
61
8D
96
2F
131
4T
27
N10
62
8C
97
1F
132
5T
28
M11
63
8B
98
1G
133
4U
29
M10
64
8A
99
2G
134
4V
30
L11
65
7D
100
2H
135
5W
31
L10
66
7C
101
1H
136
5V
32
K11
67
7B
102
2J
137
5U
33
M6
68
7A
103
1J
138
Internal
34
L6
69
6D
104
1K
35
J6
70
6G
105
6N
Note
14. Bit# 138 is preset HIGH.
Document #: 38-05353 Rev. *F
Page 18 of 28
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CY7C1462AV33
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Maximum Ratings
Neutron Soft Error Immunity
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Parameter
Description
Storage Temperature ................................. –65°C to +150°C
LSBU
Logical
Single Bit
Upsets
25°C
LMBU
Logical Multi
Bit Upsets
SEL
Single Event
Latch up
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC to Outputs in Tristate .....................–0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Test
Conditions Typ
Max*
Unit
361
394
FIT/
Mb
25°C
0
0.01
FIT/
Mb
85°C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0°C to +70°C
3.3V
–5%/+10%
2.5V –5% to
VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[15]
VIL
Input LOW Voltage[15]
IX
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IOZ
Test Conditions
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O, IOH = −4.0 mA
for 2.5V I/O, IOH = −1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND ≤ VI ≤ VDDQ
Min
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
Max
3.6
VDD
2.625
Unit
V
V
V
V
V
0.4
V
0.4
V
VDD + 0.3V
V
VDD + 0.3V
V
0.8
V
0.7
V
5
μA
–30
5
–5
–5
30
5
μA
μA
μA
μA
μA
Notes
15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
16. Tpower up: Assumes a linear ramp from 0V to VDD (Min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05353 Rev. *F
Page 19 of 28
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Electrical Characteristics Over the Operating Range[15, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
IDD
ISB1
ISB2
ISB3
ISB4
Description
VDD Operating Supply
Test Conditions
VDD = Max, IOUT = 0 mA,
4 ns cycle, 250 MHz
f = fMAX = 1/tCYC
5 ns cycle, 200 MHz
6 ns cycle, 167 MHz
Automatic CE
Max VDD, Device Deselected,
All speed grades
Power down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
Current—TTL Inputs
1/tCYC
Automatic CE
Max VDD, Device Deselected,
All speed grades
Power down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
Automatic CE
Max VDD, Device Deselected,
All speed grades
Power down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = fMAX = 1/tCYC
Automatic CE
Max VDD, Device Deselected,
All speed grades
Power down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Min
Max
475
425
375
225
Unit
mA
mA
mA
mA
120
mA
200
mA
135
mA
Capacitance[17]
Parameter
Description
Test Conditions
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
CIN
CCLK
CI/O
TA = 25°C, f = 1 MHz,
VDD = 2.5V VDDQ = 2.5V
100 TQFP
Max
6.5
3
5.5
165 FBGA
Max
7
7
6
209 FBGA
Max
5
5
7
100 TQFP
Package
25.21
165 FBGA
Package
20.8
209 FBGA
Package
25.31
°C/W
2.28
3.2
4.48
°C/W
Unit
pF
pF
pF
Thermal Resistance[17]
Parameters
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
Unit
Figure 6. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
(a)
2.5V I/O Test Load
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5V
OUTPUT
R = 351Ω
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(b)
(c)
R = 1667Ω
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
ALL INPUT PULSES
VDDQ
GND
R =1538Ω
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Note
17. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05353 Rev. *F
Page 20 of 28
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Switching Characteristics Over the Operating Range [22, 23]
Parameter
tPower[18]
Description
VCC (typical) to the first access read or write
–250
Min
–200
Max
Min
–167
Max
Min
Max
Unit
1
1
1
ms
4.0
5.0
6.0
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.5
2.0
2.4
ns
tCL
Clock LOW
1.5
2.0
2.4
ns
250
200
167
MHz
Output Times
tCO
Data Output Valid After CLK Rise
2.6
3.2
3.4
ns
tEOV
OE LOW to Output Valid
2.6
3.0
3.4
ns
3.4
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High Z[19, 20, 21]
tCLZ
Clock to Low Z[19, 20, 21]
tEOHZ
tEOLZ
1.5
2.6
1.0
OE HIGH to Output High
OE LOW to Output Low
1.0
Z[19, 20, 21]
Z[19, 20, 21]
1.5
3.0
1.3
2.6
ns
1.5
3.0
ns
3.4
ns
0
0
0
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.2
1.4
1.5
ns
tCENS
CEN Setup Before CLK Rise
1.2
1.4
1.5
ns
tWES
WE, BWx Setup Before CLK Rise
1.2
1.4
1.5
ns
tALS
ADV/LD Setup Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Select Setup
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCENH
CEN Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
tWEH
WE, BWx Hold After CLK Rise
0.3
0.4
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.3
0.4
0.5
ns
Notes
18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can
be initiated.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High Z prior to Low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V.
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05353 Rev. *F
Page 21 of 28
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CY7C1462AV33
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Switching Waveforms
1
Figure 7. Read/Write/Timing[24, 25, 26]
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW x
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
In-Out (DQ)
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
24. For this waveform ZZ is tied low.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document #: 38-05353 Rev. *F
Page 22 of 28
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CY7C1462AV33
CY7C1464AV33
Switching Waveforms
1
2
A1
A2
(continued)
Figure 8. NOP, STALL and DESELECT Cycles[24, 25, 27]
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 9. ZZ Mode Timing[28, 29]
CLK
t ZZ
ZZ
I
t
t ZZREC
ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High Z when exiting ZZ sleep mode.
Document #: 38-05353 Rev. *F
Page 23 of 28
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Table 1. Ordering Information
Speed
(MHz)
167
Ordering Code
CY7C1460AV33-167AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1462AV33-167AXC
200
250
CY7C1460AV33-167BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1460AV33-167AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1464AV33-167BGI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-200AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
Commercial
CY7C1460AV33-250AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1460AV33-250BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1460AV33-250AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Package Diagrams
Industrial
Figure 10. 100-Pin TQFP (14 x 20 x 1.4 mm)
51-85050 *C
Document #: 38-05353 Rev. *F
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Package Diagrams
(continued)
Figure 11. 165-Ball FBGA (15 x 17 x 1.4 mm)
51-85165 *B
Document #: 38-05353 Rev. *F
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Package Diagrams
(continued)
Figure 12. 209-Ball FBGA (14 x 22 x 1.76 mm)
51-85167 *A
Document #: 38-05353 Rev. *F
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Document History Page
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05353
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
254911
SYT
See ECN
New Data sheet
Part number changed from previous revision. New and old part
number differ by the letter “A”
*A
303533
SYT
See ECN
Changed H9 pin from VSSQ to VSS on the Pin Configuration table
for 209 FBGA on Page # 5
Changed the test condition from VDD = Min to VDD = Max for VOL
in the Electrical Characteristics table
Replaced ΘJA and ΘJC from TBD to respective Thermal Values
for All Packages on the Thermal Resistance Table
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA
for 250, 200 and 167 MHz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200
and 167 MHz respectively
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 and 160 mA to 200 mA for 250, 200
and 167 MHz respectively
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7
pF for TQFP Package
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for
200 MHz Speed Bin
Added Pb-Free information for 100-pin TQFP and 165 FBGA and
209 BGA packages
*B
331778
SYT
See ECN
Modified Address Expansion balls in the pinouts for 165 FBGA
and 209 BGA Package as per JEDEC standards and updated the
Pin Definitions accordingly
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF
for 165 FBGA Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA
respectively
Updated the Ordering Information by Shading and Unshading
MPNs as per availability
*C
417509
RXU
See ECN
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on
Page# 1 from “3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 and 30 μA to –30 and
5 μA respectively and also Changed IX current value in ZZ from
–30 and 5 μA to –5 and 30 μA respectively on page# 18
Modified test condition from VIH < VDD to VIH < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and
MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the
Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
*D
473229
NXR
See ECN
Added the Maximum Rating for Supply Voltage on VDDQ Relative
to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10
ns in TAP AC Switching Characteristics table
Updated the Ordering Information table.
Document #: 38-05353 Rev. *F
Page 27 of 28
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CY7C1462AV33
CY7C1464AV33
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05353
*E
2756998
VKN
08/28/09
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are
available and modified the disclaimer for the Ordering information.
Updated Package Diagram for spec 51-85165.
*F
2900822
NJY
03/29/2010
Added CY7C1460AV33-167AXI part in Ordering Information
Updated links in Sales, Solutions, and Legal Information
Updated 100-pin TQFP and 209-Ball FBGA package diagrams.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
PSoC Solutions
cypress.com/go/automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
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cypress.com/go/image
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cypress.com/go/psoc
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cypress.com/go/USB
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cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05353 Rev. *F
®
TM
QDR is the registered trademark and NoBL
the trademarks of their respective holders.
Revised March 29, 2010
and No Bus Latency
TM
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are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be
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