CY7C1464AV33-250BGC

PRELIMINARY CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 3.3V power supply • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1460AV33 and CY7C1462AV33 are available in lead-free 100-pin TQFP and 165-Ball fBGA packages; CY7C1464AV33 available in 209-Ball fBGA package • IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/ CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions.The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33 and BWa–BWb for CY7C1462AV33) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram-CY7C1460AV33 (1 Mbit x 36) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BWa BWb BWc BWd WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPa DQPb DQPc DQPd E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL Cypress Semiconductor Corporation Document #: 38-05353 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 19, 2004 PRELIMINARY Logic Block Diagram-CY7C1462AV33 (2 Mbit x 18) A0, A1, A MODE CLK CEN C WRITE ADDRESS REGISTER 1 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPa DQPb E E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Logic Block Diagram-CY7C1464AV33 (512K x 72) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Selection Guide CY7C1460AV33-250 CY7C1462AV33-250 CY7C1464AV33-250 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 475 100 CY7C1460AV33-200 CY7C1462AV33-200 CY7C1464AV33-200 3.2 425 100 CY7C1460AV33-167 CY7C1462AV33-167 CY7C1464AV33-167 3.4 375 100 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05353 Rev. *A Page 2 of 27 PRELIMINARY Pin Configurations 100-pin TQFP Packages A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ V DDQ A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC CY7C1460AV33 (1 Mbit × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1462AV33 (2 Mbit × 18) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC/288M NC/144M NC/288M NC/144M NC/72M MODE A A A A A1 A0 VSS VDD A A A A A A A A NC/72M MODE A A A A A1 A0 Document #: 38-05353 Rev. *A VSS VDD A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 27 PRELIMINARY Pin Configurations (continued) 165-Ball fBGA Pinout CY7C1460AV33 (1 Mbit × 36) 4 5 6 7 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 1 A B C D E F G H J K L M N P R NC/288M NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC/72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 8 ADV/LD 9 A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC/144M DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS CE3 CLK CEN WE OE A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A CY7C1462AV33 (2 Mbit × 18) 1 A B C D E F G H J K L M N P R NC/288M NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC/72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE VSS VSS 8 ADV/LD 9 A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC/144M DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 OE VSS VDD A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A Document #: 38-05353 Rev. *A Page 4 of 27 PRELIMINARY Pin Configurations (continued) 209-Ball PBGA CY7C1464AV33 (512K x 72) 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 CE2 BWSg BWSd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC/72M A A 6 ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BWSf BWSa VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe Pin Definitions Pin Name A0 A1 A BWa BWb BWc BWd BWe BWf BWg BWh WE ADV/LD I/O Type InputSynchronous InputSynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. InputSynchronous InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Document #: 38-05353 Rev. *A Page 5 of 27 PRELIMINARY Pin Definitions (continued) Pin Name CLK CE1 CE2 CE3 OE I/O Type InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Pin Description CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. CEN InputSynchronous I/OSynchronous DQa DQb DQc DQd DQe DQf DQg DQh DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh MODE I/OSynchronous Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO TDI TMS TCK VDD VDDQ VSS NC NC/72M JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous JTAG-Clock Power Supply Ground N/A N/A N/A N/A InputAsynchronous Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. I/O Power Supply Power supply for the I/O circuitry. NC/144M NC/288M ZZ Document #: 38-05353 Rev. *A Page 6 of 27 PRELIMINARY Introduction Functional Overview The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and Document #: 38-05353 Rev. *A CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP for CY7C1464AV33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 & DQa,b/DQPa,b for CY7C1462AV33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP for CY7C1464AV33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h/ DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/ DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is Page 7 of 27 PRELIMINARY driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33 , BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1,A0 00 01 10 11 Second Address A1,A0 01 00 11 10 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1,A0 00 01 10 11 Second Address A1,A0 01 10 11 00 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max 100 2tCYC Unit mA ns ns ns ns Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) Address Used None None External Next External Next External Next CE H X L X L X L X L X ZZ L L L L L L L L L L ADV/LD L H L H L H L H L H WE X X H X H X L X L X BWx X X X X X X L L H H OE X X L L H H X X X X L L L L L L L L L L CEN CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Data Out (Q) Data Out (Q) Tri-State Tri-State Data In (D) Data In (D) Tri-State Tri-State NOP/WRITE ABORT None (Begin Burst) WRITE ABORT (Continue Burst) Next Document #: 38-05353 Rev. *A Page 8 of 27 PRELIMINARY Truth Table[1, 2, 3, 4, 5, 6, 7] Operation IGNORE CLOCK EDGE (Stall) SLEEP MODE Address Used Current CE X ZZ L ADV/LD X WE X BWx X OE X CEN H CLK L-H CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 DQ - None X H X X X X X X Tri-State Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs=data when OE is active. Document #: 38-05353 Rev. *A Page 9 of 27 PRELIMINARY Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1460AV33) Read Write – No bytes written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Bytes b, a Write Byte c – (DQc and DQPc) Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d – (DQd and DQPd) Write Bytes d, a Write Bytes d, b Write Bytes d, b, a Write Bytes d, c Write Bytes d, c, a Write Bytes d, c, b Write All Bytes Function (CY7C1462AV33)[2,8] Read Write – No Bytes Written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Both Bytes Function (CY7C1464AV33)[2,8] Read Write – No Bytes Written Write Byte X − (DQx and DQPx) Write All Bytes WE H L L L L L L L L L L L L L L L L BWd X H H H H H H H H L L L L L L L L WE H L L L L WE H L L L BWc X H H H H L L LL L H H H H L L L L CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 BWb X H H L L H H L L H H L L H H L L BWb x H H L L BWa X H L H L H L H L H L H L H L H L BWa x H L H L BWx x H L All BW = L Note: 8. Table only lists a partial listing of the byte write combinations. Any combinaion of BW[a:d] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05353 Rev. *A Page 10 of 27 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic level. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Data-In (TDI) CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure . TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 Bypass Register 210 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Page 11 of 27 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Document #: 38-05353 Rev. *A PRELIMINARY When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The length of the Boundary Scan Register for the SRAM in different packages is listed in the Scan Register Sizes table. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #89 ( for 165-FBGA package) or bit #138 ( for 209 BGA package). Page 12 of 27 Document #: 38-05353 Rev. *A PRELIMINARY When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK) t TMSS 2 3 4 5 6 t TH t TMSH t TL t CYC Test Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 0 5 5 5 25 25 5 50 20 ns MHz ns ns ns ns ns ns ns Description Min. Max. Unit Output Times Set-up Times Notes: 9.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10.Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns. Document #: 38-05353 Rev. *A Page 13 of 27 PRELIMINARY 3.3V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input rise and fall times ..................... ..............................1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 2.5V TAP AC Test Conditions Input pulse levels ........................................ VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels................... ......................1.25V Output reference levels .................. ..............................1.25V Test load termination supply voltage .................... ........1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50Ω TDO Z O= 50Ω 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50Ω TDO Z O= 50Ω 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd =3.135V to 3.6V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Test Conditions IOH = -4.0 mA,VDDQ = 3.3V IOH = -1.0 mA,VDDQ = 2.5V IOH = -100 µA IOL = 8.0 mA IOL = 1.0 mA IOL = 100 µA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 -0.3 -0.3 -5 Min. 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Max. Unit V V V V V V V V V V V V µA Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[12] Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 (1 Mbit ×36) (2 Mbit ×18) (512K ×72) 000 01011 001000 100111 00000110100 1 000 01011 001000 010111 00000110100 1 000 01011 001000 110111 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Notes: 11. All voltages referenced to VSS (GND). 12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05353 Rev. *A Page 14 of 27 PRELIMINARY Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order-165FBGA Boundary Scan Order- 209BGA Bit Size (×36) 3 1 32 89 Bit Size (×18) 3 1 32 89 - CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Bit Size (×72) 3 1 32 138 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05353 Rev. *A Page 15 of 27 PRELIMINARY 165-Ball fBGA Boundary Scan Order [13] CY7C1460AV33 (1 Mbit x 36) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Ball ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 Bit# 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Ball ID A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bit# 83 84 85 86 87 88 89 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 CY7C1460AV33 (1 Mbit x 36) Ball ID P2 R4 P4 N5 P6 R6 Internal CY7C1462AV33 (2 Mbit x 18) N6 N7 10N P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 D10 C11 Note: 13. Bit# 89 is preset HIGH. Document #: 38-05353 Rev. *A Page 16 of 27 PRELIMINARY 165-Ball fBGA Boundary Scan Order [13] CY7C1462AV33 (2 Mbit x 18) Bit# 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Ball ID A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 Bit# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Document #: 38-05353 Rev. *A Page 17 of 27 PRELIMINARY 209-Ball BGA Boundary Scan Order [13, 14] CY7C1464AV33 (512K x 72) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Ball ID W6 V6 U6 W7 V7 U7 T7 V8 U8 T8 V9 U9 P6 W11 W10 V11 V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 K11 M6 L6 Bit# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Ball ID J6 F6 K8 K9 K10 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 B11 B10 A11 A10 C9 B9 A9 D8 C8 B8 A8 D7 C7 B7 A7 Bit# 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 Note: 14. Bit# 138 is preset HIGH. CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 CY7C1464AV33 (512K x 72) Ball ID D6 G6 H6 C6 B6 A6 A5 B5 C5 D5 D4 C4 A4 B4 C3 B3 A3 A2 A1 B2 B1 C2 C1 D2 D1 E1 E2 F2 F1 G1 G2 H2 H1 J2 J1 Bit# 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Ball ID K1 N6 K3 K4 K6 K2 L2 L1 M2 M1 N2 N1 P2 P1 R2 R1 T2 T1 U2 U1 V2 V1 W2 W1 T6 U3 V3 T4 T5 U4 V4 W5 V5 U5 Internal Document #: 38-05353 Rev. *A Page 18 of 27 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Ambient Temperature VDD VDDQ 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to VDD Electrical Characteristics Over the Operating Range[15, 16] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[15] Input LOW Voltage[15] Input Load Current except ZZ and MODE VDDQ = 3.3V VDDQ = 2.5V VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V VDD = Min., IOH= −1.0 mA, VDDQ = 2.5V VDD = Max., IOL= 8.0 mA, VDDQ = 3.3V VDD = Max., IOL= 1.0 mA, VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND ≤ VI ≤ VDDQ 2.0 1.7 –0.3 –0.3 –5 –5 30 –30 5 –5 5 475 425 375 225 225 225 100 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 5.0-ns cycle, 200 MHz 1/tCYC 6.0-ns cycle, 167 MHz Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V µA µA µA µA µA µA mA mA mA mA mA mA mA Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB2 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = 0 Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5.0-ns cycle, 200 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades ISB3 200 200 200 110 mA mA mA mA ISB4 Shaded areas contain advance information. Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05353 Rev. *A Page 19 of 27 PRELIMINARY Capacitance[17] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V 100 TQFP 6.5 3 5.5 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 165 FBGA 5 5 7 209 FBGA 5 5 7 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω 5 pF INCLUDING JIG AND SCOPE 2.5V Z0 = 50Ω OUTPUT RL = 50Ω VT = 1.25V 5 pF INCLUDING JIG AND SCOPE R =1538Ω R = 351Ω R = 317Ω ALL INPUT PULSES VDDQ 10% GND ≤ 1 ns 90% 90% 10% ≤ 1 ns VT = 1.5V (a) (b) R = 1667Ω VDDQ 10% GND ≤ 1ns (c) ALL INPUT PULSES 90% 90% 10% ≤ 1ns 2.5V I/O Test Load OUTPUT (a) (b) (c) Thermal QJA QJC Resistance[17] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. 100 TQFP 25.21 2.28 165 FBGA 20.8 3.2 209 FBGA 25.31 4.48 Unit °C/W °C/W Parameters Switching Characteristics Over the Operating Range [22, 23] 250 Parameter tPower[18] Clock tCYC FMAX tCH tCL Output Times tCO tEOV tDOH tCHZ Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise Clock to High-Z[19, 20, 21] 1.0 2.6 2.6 2.6 1.5 3.0 3.2 3.0 1.5 3.4 3.4 3.4 ns ns ns ns Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW 1.5 1.5 4.0 250 2.0 2.0 5.0 200 2.4 2.4 6.0 167 ns MHz ns ns Description VCC (typical) to the first access read or write Min. 1 Max. Min. 1 200 Max. Min. 1 167 Max. Unit ms Shaded areas contain advance information. Notes: 17. Tested initially and after any design or process changes that may affect these parameters. 18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated. 19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05353 Rev. *A Page 20 of 27 PRELIMINARY Switching Characteristics Over the Operating Range (continued)[22, 23] 250 Parameter tCLZ tEOHZ tEOLZ Set-up Times tAS tDS tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise Chip Select Set-up 1.2 1.2 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 Clock to Low-Z Description [19, 20, 21] [19, 20, 21] CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 200 Max. 2.6 Min. 1.3 3.0 0 0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max. Min. 1.5 3.4 167 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 1.0 0 OE HIGH to Output High-Z OE LOW to Output Low-Z[19, 20, 21] Switching Waveforms Read/Write/Timing[24,25,26] 1 CLK tCENS tCENH tCH tCL 2 t CYC 3 4 5 6 7 8 9 10 CEN tCES tCEH CE ADV/LD WE BWx ADDRESS tAS A1 tAH A2 tDS tDH A3 A4 tCO tCLZ tDOH A5 tOEV A6 tCHZ A7 Data In-Out (DQ) D(A1) D(A2) D(A2+1) Q(A3) Q(A4) tOEHZ Q(A4+1) D(A5) Q(A6) tDOH OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) tOELZ READ Q(A6) WRITE D(A7) DESELECT DON’T CARE UNDEFINED Notes: 24. For this waveform ZZ is tied low. 25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional. Document #: 38-05353 Rev. *A Page 21 of 27 PRELIMINARY Switching Waveforms (continued) NOP,STALL and DESELECT Cycles[24,25,27] 1 2 3 CLK CEN CE ADV/LD WE BWx ADDRESS A1 A2 A3 A4 A5 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 4 5 6 7 8 9 10 tCHZ Data In-Out (DQ) WRITE D(A1) READ Q(A2) STALL D(A1) Q(A2) Q(A3) D(A4) Q(A5) READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT DON’T CARE UNDEFINED ZZ ModeTiming[28,29] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 29. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05353 Rev. *A Page 22 of 27 PRELIMINARY Ordering Information Speed (MHz) 250 Ordering Code CY7C1460AV33-250AXC CY7C1462AV33-250AXC CY7C1460AV33-250BZC CY7C1462AV33-250BZC CY7C1464AV33-250BGC CY7C1460AV33-250BZXC CY7C1462AV33-250BZXC CY7C1464AV33-250BGXC 200 CY7C1460AV33-200AXC CY7C1462AV33-200AXC CY7C1460AV33-200BZC CY7C1462AV33-200BZC CY7C1464AV33-200BGC CY7C1460AV33-200BZXC CY7C1462AV33-200BZXC CY7C1464AV33-200BGXC 167 CY7C1460AV33-167AXC CY7C1462AV33-167AXC CY7C1460AV33-167BZC CY7C1462AV33-167BZC CY7C1464AV33-167BGC CY7C1460AV33-167BZXC CY7C1462AV33-167BZXC CY7C1464AV33-167BGXC Shaded areas contain advance information. CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Package Name A101 BB165C BB209A BB165C BB209A A101 BB165C BB209A BB165C BB209A A101 BB165C BB209A BB165C BB209A Package Type Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm) Operating Range Commercial Document #: 38-05353 Rev. *A Page 23 of 27 PRELIMINARY Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 51-85050-*A Document #: 38-05353 Rev. *A Page 24 of 27 PRELIMINARY Package Diagrams (continued) 165-Ball FBGA (15 x 17 x 1.40 mm) BB165C CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B PIN 1 CORNER Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B A B D E F G 1.00 C C D E F G 17.00±0.10 H J K 14.00 H J K M N P R 7.00 L L M N P R A 5.00 10.00 0.53±0.05 0.25 C +0.05 -0.10 1.00 0.35 0.15 C B 0.15(4X) 15.00±0.10 SEATING PLANE C 0.36 1.40 MAX. 51-85165-*A Document #: 38-05353 Rev. *A Page 25 of 27 PRELIMINARY Package Diagrams (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) BB209A CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 51-85167-** ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05353 Rev. *A Page 26 of 27 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 REV. ** ECN No. 254911 Issue Date See ECN Orig. of Change SYT Description of Change New Datasheet Part number changed from previous revision. New and old part number differ by the letter “A” Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on Page # 5 Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical Characteristics table. Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200 and 167 Mhz respectively Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167 Mhz respectively. Changed ISB2 from 80 mA to 100 mA for all frequencies Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 Mhz respectively. Changed ISB4 from 100 mA to 110 mA for all frequencies Changed CIN ,CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package. Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz Speed Bin Added lead-free information for 100-Pin TQFP and 165 FBGA and 209 BGA packages *A 303533 See ECN SYT Document #: 38-05353 Rev. *A Page 27 of 27