CY7C1471BV33
CY7C1473BV33
72-Mbit (2M × 36/4M × 18)
Flow-Through SRAM
with NoBL™ Architecture
72-Mbit (2M × 36/4M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No bus latency™ (NoBL™) architecture eliminates dead cycles
between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
■
Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte write capability
■
3.3 V/2.5 V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■
Clock enable (CEN) pin to enable clock and suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable (OE)
■
CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball
fine-pitch ball grid array (FBGA) package. CY7C1473BV33
available in JEDEC-standard Pb-free 100-pin thin quad flat
pack (TQFP)
The CY7C1471BV33 and CY7C1473BV33 are 3.3 V,
2M × 36/4M × 18 synchronous flow through burst SRAMs
designed specifically to support unlimited true back-to-back read
or write operations without the insertion of wait states. The
CY7C1471BV33 and CY7C1473BV33 are equipped with the
advanced No Bus Latency (NoBL) logic. NoBL™ is required to
enable consecutive read or write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
■
Three chip enables (CE1, CE2, CE3) for simple depth
expansion
■
Automatic power-down feature available using ZZ mode or CE
deselect
■
IEEE 1149.1 JTAG boundary scan compatible
■
Burst capability – linear or interleaved burst order
■
Low standby power
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
133 MHz
Unit
Maximum access time
Description
6.5
ns
Maximum operating current
305
mA
Maximum CMOS standby current
120
mA
Cypress Semiconductor Corporation
Document Number: 001-15029 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2018
CY7C1471BV33
CY7C1473BV33
Logic Block Diagram – CY7C1471BV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
CE
C
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
BW C
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
INPUT
REGISTER
OE
CE1
CE2
CE3
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1473BV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
CE
C
ADV/LD
C
BURST
LOGIC
A1'
Q1
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 001-15029 Rev. *K
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQPB
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 32
CY7C1471BV33
CY7C1473BV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Truth Table for Read/Write ............................................ 11
Truth Table for Read/Write ............................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Document Number: 001-15029 Rev. *K
TAP AC Switching Characteristics ............................... 17
TAP Timing ...................................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Exit Order ............................................. 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 3 of 32
CY7C1471BV33
CY7C1473BV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
40
41
42
43
44
45
46
47
48
49
50
VDD
A
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
Document Number: 001-15029 Rev. *K
81
A
82
A
83
A
84
ADV/LD
85
OE
CEN
90
87
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
BWC
96
BWB
BWD
97
95
CE2
98
A
CE1
86
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1471BV33
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
CY7C1471BV33 (2M × 36)
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 4 of 32
CY7C1471BV33
CY7C1473BV33
Pin Configurations (continued)
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
40
41
42
43
44
45
46
47
48
49
50
VDD
A
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
Document Number: 001-15029 Rev. *K
81
A
82
A
83
A
84
ADV/LD
85
OE
CEN
87
90
WE
VSS
91
88
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
CE2
97
96
CE1
A
98
86
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1473BV33
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
CY7C1473BV33 (4M × 18)
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 5 of 32
CY7C1471BV33
CY7C1473BV33
Pin Configurations (continued)
Figure 3. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1471BV33 (2M × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWC
BWB
CE3
CEN
ADV/LD
A
A
NC
R
NC/1G
A
CE2
BWD
BWA
CLK
WE
OE
A
A
NC
DQPC
VDDQ
VSS
VSS
NC
DQPB
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VSS
DQC
NC
DQC
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC/144M
A
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC/288M
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 001-15029 Rev. *K
Page 6 of 32
CY7C1471BV33
CY7C1473BV33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
Synchronous A[1:0] is fed to the two-bit burst counter.
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD Synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Advances the on-chip address counter or loads a new address. When HIGH (and
Synchronous CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded
into the device for an access. After deselection, drive ADV/LD LOW to load a new address.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
Asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “Sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronous data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Strap Pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power Supply Power supply inputs to the core of the device.
VDDQ
VSS
TDO
I/O Power
Supply
Ground
Power supply for the I/O circuitry.
Ground for the device.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not used, this pin must be left unconnected. This pin is not available on TQFP packages.
output
Synchronous
Document Number: 001-15029 Rev. *K
Page 7 of 32
CY7C1471BV33
CY7C1473BV33
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available on
input
Synchronous TQFP packages.
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
input
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Functional Overview
The CY7C1471BV33, and CY7C1473BV33 are synchronous
flow through burst SRAMs designed specifically to eliminate wait
states during write-read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. Maximum access delay from the clock rise
(tCDV) is 6.5 ns (133 MHz device).
Accesses may be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If (CEN)
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). Byte Write Select (BWX) can be used to conduct
Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
WE is deasserted HIGH
■
ADV/LD is asserted LOW
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
Document Number: 001-15029 Rev. *K
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is tri-stated immediately.
Burst Read Accesses
The CY7C1471BV33, and CY7C1473BV33 have an on-chip
burst counter that enables the user to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW to load a new address into
the SRAM, as described in the Single Read Access section. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wrap around
when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for Byte Write operations, see section Truth Table for
Read/Write on page 11 for details), input is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1471BV33, and CY7C1473BV33 provide
Byte Write capability that is described in the section Truth Table
for Read/Write on page 11. The input WE with the selected BWX
input selectively writes to only the desired bytes. Bytes not
selected during a Byte Write operation remain unaltered. A
synchronous self timed write mechanism is provided to simplify
the write operations. Byte write capability is included to greatly
simplify read/modify/write sequences, which can be reduced to
simple byte write operations.
Page 8 of 32
CY7C1471BV33
CY7C1473BV33
Because the CY7C1471BV33, and CY7C1473BV33 are
common I/O devices, do not drive data into the device when the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs. Doing
so tri-states the output drivers. As a safety precaution, DQs and
DQPX are automatically tri-stated during the data portion of a
write cycle, regardless of the state of OE.
CE1, CE2, and CE3, must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Write Accesses
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
00
11
10
The CY7C1471BV33, CY7C1473BV33 have an on-chip burst
counter that enables the user to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in section Single Write Accesses on page
8. When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. Drive the correct BWX
inputs in each cycle of the burst write to write the correct bytes
of data.
Linear Burst Address Table
Sleep Mode
(MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
Fourth
Address
A1:A0
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-15029 Rev. *K
Page 9 of 32
CY7C1471BV33
CY7C1473BV33
Truth Table
The truth table for CY7C1471BV33, and CY7C1473BV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-state
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-state
Read cycle (begin burst)
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-state
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-state
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
Write cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/Write abort (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-state
Write abort (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-state
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Read cycle (continue burst)
NOP/Dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects
are asserted, see section Truth Table for Read/Write on page 11 for details.
2. Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 11.
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected with the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 001-15029 Rev. *K
Page 10 of 32
CY7C1471BV33
CY7C1473BV33
Truth Table for Read/Write
The read/write truth table for CY7C1471BV33 follows. [8, 9, 10]
Function (CY7C1471BV33)
WE
BWa
BWb
BWc
BWd
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all bytes
L
L
L
L
L
Truth Table for Read/Write
The read/write truth table for CY7C1473BV33 follows. [8, 9, 10]
Function (CY7C1473BV33)
WE
BWa
BWb
Read
H
X
X
Write – No bytes written
L
H
H
Write byte a – (DQa and DQPa)
L
L
H
Write byte b – (DQb and DQPb)
L
H
L
Write both bytes
L
L
L
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects
are asserted, see section Truth Table for Read/Write on page 11 for details.
9. Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 11.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.
Document Number: 001-15029 Rev. *K
Page 11 of 32
CY7C1471BV33
CY7C1473BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1471BV33 incorporate a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion places
an added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
The CY7C1471BV33 contain a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
must be left unconnected. During power-up, the device comes
up in a reset state, which does not interfere with the operation of
the device.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. This ball may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram on
page 14. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
During power-up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge
of TCK.
instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. During power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows the shifting of data through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the section Identification Register
Definitions on page 18.
Document Number: 001-15029 Rev. *K
Page 12 of 32
CY7C1471BV33
CY7C1473BV33
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail in this section.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which must be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
during power-up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
Document Number: 001-15029 Rev. *K
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal when in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state when
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 32
CY7C1471BV33
CY7C1473BV33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
Document Number: 001-15029 Rev. *K
1
0
PAUSE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
Page 14 of 32
CY7C1471BV33
CY7C1473BV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TM S
Document Number: 001-15029 Rev. *K
TAP CONTROLLER
Page 15 of 32
CY7C1471BV33
CY7C1473BV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels .............................................. VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [11]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Test Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Input HIGH voltage
Input LOW voltage
Input load current
GND < VIN < VDDQ
Note
11. All voltages refer to VSS (GND).
Document Number: 001-15029 Rev. *K
Page 16 of 32
CY7C1471BV33
CY7C1473BV33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
–
5
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
Setup Times
Hold Times
TAP Timing
Figure 4. TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
UNDEFINED
Notes
12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-15029 Rev. *K
Page 17 of 32
CY7C1471BV33
CY7C1473BV33
Identification Register Definitions
CY7C1471BV33
(2M × 36)
Instruction Field
Revision number (31:29)
Device depth (28:24)
000
[14]
01011
Description
Describes the version number
Reserved for internal use
Architecture/memory type (23:18)
001001
Defines memory type and architecture
Bus width/density (17:12)
100100
Defines width and density
Cypress JEDEC ID code (11:1)
00000110100
ID register presence indicator (0)
1
Enables unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary scan order – 165-ball FBGA
71
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to High Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1 compliant.
RESERVED
101
Do not use: This instruction is reserved for future use.
RESERVED
110
Do not use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-15029 Rev. *K
Page 18 of 32
CY7C1471BV33
CY7C1473BV33
Boundary Scan Exit Order
(2M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
2
D1
22
P2
41
J11
61
B7
42
K10
62
B6
3
E1
23
R4
43
J10
63
A6
4
D2
24
P6
44
H11
64
B5
5
E2
25
R6
45
G11
65
A5
6
F1
26
R8
46
F11
66
A4
7
G1
27
P3
47
E11
67
B4
8
F2
28
P4
48
D10
68
B3
9
G2
29
P8
49
D11
69
A3
10
J1
30
P9
50
C11
70
A2
11
K1
31
P10
51
G10
71
B2
12
L1
32
R9
52
F10
13
J2
33
R10
53
E10
14
M1
34
R11
54
A9
15
N1
35
N11
55
B9
16
K2
36
M11
56
A10
17
L2
37
L11
57
B10
18
M2
38
M10
58
A8
19
R1
39
L10
59
B8
20
R2
40
K11
60
A7
Document Number: 001-15029 Rev. *K
Page 19 of 32
CY7C1471BV33
CY7C1473BV33
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65C to +150C
Ambient temperature
with power applied ................................... –55C to +125C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Range
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied
to outputs in tri-state .........................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [15, 16]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
[15]
Input HIGH voltage
Test Conditions
Min
Max
Unit
3.135
3.6
V
For 3.3 V I/O
3.135
VDD
V
For 2.5 V I/O
2.375
2.625
V
For 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
For 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
For 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
For 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
For 3.3 V I/O
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 3.3 V I/O
–0.3
0.8
V
For 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
Input LOW voltage
[15]
Input current of ZZ
Input = VDD
–
A
30
A
IOZ
Output leakage current
GND VI VDD, output disabled
–5
5
A
IDD [17]
VDD operating supply current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns
cycle, 133
MHz
–
305
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX, inputs switching
7.5 ns
cycle, 133
MHz
–
200
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 7.5 ns
VIN 0.3 V or VIN > VDD – 0.3 V, cycle, 133
f = 0, inputs static
MHz
–
120
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 7.5 ns
VIN 0.3 V or VIN > VDDQ – 0.3 cycle, 133
MHz
V, f = fMAX, inputs switching
–
200
mA
Notes
15. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
16. TPower-up: assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15029 Rev. *K
Page 20 of 32
CY7C1471BV33
CY7C1473BV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [15, 16]
ISB4
Description
Test Conditions
VDD = Max, device deselected, 7.5 ns
VIN VDD – 0.3 V or VIN 0.3 V, cycle, 133
MHz
f = 0, inputs static
Automatic CE power-down
current – TTL inputs
Min
Max
Unit
–
165
mA
Capacitance
Parameter [18]
Description
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
6
6
pF
5
5
pF
Control input capacitance
8
8
pF
CCLK
Clock input capacitance
6
6
pF
CI/O
I/O capacitance
5
5
pF
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
TA = 25C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
Thermal Resistance
Parameter [18]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, according to EIA/JESD51.
24.63
16.3
C/W
2.28
2.1
C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VL = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VL = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-15029 Rev. *K
Page 21 of 32
CY7C1471BV33
CY7C1473BV33
Switching Characteristics
Over the Operating Range
Parameter [19]
Description
tPOWER [20]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.5
–
ns
3.0
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[21, 22, 23]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [21, 22, 23]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[21, 22, 23]
OE HIGH to output high Z
[21, 22, 23]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.5
–
ns
tWES
WE, BWX setup before CLK rise
1.5
–
ns
tCENS
CEN setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
19. Unless otherwise noted in the following table, timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. Test conditions shown in part (a)
of Figure 5 on page 21 unless otherwise noted.
20. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation is initiated.
21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 5 on page 21. Transition is measured ±200 mV from steady-state voltage.
22. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High Z before Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 001-15029 Rev. *K
Page 22 of 32
CY7C1471BV33
CY7C1473BV33
Switching Waveforms
Figure 5. Read/Write Timing [24, 25, 26]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-15029 Rev. *K
Page 23 of 32
CY7C1471BV33
CY7C1473BV33
Switching Waveforms (continued)
Figure 6. NOP, STALL, and DESELECT Cycles [27, 28, 29]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
27. For this waveform ZZ is tied LOW.
28. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
29. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-15029 Rev. *K
Page 24 of 32
CY7C1471BV33
CY7C1473BV33
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See the Truth Table on page 10 for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-15029 Rev. *K
Page 25 of 32
CY7C1471BV33
CY7C1473BV33
Ordering Information
Table 1 lists the CY7C1471BV33, CY7C1473BV33 key package features and ordering codes. The table contains only the parts that
are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit
the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 1. CY7C1471BV33, CY7C1473BV33 Key Features and Ordering Information
Speed
(MHz)
133
Ordering Code
Package
Diagram
Package
CY7C1471BV33-133BZI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1471BV33-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Ranges
Industrial
Commercial
CY7C1473BV33-133AXC
Ordering Code Definitions
CY 7
C
14XX
B
V33 - 133 XX
X
X
Temperature Range: X = I or C
I = Industrial; C = Commercial
Pb-free
Package Type: XX = BZ or A
BZ = 165-ball FBGA
A = 100-pin TQFP
Speed Grade: 133 MHz
V33 = 3.3 V
Die Revision
Part Identifier: 14XX = 1471 or 1473
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-15029 Rev. *K
Page 26 of 32
CY7C1471BV33
CY7C1473BV33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-15029 Rev. *K
Page 27 of 32
CY7C1471BV33
CY7C1473BV33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *E
Document Number: 001-15029 Rev. *K
Page 28 of 32
CY7C1471BV33
CY7C1473BV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CEN
Clock Enable
CMOS
Complementary Metal-Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
FBGA
Fine-Pitch Ball Grid Array
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
JTAG
Joint Test Action Group
ms
millisecond
LSB
Least Significant Bit
mV
millivolt
MSB
Most Significant Bit
ns
nanosecond
OE
Output Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-15029 Rev. *K
Symbol
Unit of Measure
Page 29 of 32
CY7C1471BV33
CY7C1473BV33
Document History Page
Document Title: CY7C1471BV33/CY7C1473BV33, 72-Mbit (2M × 36/4M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15029
Rev.
ECN
Orig. of
Change
Submission
Date
**
1024500
VKN /
KKVTMP
05/01/2007
New data sheet.
*A
1274731
VKN /
AESA
07/18/2007
Updated Switching Waveforms (Updated Figure 6 (Corrected typo)).
*B
2183566
VKN /
PYRS
03/06/2008
Changed status from Preliminary to Final.
Updated Electrical Characteristics (Added Note 17 and referred the same note
in IDD parameter).
*C
2898663
NJY
03/24/2010
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85165 – Changed revision from *A to *B.
spec 51-85167 – Changed revision from ** to *A.
*D
2905600
VKN
04/06/2010
Updated Ordering Information (Updated part numbers).
*E
3298193
OSN
06/30/2011
Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
spec 51-85165 – Changed revision from *B to *C.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*F
3436299
PRIT
11/15/2011
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85165 – Changed revision from *C to *D.
spec 51-85167 – Changed revision from *A to *B.
Updated to new template.
*G
3628180
PRIT
05/25/2012
Updated Features (Removed CY7C1475BV33 related information, removed
209-ball FBGA package related information, removed 165-ball FBGA package
related information (Corresponding to CY7C1473BV33)).
Updated Functional Description (Removed CY7C1475BV33 related
information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Removed Logic Block Diagram – CY7C1475BV33.
Updated Pin Configurations (Updated Figure 3 (Removed CY7C1475BV33
related information), removed 209-ball FBGA package related information).
Updated Pin Definitions.
Updated Functional Overview (Removed CY7C1475BV33 related
information).
Updated Truth Table (Removed CY7C1475BV33 related information).
Updated Truth Table for Read/Write (Removed CY7C1475BV33 related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1473BV33, CY7C1475BV33 related information).
Updated Identification Register Definitions (Removed CY7C1473BV33,
CY7C1475BV33 related information).
Updated Scan Register Sizes (Removed Bit Size (× 18), and Bit Size (× 72)
columns).
Removed Boundary Scan Exit Order (Corresponding to CY7C1473BV33).
Document Number: 001-15029 Rev. *K
Description of Change
Page 30 of 32
CY7C1471BV33
CY7C1473BV33
Document History Page (continued)
Document Title: CY7C1471BV33/CY7C1473BV33, 72-Mbit (2M × 36/4M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15029
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*G (cont.)
3628180
PRIT
05/25/2012
Updated Electrical Characteristics (Removed 117 MHz frequency related
information).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Package Diagrams (Removed 209-ball FBGA package related
information (spec 51-85167 Rev. *B)).
Completing Sunset Review.
*H
4489161
PRIT
08/31/2014
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
*I
4569232
PRIT
11/14/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
4812510
PRIT
06/26/2015
Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*K
6029208
CNX
01/12/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-15029 Rev. *K
Page 31 of 32
CY7C1471BV33
CY7C1473BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-15029 Rev. *K
Revised January 12, 2018
Page 32 of 32
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