CY7C1471V33
72-Mbit (2M × 36) Flow-Through SRAM
with NoBL™ Architecture
72-Mbit (2M × 36) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
■
Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte Write capability
■
3.3 V/2.5 V I/O supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock enable (CEN) pin to enable clock and suspend operation
■
Synchronous self timed writes
■
Asynchronous output enable (OE)
■
CY7C1471V33 available in JEDEC-standard Pb-free 100-pin
TQFP
■
Three chip enables (CE1, CE2, CE3) for simple depth
expansion
■
Automatic power down feature available using ZZ mode or CE
deselect
■
Burst capability – linear or interleaved burst order
■
Low standby power
The CY7C1471V33 is 3.3 V, 2M × 36 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33 is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle.Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four byte write select
(BWX) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
133 MHz
Unit
Maximum access time
Description
6.5
ns
Maximum operating current
305
mA
Maximum CMOS standby current
120
mA
Errata: For information on silicon errata, see Errata on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05288 Rev. *V
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 12, 2018
CY7C1471V33
Logic Block Diagram – CY7C1471V33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
BW C
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05288 Rev. *V
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 24
CY7C1471V33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Document Number: 38-05288 Rev. *V
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
Product Status ........................................................... 19
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 3 of 24
CY7C1471V33
Pin Configurations
A
40
41
42
43
44
45
46
47
48
49
50
A
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
81
A
82
A
83
A
84
ADV/LD
85
OE
CEN
90
87
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
BWC
96
BWB
BWD
97
95
CE2
98
A
CE1
86
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1471V33
A
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 19.
Document Number: 38-05288 Rev. *V
Page 4 of 24
CY7C1471V33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous A[1:0] are fed to the two-bit burst counter.
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Advances the on-chip address counter or loads a new address. When HIGH (and
synchronous CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded
into the device for an access. After being deselected, ADV/LD should must driven LOW to load a new
address.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select or deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select or deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select or deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device is deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ[2]
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input strap pin Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power
supply
VSS
Ground
NC
–
Power supply for the I/O circuitry.
Ground for the device.
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 19.
Document Number: 38-05288 Rev. *V
Page 5 of 24
CY7C1471V33
Functional Overview
The CY7C1471V33 is synchronous flow through burst SRAMs
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns
(133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If (CEN)
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). Byte write select (BWX) can be used to conduct
byte write operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are all asserted active
■
WE is deasserted HIGH
■
ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is be tri-stated immediately.
Burst Read Accesses
The CY7C1471V33 have an on-chip burst counter that enables
the user to supply a single address and conduct up to four reads
without reasserting the address inputs. ADV/LD must be driven
LOW to load a new address into the SRAM, as described in the
Single Read Accesses section. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
Document Number: 38-05288 Rev. *V
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for Byte Write operations, see Truth Table for
Read/Write on page 9 for details) inputs is latched into the device
and
the
write
is
complete.
Additional
accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1471V33 provides Byte Write capability that
is described in the Truth Table for Read/Write on page 9. The
input WE with the selected BWX input selectively writes to only
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self timed write
mechanism has been provided to simplify the write operations.
Byte write capability is included to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1471V33 are common I/O devices, data must
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQPX inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPX are automatically
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
Burst Write Accesses
The CY7C1471V33 have an on-chip burst counter that enables
the user to supply a single address and conduct up to four write
operations without reasserting the address inputs. ADV/LD must
be driven LOW to load the initial address, as described in the
Single Write Accesses section. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the burst
write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Page 6 of 24
CY7C1471V33
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05288 Rev. *V
Page 7 of 24
CY7C1471V33
Truth Table
The truth table for CY7C1471V33 follows. [3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-state
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-state
Read cycle (begin burst)
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-state
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-state
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
Write cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/write abort (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-state
Write abort (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-state
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see Truth Table for Read/Write on page 9 for details.
4. Write is defined by BWX, and WE. See Truth Table for Read/Write on page 9.
5. When a Write cycle is detected, all I/Os are tri-stated, even during byte writes.
6. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. CEN = H, inserts wait states.
8. Device powers up deselected with the I/Os in a tri-state condition, regardless of OE.
9. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 38-05288 Rev. *V
Page 8 of 24
CY7C1471V33
Truth Table for Read/Write
The read-write truth table for CY7C1471V33 follows. [10, 11, 12]
Function
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write no bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all bytes
L
L
L
L
L
Notes
10. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see Truth Table for Read/Write for details.
11. Write is defined by BWX, and WE. See Truth Table for Read/Write.
12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.
Document Number: 38-05288 Rev. *V
Page 9 of 24
CY7C1471V33
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VDD
VDDQ
Commercial
0 C to +70 C
3.3 V– 5% / 2.5 V – 5%
+ 10%
to VDD
Electrical Characteristics
Over the Operating Range
Parameter [13, 14]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
[13]
Test Conditions
Min
Max
Unit
3.135
3.6
V
For 3.3 V I/O
3.135
VDD
V
For 2.5 V I/O
2.375
2.625
V
For 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
For 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
For 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
For 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
For 3.3 V I/O
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 3.3 V I/O
–0.3
0.8
V
For 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input LOW voltage
[13]
Input current of ZZ
IOZ
Output leakage current
GND VI VDD, output disabled
–5
5
A
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
305
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX, inputs switching
7.5 ns cycle,
133 MHz
–
200
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 7.5 ns cycle,
VIN 0.3 V or VIN > VDD – 0.3 V, 133 MHz
f = 0, inputs static
–
120
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 7.5 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX, inputs switching
–
200
mA
ISB4
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, 7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
165
mA
Notes
13. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
14. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05288 Rev. *V
Page 10 of 24
CY7C1471V33
Capacitance
Parameter [15]
Description
Test Conditions
100-pin TQFP
Package
Unit
6
pF
5
pF
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
Control input capacitance
8
pF
CCLK
Clock input capacitance
6
pF
CIO
Input/Output capacitance
5
pF
Thermal Resistance
Parameter [15]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP Unit
Max
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51.
24.63
C/W
2.28
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VL = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VL = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05288 Rev. *V
Page 11 of 24
CY7C1471V33
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
tPOWER [18]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.5
–
ns
3.0
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[19, 20, 21]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [19, 20, 21]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[19, 20, 21]
OE HIGH to output high Z
[19, 20, 21]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.5
–
ns
tWES
WE, BWX setup before CLK rise
1.5
–
ns
tCENS
CEN setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
16. Unless otherwise noted in the following table, timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
18. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) ofFigure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
20. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z before low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 38-05288 Rev. *V
Page 12 of 24
CY7C1471V33
Switching Waveforms
Figure 3. Read/Write Timing [22, 23, 24]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
24. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05288 Rev. *V
Page 13 of 24
CY7C1471V33
Switching Waveforms (continued)
Figure 4. NOP, STALL and DESELECT Cycles [25, 26, 27]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05288 Rev. *V
Page 14 of 24
CY7C1471V33
Switching Waveforms (continued)
Figure 5. ZZ Mode Timing [28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05288 Rev. *V
Page 15 of 24
CY7C1471V33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1471V33-133AXC
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY
7
C 1471 V33 - 133 A
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
3.3 V VDD
Part Identifier: 1471 = FT, 2Mb × 36 (72Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05288 Rev. *V
Page 16 of 24
CY7C1471V33
Package Diagrams
Figure 6. 100-pin TQFP (16 × 22 × 1.6 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05288 Rev. *V
Page 17 of 24
CY7C1471V33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
NoBL
No Bus Latency
mm
millimeter
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
mV
millivolt
TQFP
Thin Quad Flat Pack
ns
nanosecond
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05288 Rev. *V
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 18 of 24
CY7C1471V33
Errata
This section describes the Ram9 NoBL ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
72Mb-Ram9 NoBL SRAMs: CY7C147*V33
100-pin TQFP
Commercial
Product Status
All of the devices in the Ram9 72Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 72Mb NoBL family devices.
Item
1.
Issues
ZZ Pin
Description
Device
Fix Status
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
72M-Ram9 (90 nm)
For the 72M Ram9 (90 nm)
devices, this issue was fixed in
the new revision. Please
contact your local sales rep for
availability.
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
Fix was done for the 72M RAM9 NoBL SRAMs devices. Fixed devices have a new revision. The following table lists the devices
affected and the new revision after the fix.
Table 1. List of Affected Devices and the new revision
Revision before the Fix
New Revision after the Fix
CY7C147*V33
CY7C147*BV33
Document Number: 38-05288 Rev. *V
Page 19 of 24
CY7C1471V33
Document History Page
Document Title: CY7C1471V33, 72-Mbit (2M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05288
Rev.
ECN
Orig. of
Change
Submission
Date
**
114675
PKS
08/06/2002
New data sheet.
*A
121521
CJM
02/07/2003
Changed status from Advanced Information to Preliminary.
Updated Features (for package offering).
Updated Ordering Information (Updated part numbers).
*B
223721
NJY
05/14/2004
Updated Features (Removed 150 MHz frequency related information).
Updated Functional Description (Removed 150 MHz frequency related
information).
Updated Logic Block Diagram (Splitted Logic Block Diagram into three Logic
Block Diagrams).
Updated Selection Guide (Removed 150 MHz frequency related information).
Updated Functional Overview (Removed 150 MHz frequency related
information).
Updated Boundary Scan Exit Order (Replaced TBD with values for all
packages).
Updated Electrical Characteristics (Removed 150 MHz frequency related
information; replaced TBD with values for maximum values of IDD, ISB1, ISB2,
ISB3, ISB4 parameters).
Updated Capacitance (Replaced TBD with values for all packages).
Updated Thermal Resistance (Replaced TBD with values for all packages).
Updated Switching Characteristics (Removed 150 MHz frequency related
information).
Updated Switching Waveforms.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85165 – Changed revision from ** to *A.
Removed spec 51-85115 *B.
Removed spec 51-85143 *B.
Added spec 51-85167 **.
*C
235012
RYQ
06/17/2004
Minor Change (To match on the spec system and external web).
*D
243572
NJY
07/20/2004
Updated Pin Configurations:
Updated Figure “165-Ball FBGA (15 × 17 × 1.40 mm) pinout (3 Chip Enable
with JTAG)” (Changed ball H2 from VDD to NC).
Updated Figure “209-ball BGA (14 × 22 × 1.76 mm) pinout” (Changed ball R11
from DQPa to DQPe).
Updated Capacitance (Splitted CIN parameter into CADDRESS, CDATA, CCLK
parameters; and also updated the values).
*E
299511
SYT
12/14/2004
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated Electrical Characteristics (Removed 117 MHz frequency related
information).
Updated Thermal Resistance (Changed value of JA from 16.8 C/W to
24.63 C/W; changed value of JC from 3.3 C/W to 2.28 C/W for 100-pin
TQFP package).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (Removed 117 MHz
frequency related information, added Pb-free information for 100-pin TQFP,
165-ball FBGA and 209-ball BGA Packages); added comment of “Pb-free BG
packages availability” below the Ordering Information).
*F
320197
PCI
02/15/2005
Updated Ordering Information (No change in part numbers; removed comment
of “Pb-free BG packages availability” below the Ordering Information).
Document Number: 38-05288 Rev. *V
Description of Change
Page 20 of 24
CY7C1471V33
Document History Page (continued)
Document Title: CY7C1471V33, 72-Mbit (2M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05288
Rev.
ECN
Orig. of
Change
Submission
Date
*G
331513
PCI
03/09/2005
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated Pin Definitions (Added Address Expansion pins).
Updated Operating Range (Added Industrial Operating Range).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters).
Updated Ordering Information (Updated part numbers).
*H
416221
RXU
12/22/2005
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Features (Removed 100 MHz frequency related information and
added 117 MHz frequency related information).
Updated Selection Guide (Removed 100 MHz frequency related information
and added 117 MHz frequency related information).
Updated Electrical Characteristics (Removed 100 MHz frequency related
information and added 117 MHz frequency related information; updated Note
14 (Changed VIH < VDD to VIH < VDD); changed description of IX parameter
from Input Load Current except ZZ and MODE to Input Leakage Current except
ZZ and MODE; changed minimum value of IX parameter (corresponding to
Input Current of MODE (Input = VSS)) from –5 A to –30 A; changed maximum
value of IX parameter (corresponding to Input Current of MODE (Input = VDD))
from 30 A to 5 A; changed minimum value of IX parameter (corresponding
to Input Current of ZZ (Input = VSS)) from –30 A to –5 A; changed maximum
value of IX parameter (corresponding to Input Current of ZZ (Input = VDD)) from
5 A to 30 A).
Updated Switching Characteristics (Removed 100 MHz frequency related
information and added 117 MHz frequency related information).
Updated Ordering Information (Updated part numbers; replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated to new template.
*I
472335
VKN
06/27/2006
Updated Pin Configurations:
Updated Figure “209-ball FBGA (14 × 22 × 1.76 mm) pinout” (Corrected the
ball name for H9 to VSS from VSSQ).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH,
tTL parameters from 25 ns to 20 ns; changed maximum value of tTDOV
parameters from 5 ns to 10 ns).
Updated Maximum Ratings (Added “Supply Voltage on VDDQ Relative to GND”
and its corresponding details).
Updated Ordering Information (Updated part numbers).
*J
1274732
VKN /
AESA
07/18/2007
Updated Switching Waveforms (Updated Figure 4 (Corrected typo)).
*K
2898501
NJY
03/24/2010
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85165 – Changed revision from *A to *B.
spec 51-85167 – Changed revision from ** to *A.
*L
3034798
NJY
09/21/2010
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05288 Rev. *V
Description of Change
Page 21 of 24
CY7C1471V33
Document History Page (continued)
Document Title: CY7C1471V33, 72-Mbit (2M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05288
Rev.
ECN
Orig. of
Change
Submission
Date
*M
3357114
PRIT
08/29/2011
Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
spec 51-85165 – Changed revision from *B to *C.
spec 51-85167 – Changed revision from *A to *B.
Completing Sunset Review.
*N
3633894
PRIT
06/01/2012
Updated Features (Removed CY7C1473V33, CY7C1475V33 related
information; removed 165-ball FBGA package, 209-ball FBGA package related
information).
Updated Functional Description (Removed CY7C1473V33, CY7C1475V33
related information; removed the Note “For best practice recommendations,
refer to the Cypress application note AN1064, SRAM System Guidelines.” and
its reference).
Updated Selection Guide (Removed 117 MHz frequency related information).
Removed Logic Block Diagram – CY7C1473V33.
Removed Logic Block Diagram – CY7C1475V33.
Updated Pin Configurations (Removed CY7C1473V33, CY7C1475V33 related
information; removed 165-ball FBGA package, 209-ball FBGA package related
information).
Updated Pin Definitions (Removed JTAG related information).
Updated Functional Overview (Removed CY7C1473V33, CY7C1475V33
related information).
Updated Truth Table (Removed CY7C1473V33, CY7C1475V33 related
information).
Removed Truth Table for Read/Write (Corresponding to CY7C1473V33,
CY7C1475V33).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Exit Order (Corresponding to CY7C1471V33,
CY7C1473V33, CY7C1475V33).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 117 MHz frequency related
information).
Updated Capacitance (Removed 165-ball FBGA package, 209-ball FBGA
package related information).
Updated Thermal Resistance (Removed 165-ball FBGA package, 209-ball
FBGA package related information).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Package Diagrams:
Removed spec 51-85165 *C.
Removed spec 51-85167 *B.
*O
3766472
PRIT
10/04/2012
No technical updates.
Completing Sunset Review.
*P
3970182
PRIT
04/18/2013
Added Errata.
Document Number: 38-05288 Rev. *V
Description of Change
Page 22 of 24
CY7C1471V33
Document History Page (continued)
Document Title: CY7C1471V33, 72-Mbit (2M × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05288
Rev.
ECN
Orig. of
Change
Submission
Date
*Q
4038218
PRIT
06/24/2013
Added Errata Footnotes.
Updated to new template.
*R
4146627
PRIT
10/04/2013
Updated Errata.
*S
4539205
PRIT
10/15/2014
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*T
4572829
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*U
5513955
PRIT
11/08/2016
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*V
6068055
RMES
02/12/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05288 Rev. *V
Description of Change
Page 23 of 24
CY7C1471V33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2002-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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Document Number: 38-05288 Rev. *V
Revised February 12, 2018
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
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