CY7C1470V25 CY7C1472V25 CY7C1474V25
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 2.5V power supply • 2.5V/1.8V I/O supply (VDDQ) • Fast clock-to-output times — 3.0 ns (for 250-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1470V25, CY7C1472V25 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1474V25 available in lead-free and non-lead-free 209 ball FBGA package • IEEE 1149.1 JTAG Boundary Scan compatible • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWh for CY7C1474V25, BWa–BWd for CY7C1470V25 and BWa–BWb for CY7C1472V25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Logic Block Diagram-CY7C1470V25 (2M x 36)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2
C
ADV/LD
BWa BWb BWc BWd
WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
DQs DQPa DQPb DQPc DQPd
E
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3
ZZ
READ LOGIC
SLEEP CONTROL
Cypress Semiconductor Corporation Document #: 38-05290 Rev. *I
•
198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised June 21, 2006
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Logic Block Diagram-CY7C1472V25 (4M x 18)
A0, A1, A MODE CLK CEN C
WRITE ADDRESS REGISTER 1
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 2
ADV/LD BWa BWb WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
DQs DQPa DQPb
E
E
INPUT REGISTER 1 E
INPUT REGISTER 0 E
OE CE1 CE2 CE3 ZZ
READ LOGIC
Sleep Control
Logic Block Diagram-CY7C1474V25 (1M x 72)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2
C
ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
E
DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh
WE
INPUT REGISTER 1 E INPUT REGISTER 0 E
OE CE1 CE2 CE3
ZZ
READ LOGIC
Sleep Control
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Pin Configurations 100-pin TQFP Pinout
A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1470V25 (2M × 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CY7C1472V25 (4M × 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0
NC(288) NC(144)
MODE A A A A A1 A0
VSS VDD
NC(288) NC(144)
A A A A A A A A A
Document #: 38-05290 Rev. *I
VSS VDD
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470V25 (2M x 36)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC/144M MODE
2
A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD
9
A
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa
OE
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/288M
A
A
A
A
CY7C1472V25 (4M x 18)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC/144M MODE
2
A A NC DQb DQb DQb DQb NC NC NC NC NC NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE VSS VSS
8
ADV/LD
9
A
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
OE VSS
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
NC/288M
A
A
A
A
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474V25 (1M x 72)
1 A B C D E F G H J K L M N P R T U V W
DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd
2
DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd
3
A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC/144M A TMS
4
CE2 BWSg BWSd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI
5
A NC NC/576M NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
6
ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0
7
A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSf BWSa VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC/288M A TCK
10
DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe
11
DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
Pin Definitions
Pin Name A0 A1 A BWa BWb BWc BWd BWe BWf BWg BWh WE I/O Type InputSynchronous InputSynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Pin Definitions (continued)
Pin Name ADV/LD I/O Type InputSynchronous Pin Description Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQh are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[71:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
CLK CE1 CE2 CE3 OE
InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous I/OSynchronous
DQs
DQPX
I/OSynchronous
MODE
Input Strap Pin
TDO
JTAG Serial Output Synchronous
TDI TMS TCK VDD VDDQ VSS NC NC(144M, 288M, 576M, 1G) ZZ
JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous JTAG Clock Power Supply Ground – – Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and 1G densities. ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Page 6 of 28
I/O Power Supply Power supply for the I/O circuitry.
InputAsynchronous
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Functional Overview The CY7C1470V25/CY7C1472V25/CY7C1474V25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A Read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a Read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment Document #: 38-05290 Rev. *I the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The Write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP for CY7C1474V25, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 & DQa,b/DQPa,b for CY7C1472V25) (or a subset for Byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for CY7C1470V25 and BWa,b for CY7C1472V25) signals. The CY7C1470V25/CY7C1472V25/CY7C1474V25 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25) are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for Page 7 of 28
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CY7C1470V25 CY7C1472V25 CY7C1474V25
CY7C1474V25, BWa,b,c,d for CY7C1470V25 and BWa,b for CY7C1472V25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First Address A1,A0 00 01 10 11 Second Address A1,A0 01 10 11 00 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 00 01 10
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1,A0 00 01 10 11 Second Address A1,A0 01 00 11 10 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 10 01 00
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 120 2tCYC Unit mA ns ns ns ns
Truth Table [1, 2, 3, 4, 5, 6, 7]
Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address Used None None External Next External Next External Next None Next Current None CE H X L X L X L X L X X X ZZ L L L L L L L L L L L H ADV/LD WE L H L H L H L H L H X X X X H X H X L X L X X X BWx X X X X X X L L H H X X OE X X L L H H X X X X X X CEN L L L L L L L L L L H X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X DQ Tri-State Tri-State Data Out (Q) Data Out (Q) Tri-State Tri-State Data In (D) Data In (D) Tri-State Tri-State – Tri-State
Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details. 3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles.During a Read cycle DQs and DQP[a:d] = Tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1470V25) Read Write – No bytes written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Bytes b, a Write Byte c – (DQc and DQPc) Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d – (DQd and DQPd) Write Bytes d, a Write Bytes d, b Write Bytes d, b, a Write Bytes d, c Write Bytes d, c, a Write Bytes d, c, b Write All Bytes Function (CY7C1472V25) Read Write – No Bytes Written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Both Bytes WE H L L L L L L L L L L L L L L L L BWd X H H H H H H H H L L L L L L L L WE H L L L L BWc X H H H H L L LL L H H H H L L L L BWb x H H L L BWb X H H L L H H L L H H L L H H L L BWa X H L H L H L H L H L H L H L H L BWa x H L H L
Function (CY7C1474V25) Read Write – No Bytes Written Write Byte X − (DQx and DQPx) Write All Bytes
WE H L L L
BWx x H L All BW = L
Note: 8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write will be done based on which Byte Write is active.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V or 1.8V I/O logic levels. The CY7C1470V25/CY7C1472V25/CY7C1474V25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0 Bypass Register
210
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
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Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still
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possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON’T CARE UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 0 5 5 5 20 20 10 50 20 ns MHz ns ns ns ns ns ns ns Description Min. Max. Unit
Output Times
Set-up Times
Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 2.5V Input rise and fall time..................................................... 1 ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V
1.8V TAP AC Test Conditions
Input pulse levels..................................... 0.2V to VDDQ – 0.2 Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 0.9V Output reference levels .................................................. 0.9V Test load termination supply voltage .............................. 0.9V
2.5V TAP AC Output Load Equivalent
1.25V 50Ω TDO Z O= 50Ω 20pF
1.8V TAP AC Output Load Equivalent
0.9V 50Ω TDO Z O= 50Ω 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND ≤ VI ≤ VDDQ Test Conditions IOH = –1.0 mA IOH = –100 µA IOL = 1.0 mA IOL = 100 µA VDDQ = 2.5V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V 1.7 1.26 –0.3 –0.3 –5 Min. 1.7 2.1 1.6 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.36 5 Max. Unit V V V V V V V V V V µA
Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1470V25 (2M x 36) 000 01011 001000 100100 00000110100 1 CY7C1472V25 (4M x 18) 000 01011 001000 010100 00000110100 1 CY7C1474V25 (1M x 72) 000 01011 001000 110100 00000110100 1 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register
Note: 11. All voltages referenced to VSS (GND).
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Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order–165FBGA Boundary Scan Order–209BGA Bit Size (x36) 3 1 32 71 – Bit Size (x18) 3 1 32 52 – Bit Size (x72) 3 1 32 – 110
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD Code 000 001 010 011 100 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
RESERVED RESERVED BYPASS
101 110 111
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Boundary Scan Exit Order (2M x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 165-Ball ID R3 P2 R4 P6 R6 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 L10 K11 Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 165-Ball ID J11 K10 J10 H11 G11 F11 E11 D10 D11 C11 G10 F10 E10 A9 B9 A10 B10 A8 B8 A7 Bit # 61 62 63 64 65 66 67 68 69 70 71 165-Ball ID B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2
Boundary Scan Exit Order (4M x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 Bit # 14 15 16 17 18 19 20 21 22 23 24 25 26 165-Ball ID R4 P6 R6 R8 P3 P4 P8 P9 P10 R9 R10 R11 M10 Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 165-Ball ID L10 K10 J10 H11 G11 F11 E11 D11 C11 A11 A9 B9 A10 Bit # 40 41 42 43 44 45 46 47 48 49 50 51 52 165-Ball ID B10 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2
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Boundary Scan Exit Order (1M x 72)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 209-Ball ID A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 L1 L2 M1 M2 N1 N2 P1 P2 R2 R1 Bit # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 209-Ball ID T1 T2 U1 U2 V1 V2 W1 W2 T6 V3 V4 U4 W5 V6 W6 V5 U5 U6 W7 V7 U7 V8 V9 W11 W10 V11 V10 U11 Bit # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 209-Ball ID U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 P6 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 Bit # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 209-Ball ID B11 B10 A11 A10 A7 A5 A9 U8 A6 D6 K6 B6 K3 A8 B4 B3 C3 C4 C8 C9 B9 B8 A4 C6 B7 A3
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD VDDQ
2.5V –5%/+5% 1.7V to VDD
Electrical Characteristics Over the Operating Range[12, 13]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12] Input Leakage Current except ZZ and MODE for 2.5V I/O for 1.8V I/O for 2.5V I/O, IOH= −1.0 mA for 1.8V I/O, IOH = –100 µA for 2.5V I/O, IOL= 1.0 mA for 1.8V I/O, IOL= 100 µA for 2.5V I/O for 1.8V I/O for 2.5V I/O for 1.8V I/O GND ≤ VI ≤ VDDQ 1.7 1.26 –0.3 –0.3 –5 –30 5 –5 30 –5 5 450 450 400 200 200 200 120 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, 4.0-ns cycle, 250MHz VIN ≥ VIH or VIN ≤ VIL, 5.0-ns cycle, 200 MHz f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz All speed grades Test Conditions Min. 2.375 2.375 1.7 2.0 1.6 0.4 0.2 VDD + 0.3V VDD + 0.3V 0.7 0.36 5 Max. 2.625 VDD 1.9 Unit V V V V V V V V V V V µA µA µA µA µA µA mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
ISB2
ISB3
Automatic CE Max. VDD, Device Deselected, Power-down VIN ≤ 0.3V or Current—CMOS Inputs VIN > VDDQ − 0.3V, f = 0 Automatic CE Max. VDD, Device Deselected, Power-down VIN ≤ 0.3V or Current—CMOS Inputs VIN > VDDQ − 0.3V, f = fMAX = 1/tCYC Automatic CE Power-down Current—TTL Inputs
4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz
200 200 200 135
mA mA mA mA
ISB4
Max. VDD, Device Deselected, All speed grades VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes: 12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 13. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[14]
Parameter CADDRESS CDATA CCTRL CCLK CI/O Description Address Input Capacitance Data Input Capacitance Control Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V 100 TQFP Max. 6 5 8 6 5 165 FBGA 209 FBGA Max. Max. 6 5 8 6 5 6 5 8 6 5 Unit pF pF pF pF pF
Thermal Resistance[14]
Parameter ΘJA ΘJC Description Test Conditions 100 TQFP Package 24.63 2.28 165 FBGA Package 16.3 2.1 209 FBGA Package 15.2 1.7 Unit °C/W °C/W
Thermal Resistance Test conditions follow standard (Junction to Ambient) test methods and procedures for Thermal Resistance measuring thermal impedance, per EIA/JESD51. (Junction to Case)
AC Test Loads and Waveforms
2.5V I/O Test Load
OUTPUT Z0 = 50Ω 2.5V OUTPUT RL = 50Ω 5 pF VL = 1.25V R = 1538Ω R = 1667Ω VDDQ 10% GND ≤ 1 ns ALL INPUT PULSES 90% 90% 10% ≤ 1 ns
(a) 1.8V I/O Test Load
OUTPUT Z0 = 50Ω 1.8V
INCLUDING JIG AND SCOPE
(b)
(c)
R = 14 KΩ VDDQ - 0.2 10% 5 pF 0.2 R = 14 KΩ ≤ 1 ns ALL INPUT PULSES 90% 90% 10% ≤ 1 ns
OUTPUT RL = 50Ω VL =0.9V
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
Note: 14. Tested initially and after any design or process changes that may affect these parameters.
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Switching Characteristics Over the Operating Range
Parameter tPower tCYC FMAX tCH tCL Output Times tCO tOEV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-up Times tAS tDS tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise Chip Select Set-up 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise Clock to Clock to High-Z[18, 19, 20] Low-Z[18, 19, 20] High-Z[18, 19, 20] 0 1.3 3.0 0 1.3 3.0 1.3 3.0 0 3.0 3.0 1.3 3.0 1.5 3.4 3.0 3.0 1.5 3.4 3.4 3.4 ns ns ns ns ns ns ns
[17] [15, 16]
–250 Description VCC (typical) to the First Access Read or Write Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW 2.0 2.0 Min. 1 4.0 250 2.0 2.0 Max. 1 5.0
–200 Min. Max. 1 6.0 200 2.2 2.2
–167 Min. Max. Unit ms ns 167 MHz ns ns
Clock
OE HIGH to Output
OE LOW to Output Low-Z[18, 19, 20]
Notes: 15. Timing reference is 1.25V when VDDQ = 2.5V and 0.9V when VDDQ = 1.8V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested.
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Switching Waveforms
Read/Write/Timing[21, 22, 23]
1 CLK
tCENS tCENH
2
t CYC
3
4
5
6
7
8
9
10
tCH
tCL
CEN
tCES tCEH
CE ADV/LD WE BWx ADDRESS
tAS
A1
tAH
A2
tDS tDH
A3
A4
tCO tCLZ tDOH
A5
tOEV
A6
tCHZ
A7
Data In-Out (DQ)
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tOEHZ
Q(A4+1)
D(A5)
Q(A6)
tDOH
OE
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5)
tOELZ
READ Q(A6)
WRITE D(A7)
DESELECT
DON’T CARE
UNDEFINED
Notes: 21. For this waveform ZZ is tied LOW. 22. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 23. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[21, 22, 24]
1
CLK CEN CE ADV/LD WE BWx ADDRESS A1
2
3
4
5
6
7
8
9
10
A2
A3
A4
A5
tCHZ
Data In-Out (DQ)
WRITE D(A1) READ Q(A2) STALL
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
READ Q(A3)
WRITE D(A4)
STALL
NOP
READ Q(A5)
DESELECT
CONTINUE DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[25, 26]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes: 24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle. 25. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 26. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1470V25-167AXC CY7C1472V25-167AXC CY7C1470V25-167BZC CY7C1472V25-167BZC CY7C1470V25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V25-167BZXC CY7C1474V25-167BGC CY7C1474V25-167BGXC CY7C1470V25-167AXI CY7C1472V25-167AXI CY7C1470V25-167BZI CY7C1472V25-167BZI CY7C1470V25-167BZXI CY7C1472V25-167BZXI CY7C1474V25-167BGI CY7C1474V25-167BGXI 200 CY7C1470V25-200AXC CY7C1472V25-200AXC CY7C1470V25-200BZC CY7C1472V25-200BZC CY7C1470V25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V25-200BZXC CY7C1474V25-200BGC CY7C1474V25-200BGXC CY7C1470V25-200AXI CY7C1472V25-200AXI CY7C1470V25-200BZI CY7C1472V25-200BZI CY7C1470V25-200BZXI CY7C1472V25-200BZXI CY7C1474V25-200BGI CY7C1474V25-200BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1470V25-250AXC CY7C1472V25-250AXC CY7C1470V25-250BZC CY7C1472V25-250BZC CY7C1470V25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1472V25-250BZXC CY7C1474V25-250BGC CY7C1474V25-250BGXC CY7C1470V25-250AXI CY7C1472V25-250AXI CY7C1470V25-250BZI CY7C1472V25-250BZI CY7C1470V25-250BZXI CY7C1472V25-250BZXI CY7C1474V25-250BGI CY7C1474V25-250BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20 14.00±0.10
100 1 81 80
1.40±0.05
0.30±0.08
22.00±0.20
20.00±0.10
0.65 TYP.
30 31 50 51
12°±1° (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0° MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0°-7°
R 0.08 MIN. 0.20 MAX.
0.60±0.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05290 Rev. *I
0.10
R 0.08 MIN. 0.20 MAX.
Page 24 of 28
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) (51-85165)
BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
PIN 1 CORNER
A B
A B
D E F G
1.00
C
C D E F G
17.00±0.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.53±0.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.00±0.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
Document #: 38-05290 Rev. *I
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Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05290 Rev. *I
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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Document History Page
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 REV. ** *A ECN No. 114677 121519 Issue Date 08/06/02 01/27/03 Orig. of Change PKS CJM New data sheet Updated features for package offering Removed 300-MHz offering Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz), tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns to 1.3 ns (200 MHz) Updated ordering information Changed Advanced Information to Preliminary Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250-MHz offering and included 225-MHz speed bin Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering Minor Change: The data sheets do not match on the spec system and external web Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to DQPa,DQa,DQa,DQa,DQa in page 4 Modified capacitance values in page 19 Removed 225-MHz offering and included 250-MHz speed bin Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 19 Added lead-free information for 100-Pin TQFP and 165 FBGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Corrected typo in part numbers on page# 9 and 10 Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Industrial Operating Range Modified VOL, VOH Test Conditions Updated Ordering Information Table Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-state to Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 17 Changed the IX current values of MODE on page # 17 from –5 µA and 30 µA to –30 µA and 5 µA Changed the IX current values of ZZ on page # 17 from –30 µA and 5 µA to –5 µA and 30 µA Changed VDDQ < VDD to VDDQ < VDD on page #17 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information table Description of Change
*B
223721
See ECN
NJY
*C *D
235012 243572
See ECN See ECN
RYQ NJY
*E
299511
See ECN
SYT
*F *G
320197 331513
See ECN See ECN
PCI PCI
*H
416221
See ECN
RXU
Document #: 38-05290 Rev. *I
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CY7C1470V25 CY7C1472V25 CY7C1474V25
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 *I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for H9 to VSS from VSSQ). Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table.
Document #: 38-05290 Rev. *I
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