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CY7C1481BV33
72-Mbit (2M × 36) Flow-Through SRAM
72-Mbit (2M × 36) Flow-Through SRAM
Features
Functional Description
■
Supports 133 MHz bus operations
■
2M × 36 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O supply (VDDQ)
■
Fast clock to output time
❐ 6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
CY7C1481BV33 available in JEDEC standard Pb-free 100-pin
TQFP and 119-ball Pb-free BGA package.
■
IEEE 1149.1 JTAG compatible boundary scan
■
ZZ sleep mode option
The CY7C1481BV33 is a 3.3 V, 2M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE1), depth expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1481BV33 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1481BV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
133 MHz
Unit
Maximum Access Time
Description
6.5
ns
Maximum Operating Current
335
mA
Maximum CMOS Standby Current
150
mA
Cypress Semiconductor Corporation
Document Number: 001-74857 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 7, 2018
CY7C1481BV33
Logic Block Diagram – CY7C1481BV33
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-74857 Rev. *J
Page 2 of 30
CY7C1481BV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port (TAP) ............................................. 10
PERFORMING A TAP RESET .................................. 10
TAP REGISTERS ...................................................... 10
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 14
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
Document Number: 001-74857 Rev. *J
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
Boundary Scan Exit Order ............................................. 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Electrical Characteristics ............................................... 18
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 19
Switching Characteristics .............................................. 20
Timing Diagrams ............................................................ 21
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Page 3 of 30
CY7C1481BV33
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1481BV33
(2M × 36)
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Figure 2. 119-ball BGA pinout
1
CY7C1481BV33 (2M X36)
3
4
5
A
A
ADSP
A
VDDQ
2
A
B
C
NC/288M
NC/144M
CE2
A
A
A
ADSC
VDD
A
A
A
A
NC/512M
NC/1G
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
L
DQD
DQD
NC
DQA
VDDQ
DQD
DQA
VDDQ
N
DQD
DQD
VSS
BWE
A1
BWA
VSS
DQA
M
BWD
VSS
VSS
DQA
DQA
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
A
TMS
A
TDI
A
TCK
A
TDO
A
NC
ZZ
VDDQ
Document Number: 001-74857 Rev. *J
GW
VDD
CLK
6
A
7
VDDQ
Page 4 of 30
CY7C1481BV33
Pin Definitions
Pin Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA, BWB,
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
CLK
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
InputClock
Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter
when ADV is asserted LOW during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
InputZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence,
the first clock when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating,
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
Document Number: 001-74857 Rev. *J
Page 5 of 30
CY7C1481BV33
Pin Definitions (continued)
Pin Name
VDD
VDDQ
VSS
VSSQ[1]
I/O
Description
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
I/O Ground Ground for the I/O Circuitry.
TDO
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
is not used, this pin must be left unconnected. This pin is not available on TQFP packages.
Output
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input
this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on
Synchronous TQFP packages.
TMS
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG Clock Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Note
1. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the I/O circuitry.
Document Number: 001-74857 Rev. *J
Page 6 of 30
CY7C1481BV33
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1481BV33 supports secondary cache in systems
using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user selectable and is
determined by sampling the MODE input. Accesses are initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
2-bit on-chip wraparound burst counter captures the first address
in a burst sequence and automatically increments the address
for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic. It is then presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQs is written into the
specified address location. The device allows byte writes. All
I/Os are tri-stated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
before the data is presented to DQs. As a safety precaution, the
data lines are tri-stated after a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1481BV33 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to an interleaved burst sequence.
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed.
The device must be deselected before entering the “sleep”
mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Single Write Accesses Initiated by ADSP
00
01
10
11
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 9 for appropriate states that indicate a write) on the next
clock rise, the appropriate data is latched and written into the
device. The device allows byte writes. All I/Os are tri-stated
during a byte write. Because this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/Os
must be tri-stated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tri-stated after a write cycle
is detected, regardless of the state of OE.
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
Single Write Accesses Initiated by ADSC
10
11
00
01
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
11
00
01
10
Document Number: 001-74857 Rev. *J
Page 7 of 30
CY7C1481BV33
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
150
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Truth Table
The truth table for CY7C1481BV33 follows. [2, 3, 4, 5, 6]
Cycle Description
Address Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
L–H Tri-State
Deselected Cycle, Power Down
None
X
X
H
L
H
L
X
X
X
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
D
Q
Notes
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-74857 Rev. *J
Page 8 of 30
CY7C1481BV33
Truth Table for Read/Write
The read-write truth table for CY7C1481BV33 follows. [7, 8]
Function (CY7C1481BV33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
7. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
8. Table only includes a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active.
Document Number: 001-74857 Rev. *J
Page 9 of 30
CY7C1481BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1481BV33 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion places
an added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC standard 3.3 V or 2.5 V
I/O logic levels.
The CY7C1481BV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information on loading the
instruction register, see the TAP Controller State Diagram on
page 12. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
Whether the output is active depends on the current state of the
TAP state machine (see Identification Codes on page 16). The
output changes on the falling edge of TCK. TDO is connected to
the least significant bit (LSB) of any register.
TAP Registers
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls, as shown in the TAP Controller Block Diagram
on page 13. At power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that is placed between the TDI and
TDO balls. This shifts the data through the SRAM with minimal
delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The × 36 configuration has a
73-bit long register.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions are used to
capture the contents of the I/O ring.
The Boundary Scan Exit Order on page 17 show the order in
which the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
Performing a TAP Reset
To perform a RESET, force TMS HIGH (VDD) for five rising edges
of TCK. This RESET does not affect the operation of the SRAM
and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Document Number: 001-74857 Rev. *J
Page 10 of 30
CY7C1481BV33
TAP Instruction Set
SAMPLE/PRELOAD
Overview
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed
whenever the instruction register is loaded with all zeros.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
Be aware that the TAP controller clock only operates at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction is loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
IDCODE
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction loads a vendor specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
BYPASS
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
Document Number: 001-74857 Rev. *J
Page 11 of 30
CY7C1481BV33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-74857 Rev. *J
Page 12 of 30
CY7C1481BV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TM S
Document Number: 001-74857 Rev. *J
TAP CONTROLLER
Page 13 of 30
CY7C1481BV33
TAP Timing
Figure 3 shows the TAP timing diagram.
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK )
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH Time
20
–
ns
tTL
TCK Clock LOW Time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-74857 Rev. *J
Page 14 of 30
CY7C1481BV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
TDO
50Ω
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [11]
VOH1
Description
Output HIGH Voltage
Min
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
Conditions
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
–
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3 V
2.9
VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VOL2
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
GND < VIN < VDDQ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
11. All voltages refer to VSS (GND).
Document Number: 001-74857 Rev. *J
Page 15 of 30
CY7C1481BV33
Identification Register Definitions
Bit# 24 is “1” in the ID Register definitions for both 2.5 V and 3.3 V versions of the device.
CY7C1481BV33
(2M × 36)
Instruction Field
Revision Number (31:29)
000
Device Depth (28:24)
01011
Architecture/Memory Type (23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number
Reserved for internal use
000001
Defines memory type and architecture
100100
Defines width and density
00000110100
ID Register Presence Indicator (0)
Description
1
Enables unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
Bypass
1
ID
32
Boundary Scan Order – 165-ball FBGA
73
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-74857 Rev. *J
Page 16 of 30
CY7C1481BV33
Boundary Scan Exit Order
(2M × 36) - 119-Ball ID
Bit #
119-ball ID
Bit #
119-ball ID
Bit #
119-ball D
Bit #
119-ball ID
1
D2
21
R2
41
N6
61
F4
2
F2
22
T2
42
K6
62
M4
3
E1
23
C2
43
L7
63
H4
4
E2
24
N4
44
L6
64
K4
5
D1
25
P4
45
K7
65
VSS
6
G1
26
B6
46
T7
66
L5
7
H2
27
B2
47
H6
67
G5
8
H1
28
T5
48
F6
68
G3
9
G2
29
T6
49
G7
69
L3
10
P2
30
C3
50
E6
70
VDD
11
K2
31
R6
51
D6
71
E4
12
L1
32
C5
52
E7
72
A2
13
L2
33
A5
53
H7
73
B3
14
M2
34
C6
54
G6
15
N1
35
T3
55
D7
16
N2
36
B5
56
A6
17
P1
37
P6
57
A3
18
K1
38
N7
58
G4
19
R3
39
M6
59
A4
20
T4
40
P7
60
B4
Document Number: 001-74857 Rev. *J
Page 17 of 30
CY7C1481BV33
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch Up Current ................................................... >200 mA
Operating Range
Ambient
Temperature
Commercial
0 °C to +70 °C
Industrial
–40 °C to +85 °C
Range
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
VDD
Power Supply Voltage
VDDQ
IO Supply Voltage
VOH
VOL
VIH
VIL
IX
IOZ
IDD [14]
Test Conditions
For 3.3 V I/O
For 2.5 V I/O
Output HIGH Voltage
For 3.3 V I/O, IOH = –4.0 mA
For 2.5 V I/O, IOH = –1.0 mA
Output LOW Voltage
For 3.3 V I/O, IOL = 8.0 mA
For 2.5 V I/O, IOL = 1.0 mA
Input HIGH Voltage[12]
For 3.3 V I/O
For 2.5 V I/O
Input LOW Voltage[12]
For 3.3 V I/O
For 2.5 V I/O
Input Leakage Current Except ZZ GND VI VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
Output Leakage Current
GND VI VDD, Output Disabled
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
7.5 ns cycle,
f = fMAX = 1/tCYC
133 MHz
ISB1
Automatic CE Power Down
Current – TTL Inputs
ISB2
Automatic CE Power Down
Current – CMOS Inputs
ISB3
Automatic CE Power Down
Current – CMOS Inputs
ISB4
Automatic CE Power Down
Current – TTL Inputs
Min
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
Max
Unit
3.6
V
VDD
V
2.625
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3 V
V
VDD + 0.3 V
V
0.8
V
0.7
V
5
A
–30
–
–5
–
–5
–
–
5
–
30
5
335
A
A
A
A
A
mA
7.5 ns cycle,
133 MHz
–
200
mA
7.5 ns cycle,
133 MHz
–
150
mA
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
Max VDD, Device Deselected, 7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
200
mA
–
165
mA
Max VDD, Device Deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
Notes
12. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
13. TPower-up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-74857 Rev. *J
Page 18 of 30
CY7C1481BV33
Capacitance
Parameter [15]
Description
Test Conditions
100-pin TQFP
Max
119-Ball BGA
Unit
6
6
pF
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CADDRESS
Address Input Capacitance
CDATA
Data Input Capacitance
5
5
pF
CCTRL
Control Input Capacitance
8
8
pF
CCLK
Clock Input Capacitance
6
6
pF
CIO
Input/Output Capacitance
5
5
pF
Thermal Resistance
Parameter [15]
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
100-pin TQFP
Package
119-ball BGA
Package
Unit
24.63
15.85
C/W
2.28
1.44
C/W
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3V IO Test Load
R = 317
3.3V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VL = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5V IO Test Load
R = 1667
2.5V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VL = 1.25V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74857 Rev. *J
Page 19 of 30
CY7C1481BV33
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
tPOWER
Description
VDD(typical) to the First Access [18]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.5
–
ns
Clock to Low Z
[19, 20, 21]
3.0
–
ns
tCHZ
Clock to High Z
[19, 20, 21]
–
3.8
ns
tOEV
OE LOW to Output Valid
–
3.0
ns
0
–
ns
–
3.0
ns
tCLZ
tOELZ
tOEHZ
OE LOW to Output Low Z
[19, 20, 21]
OE HIGH to Output High Z
[19, 20, 21]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.5
–
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup
1.5
–
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
–
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Notes
16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted.
18. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage.
20. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. The device is designed to
achieve High Z before Low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 001-74857 Rev. *J
Page 20 of 30
CY7C1481BV33
Timing Diagrams
Figure 5. Read Cycle Timing [22]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE, BWX
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 001-74857 Rev. *J
Page 21 of 30
CY7C1481BV33
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [23, 24]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE, BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 001-74857 Rev. *J
Page 22 of 30
CY7C1481BV33
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [25, 26, 27]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
WES
t
A5
A6
WEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
D(A5)
Q(A2)
Back-to-Back READs
D(A6)
t CDV
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
26. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH.
Document Number: 001-74857 Rev. *J
Page 23 of 30
CY7C1481BV33
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
29. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-74857 Rev. *J
Page 24 of 30
CY7C1481BV33
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
CY7C1481BV33-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
lndustrial
CY7C1481BV33-133BGXI
51-85181 119-ball FBGA (14 × 22 × 1.96 mm) Pb-free
lndustrial
Ordering Code Definitions
CY 7
C
1481 B V33 - 133 XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP (3 chip enable); BG = 119-ball FBGA
Speed Grade: 133 MHz
V33 = 3.3 V VDD
Die Revision: B errata fix PCN084636
Part Identifier: 1481 = SCD, 2Mb × 36 (72Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-74857 Rev. *J
Page 25 of 30
CY7C1481BV33
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
A1
0.05
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.20
c
L1
INCLUDE MOLD PROTRUSION/END FLASH.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-74857 Rev. *J
Page 26 of 30
CY7C1481BV33
Figure 10. 119-ball FBGA (14 × 22 × 1.96 mm) Package Outline, 51-85181
51-85181 *D
Document Number: 001-74857 Rev. *J
Page 27 of 30
CY7C1481BV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
FBGA
Fine-Pitch Ball Grid Array
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
mV
millivolt
TQFP
Thin Quad Flat Pack
ns
nanosecond
TTL
Transistor-Transistor Logic
Document Number: 001-74857 Rev. *J
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 28 of 30
CY7C1481BV33
Document History Page
Document Title: CY7C1481BV33, 72-Mbit (2M × 36) Flow-Through SRAM
Document Number: 001-74857
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
3466988
GOPA
01/17/2012
New data sheet.
*A
3508574
GOPA
01/25/2012
Changed status from Preliminary to Final.
*B
3862706
PRIT
01/09/2013
No technical updates.
Completing Sunset Review.
*C
4575228
PRIT
11/20/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*D
5071457
PRIT
01/04/2016
Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*E
5309766
PRIT
06/15/2016
Updated Truth Table:
Replaced “X” with “H” in CE3 column corresponding to “Deselected Cycle,
Power Down” in fifth row.
Updated to new template.
*F
6010395
CNX
01/02/2018
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Completing Sunset Review.
*G
6129830
NILE
04/13/2018
Removed 165-ball FBGA package related information in all instances across
the document.
Added 119-ball BGA package related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Removed spec 51-85165 *E.
Added spec 51-85181 *D.
Completing Sunset Review.
*H
6175306
NILE
05/18/2018
Updated Pin Configurations:
Updated Figure 2 (Replaced “CY7C1361C (256K × 36)” with
“CY7C1361BV33 (256K × 36)”).
Updated to new template.
*I
6197618
VINI
06/06/2018
Updated Pin Configurations:
Updated Figure 2 (Replaced “CY7C1361BV33 (256K × 36)” with
“CY7C1481BV33 (256K × 36)”).
*J
6085132
NILE
08/07/2018
Updated Figure 2: Fixed the device density to 2M X36.
Document Number: 001-74857 Rev. *J
Page 29 of 30
CY7C1481BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/arm
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cypress.com/clocks
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cypress.com/iot
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cypress.com/mcu
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-74857 Rev. *J
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation.
Revised August 7, 2018
Page 30 of 30
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