CY7C1481V33 CY7C1483V33 CY7C1487V33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Features
• • • • • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 3.3V core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times
Functional Description[1]
The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.
— 6.5 ns (133 MHz version) • Provide high-performance 2-1-1-1 access rate • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self timed write • Asynchronous output enable • CY7C1481V33, CY7C1483V33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V33 available in Pb-free and non-Pb-free 209 ball FBGA package • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode option
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 335 150 100 MHz 8.5 305 150 Unit ns mA mA
Note 1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 38-05284 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised May 01, 2007
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Logic Block Diagram – CY7C1481V33 (2M x 36)
A 0, A1, A
ADDRESS REGISTER A [1:0]
MODE
ADV CLK
BURST Q1 COUNTER AND LOGIC Q0 CLR
ADSC ADSP DQ D , DQP D BW D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE REGISTER DQ A , DQP A BW A BWE GW CE1 CE2 CE3 OE DQ A , DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQ D , DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BW B BYTE WRITE REGISTER
BW C
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
DQ s DQP A DQP B DQP C DQP D
ENABLE REGISTER
INPUT REGISTERS
ZZ
SLEEP CONTROL
Logic Block Diagram – CY7C1483V33 (4M x 18)
A0,A1,A MODE
ADDRESS REGISTER
A[1:0]
ADV CLK
BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC
ADSP DQ B ,DQP B WRITE REGISTER DQ B ,DQP B WRITE DRIVER
BW B
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
BW A BWE GW
DQ A ,DQP A WRITE REGISTER
DQ A ,DQP A WRITE DRIVER INPUT REGISTERS
DQs DQP A DQP B
CE 1 CE 2 CE 3
OE
ENABLE REGISTER
ZZ
SLEEP CONTROL
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Logic Block Diagram – CY7C1487V33 (1M x 72)
ADDRESS REGISTER
A[1:0]
A0, A1,A
MODE ADV CLK Q1 BINARY COUNTER CLR Q0
ADSC ADSP
BW H
DQ H , DQPH WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ E , DQPE WRITE DRIVER DQ D, DQPD WRITE DRIVER
DQ H , DQPH WRITE DRIVER DQ G , DQPG WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ E , DQPE BYTE “a” WRITE DRIVER DQ D, DQPD WRITE DRIVER DQ C, DQPC WRITE DRIVER
SENSE AMPS
BW G
BW F
BW E
MEMORY ARRAY
BW D
BW C
DQ C, DQPC WRITE DRIVER
OUTPUT REGISTERS
BW B
DQ B , DQPB WRITE DRIVER
DQ B , DQPB WRITE DRIVER DQ A , DQPA WRITE DRIVER
OUTPUT BUFFERS E
BW A BWE GW CE1 CE2 CE3 OE
DQ A , DQPA WRITE DRIVER
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H
ZZ
SLEEP CONTROL
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Pin Configurations 100-Pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1481V33 (2Mx 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1483V33 (4M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 A A VSS VDD A A A A A A A A A
MODE A A A A A1 A0 A A VSS VDD
Document #: 38-05284 Rev. *H
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1481V33 (2M x 36)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A1 A0
A
A
A
CY7C1483V33 (4M x 18)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A1 A0
A
A
A
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Pin Configurations (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1487V33 (1M × 72)
1 A B C D E F G H J K L M N P R T U V W 2 3
A BWSC BWSH VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS
4
CE2
5
6
7
ADV A NC/576M GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSB BWSE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSF BWSA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK
10
11
DQG DQG DQG DQG DQPG DQC DQC DQC DQC
NC
DQG DQG DQG DQG DQPC DQC DQC DQC DQC
NC
ADSP ADSC BW
DQB DQB DQB DQB DQPF DQF DQF DQF DQF
NC
DQB DQB DQB DQB DQPB DQF DQF DQF DQF
NC
BWSG NC/288M
BWSD NC/144M CE1 NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0
DQH DQH DQH DQH DQPD DQD DQD DQD DQD
DQH DQH DQH DQH
DQA DQA DQA DQA DQPA DQE DQE DQE DQE
DQA DQA DQA DQA DQPE DQE DQE DQE DQE
DQPH VDDQ DQD DQD DQD DQD
VSS A A TMS
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Pin Definitions
Pin Name A0, A1, A IO InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPx is controlled by BWX correspondingly. Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating, selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. Page 7 of 30
BWA,BWB,BWC,BWD, BWE,BWF,BWG,BWH GW
CLK CE1
CE2
CE3
OE
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
BWE ZZ
InputSynchronous InputAsynchronous IOSynchronous
DQs
DQPX MODE
IOSynchronous Input-Static
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Pin Definitions (continued)
Pin Name VDD VDDQ VSS VSSQ TDO
[2}
IO Power Supply Ground I/O Ground JTAG Serial Output Synchronous
Description Power supply inputs to the core of the device. Ground for the core of the device. Ground for the IO circuitry. Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin should be left unconnected. This pin is not available on TQFP packages.
IO Power Supply Power supply for the IO circuitry.
TDI
JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG Clock Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see “Truth Table for Read/Write” on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are supported. All IOs are tri-stated during a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated before the presentation of data to DQs. As a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQs will be written into the specified address location. Byte writes are supported.
TMS
TCK NC
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1481V33/CY7C1483V33/CY7C1487V33 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be
Note 2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
All IOs are tri-stated when a write is detected, even a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated before the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 150 2tCYC Unit mA ns ns ns ns
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Truth Table
The truth table for CY7C1481V33, CY7C1483V33, and CY7C1487V33 follows.[3, 4, 5, 6, 7] Cycle Description Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Sleep Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS CE CE CE ZZ 1 2 3 Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L X X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D
Notes 3. X = Do Not Care, H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Truth Table for Read/Write
The read-write truth table for CY7C1481V33 follows.[3, 8] Function Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Truth Table for Read/Write
The read-write truth table for CY7C1483V33 follows.[3, 8] Function Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
Truth Table for Read/Write
The read-write truth table for CY7C1487V33 follows.[3, 8] Function Read Read Write Byte x – (DQx and DQPx) Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWx[9] X All BW = H L All BW = L X
Notes 8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active. 9. BWx represents any byte write signal BWX.To enable any byte write BWx , a Logic LOW signal must be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1481V33/CY7C1483V33/CY7C1487V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V IO logic levels. The CY7C1481V33/CY7C1483V33/CY7C1487V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0 Bypass Register
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
210
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TM S
TAP CONTROLLER
Performing a TAP Reset To perform a RESET, force TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in the “TAP Controller Block Diagram” on page 12. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the Page 12 of 30
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this Document #: 38-05284 Rev. *H
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IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register, and the x18 configuration has a 54-bit-long register. The boundary scan register is loaded with the contents of the RAM I/ ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page 15. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state, when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction, which is to be executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.
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After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK )
t TM SS
2
3
4
5
6
t TH t TM SH
t
TL
t CY C
Test M ode Select (TM S)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON’T CA RE UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[10,11] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 5 5 5 ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 20 20 50 20 ns MHz ns ns Description Min Max Unit
Notes 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 n.s.
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3.3V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 Ω TDO Z O= 50 Ω 20pF
2.5V TAP AC Output Load Equivalent
1.25V 50 Ω TDO Z O= 50 Ω 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ IOH = –4.0 mA IOH = –1.0 mA IOH = –100 µA IOL = 8.0 mA IOL = 1.0 mA IOL = 100 µA Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 –0.3 –0.3 –5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Max Unit V V V V V V V V V V V V µA
Identification Register Definitions
Bit# 24 is “1” in the ID Register definitions for both 2.5V and 3.3V versions of the device. Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0)
Note 12. All voltages refer to VSS (GND).
CY7C1481V33 (2M x 36) 000 01011 000001 100100 00000110100 1
CY7C1483V33 (4M x18) 000 01011 000001 010100 00000110100 1
CY7C1487V33 (1M x72) 000 01011 000001 110100 00000110100 1
Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Enables unique identification of SRAM vendor Indicates the presence of an ID register
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Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order -165FBGA Boundary Scan Order -209 BGA Bit Size (X36) 3 1 32 73 Bit Size (X18) 3 1 32 54 Bit Size (X72) 3 1 32 112
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures IO ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Description
Boundary Scan Exit Order (2M x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 165-Ball ID R3 P2 R4 P6 R6 N6 P11 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 165-Ball ID L10 K11 J11 K10 J10 H11 G11 F11 E11 D10 D11 C11 G10 F10 E10 A10 B10 A9 B9 A8 Page 16 of 30 Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 165-Ball ID B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2
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Boundary Scan Exit Order (4M x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 R4 P6 R6 N6 P11 Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 165-Ball ID R8 P3 P4 P8 P9 P10 R9 R10 R11 M10 L10 K10 J10 H11 G11 F11 E11 D11 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 165-Ball ID C11 A11 A10 B10 A9 B9 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2
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Boundary Scan Exit Order (1M x 72)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 209-Ball ID A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 L1 L2 M1 M2 N1 N2 P1 P2 R2 R1 Bit # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 209-Ball ID T1 T2 U1 U2 V1 V2 W1 W2 T6 V3 V4 U4 W5 V6 W6 U3 U9 V5 U5 U6 W7 V7 U7 V8 V9 W11 W10 V11 Bit # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 209-Ball ID V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 P6 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 Bit # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 209-Ball ID C11 C10 B11 B10 A11 A10 A9 U8 A7 A5 A6 D6 B6 D7 K3 A8 B4 B3 C3 C4 C8 C9 B9 B8 A4 C6 B7 A3
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA
Operating Range
Ambient VDD VDDQ Temperature Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Range
Electrical Characteristics
Over the Operating Range[13, 14] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[13] Input LOW Voltage[13] Input Leakage Current Except ZZ and MODE For 3.3V I/O For 2.5V I/O For 3.3V I/O, IOH = –4.0 mA For 2.5V I/O, IOH = –1.0 mA For 3.3V I/O, IOL = 8.0 mA For 2.5V I/O, IOL = 1.0 mA For 3.3V I/O For 2.5V I/O For 3.3V I/O For 2.5V I/O GND ≤ VI ≤ VDDQ 2.0 1.7 –0.3 –0.3 –5 –30 5 –5 30 –5 5 335 305 200 200 150 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz Test Conditions Min 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max 3.6 VDD 2.625 Unit V V V V V V V V V V V µA µA µA µA µA µA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD ISB1 ISB2 ISB3 ISB4 Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled VDD Operating Supply Current Automatic CE Power Down Current—TTL Inputs VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC Max VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching
Automatic CE Max VDD, Device Deselected, All speeds Power Down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—CMOS Inputs f = 0, inputs static Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz Automatic CE Power Down VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 10-ns cycle, 100 MHz Current—CMOS Inputs f = fMAX, inputs switching Automatic CE Power Down Current—TTL Inputs Max VDD, Device Deselected, All Speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static
200 200 165
mA mA mA
Notes 13. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2). 14. TPower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CADDRESS CDATA CCTRL CCLK CI/O Description Address Input Capacitance Data Input Capacitance Control Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max 6 5 8 6 5 165 FBGA Max 6 5 8 6 5 209 FBGA Max 6 5 8 6 5 Unit pF pF pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 24.63 2.28 165 FBGA Package 16.3 2.1 209 FBGA Package 15.2 1.7 Unit °C/W °C/W
AC Test Loads and Waveforms
3.3V IO Test Load
OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω R = 317Ω VDDQ 5 pF GND R = 351Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1 ns
VL = 1.5V
≤ 1 ns
(a) 2.5V IO Test Load
OUTPUT Z0 = 50Ω 2.5V
INCLUDING JIG AND SCOPE
(b)
(c)
R = 1667Ω VDDQ 5 pF GND R = 1538Ω 10%
ALL INPUT PULSES 90% 90% 10% ≤ 1 ns
OUTPUT RL = 50Ω VL = 1.25V
≤ 1 ns
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
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Switching Characteristics
Over the Operating Range.[15, 16] Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSP, ADSC Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWX Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[18, 19, 20] Clock to High-Z[18, 19, 20] OE LOW to Output Valid OE LOW to Output OE HIGH to Output Low-Z[18, 19, 20] High-Z[18, 19, 20] 0 3.0 2.5 3.0 3.8 3.0 0 4.0 6.5 2.5 3.0 4.5 3.8 8.5 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 10 3.0 3.0 ns ns ns Description VDD(Typical) to the First Access[17] 133 MHz Min 1 Max 100 MHz Min 1 Max Unit ms
Notes 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted. 17. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 18. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV from steady-state voltage. 19. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested.
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Timing Diagrams
Figure 1. Read Cycle Timing[21]
tCYC
CLK
t
CH
t CL
t ADS
tADH
ADSP
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
t WES t WEH
A2
GW, BWE, BWX
t CES t CEH
Deselect Cycle
CE
t ADVS t ADVH
ADV ADV suspends burst OE
t OEV t CLZ t OEHZ t OELZ
t CDV t DOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CDV
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around to its initial state
Single READ DON’T CARE
BURST READ UNDEFINED
Note 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Timing Diagrams (continued)
Figure 2. Write Cycle Timing[21, 22]
t CYC
CLK
t
CH
t
CL
t ADS
tADH
ADSP
t ADS tADH
ADSC extends burst
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
t WES tWEH
BWE, BW X
t t WEH
WES
GW
t CES tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
Data in (D)
High-Z
t
D(A1) OEHZ
D ata Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON’T CARE
UNDEFINED
Note 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
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Timing Diagrams (continued)
Figure 3. Read/Write Cycle Timing[21, 23, 24]
tCYC
CLK
t
CH
t
CL
t ADS
tADH
ADSP
ADSC
t AS tAH
ADDRESS
A1
A2
A3
t WES t WEH
A4
A5
A6
BWE, BW X
t CES tCEH
CE
ADV
OE
t DS tDH t OELZ
Data In (D) Data Out (Q)
High-Z
t OEHZ
D(A3)
t CDV
D(A5)
D(A6)
Q(A1)
Q(A2) Single WRITE DON’T CARE
Q(A4)
Q(A4+1) BURST READ UNDEFINED
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
Back-to-Back READs
Notes 23. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH.
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Timing Diagrams (continued)
Figure 4. ZZ Mode Timing[25, 26]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes 25. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device. 26. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1481V33-133AXC CY7C1483V33-133AXC CY7C1481V33-133BZC CY7C1483V33-133BZC CY7C1481V33-133BZXC CY7C1483V33-133BZXC CY7C1487V33-133BGC CY7C1487V33-133BGXC CY7C1481V33-133AXI CY7C1483V33-133AXI CY7C1481V33-133BZI CY7C1483V33-133BZI CY7C1481V33-133BZXI CY7C1483V33-133BZXI CY7C1487V33-133BGI CY7C1487V33-133BGXI 100 CY7C1481V33-100AXC CY7C1483V33-100AXC CY7C1481V33-100BZC CY7C1483V33-100BZC CY7C1481V33-100BZXC CY7C1483V33-100BZXC CY7C1487V33-100BGC CY7C1487V33-100BGXC CY7C1481V33-100AXI CY7C1483V33-100AXI CY7C1481V33-100BZI CY7C1483V33-100BZI CY7C1481V33-100BZXI CY7C1483V33-100BZXI CY7C1487V33-100BGI CY7C1487V33-100BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Package Diagrams
Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00±0.20 14.00±0.10
100 1 81 80
1.40±0.05
0.30±0.08
22.00±0.20
20.00±0.10
0.65 TYP.
30 31 50 51
12°±1° (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0° MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0°-7°
R 0.08 MIN. 0.20 MAX.
0.60±0.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05284 Rev. *H
0.10
R 0.08 MIN. 0.20 MAX.
Page 27 of 30
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Package Diagrams (continued)
Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B
PIN 1 CORNER
Ø0.45±0.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A B
A B
D E F G
1.00
C
C D E F G
17.00±0.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.53±0.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.00±0.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
Document #: 38-05284 Rev. *H
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Package Diagrams (continued)
Figure 7. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05284 Rev. *H
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© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1481V33 CY7C1483V33 CY7C1487V33
Document History Page
Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Document Number: 38-05284 REV. ** *A ECN NO. 114671 118283 Issue Date 08/12/02 01/27/03 Orig. of Change PKS HGK New Data Sheet Updated Ordering Information Updated the features for package offering Changed from Advance Information to Preliminary Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 150-MHz speed grade offering Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering Removed 117-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 21 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Changed the IX current values of MODE on page # 19 from -5 µA and 30 µA to -30 µA and 5 µA Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA to -5 µA and 30 µA Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering Information table Converted from Preliminary to Final Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table Corrected the typo in the 209-Ball FBGA pinout. (Corrected the ball name H9 to VSS from VSSQ). Description of Change
*B
233368
See ECN
NJY
*C
299452
See ECN
SYT
*D
323080
See ECN
PCI
*E
416193
See ECN
NXR
*F
470723
See ECN
VKN
*G *H
486690 1062041
See ECN See ECN
VKN
VKN/KKVTMP Added footnote #2 related to VSSQ
Document #: 38-05284 Rev. *H
Page 30 of 30
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