CY7C149-35DMB

49 CY7C148 CY7C149 1Kx4 Static RAM Features • • • • Automatic power-down when deselected (7C148) CMOS for optimum speed/power 25-ns access time Low active power — 440 mW (commercial) sion is provided by an active LOW chip select (CS) input and three-state outputs. The CY7C148 remains in a low-power mode as long as the device remains unselected; i.e., (CS) is HIGH, thus reducing the average power requirements of the device. The chip select (CS) of the CY7C149 does not affect the power dissipation of the device. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the I/O pins (I/O0 through I/O3) is written into the memory locations specified on the address pins (A0 through A9). Reading the device is accomplished by taking chip select (CS) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data I/O pins. The I/O pins remain in a high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW. — 605 mW (military) • Low standby power (7C148) — 82.5 mW (25-ns version) — 55 mW (all others) • 5-volt power supply ± 10% tolerance, both commercial and military • TTL-compatible inputs and outputs Functional Description The CY7C148 and CY7C149 are high-performance CMOS static RAMs organized as 1024 by 4 bits. Easy memory expan- Logic Block Diagram Pin Configurations DIP Top View A6 A5 A4 A3 A0 A1 A2 SENSE AMP INPUTBUFFER 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 CS COLUMN DECODER POWER DOWN (7C148) WE C148–1 A3 A2 A1 A0 A4 A13 A10 A11 A12 2 1 1817 3 16 4 15 5 14 6 13 7 12 8 9 1011 CS GND WE I/0 3 A5 A6 V CC A7 A9 A8 A7 A6 A5 A4 ROW DECODER I/O0 I/O1 I/O2 I/O3 V CC A7 A8 A9 I/O 0 I/O 1 I/O 2 I/O 3 WE C148–2 CS GND 64 x 64 ARRAY LCC Top View A8 A9 I/O 0 I/O 1 I/O2 C148–3 Selection Guide 7C148−25 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Commercial Military Commercial Military 15 25 90 7C148−35 35 80 110 10 10 7C148−45 45 80 110 10 10 7C149−25 25 90 7C149−35 35 80 110 7C149−45 45 80 110 Cypress Semiconductor Corporation Document #: 38-05059 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 18, 2001 [+] Feedback CY7C148 CY7C149 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................−65°C to+150°C Ambient Temperature with Power Applied ................................................... −55°C to+125°C Supply Voltage to Ground Potential (Pin 18 to Pin 9) ....................................................−0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ......................................................−0.5V to+7.0V DC Input Voltage .................................................−3.0V to +7.0V Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Military[1] Ambient Temperature 0°C to +70°C −55°C to +125°C VCC 5V ± 10% 5V ± 10% Note: 1. TA is the “instant on” case temperature. Electrical Characteristics Over the Operating Range[2] 7C148−25 7C149−25 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB IPO IOS Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current Peak Power-On Current[3] Output Short Circuit Current[4] GND < VI < VCC GND < VO < VCC Output Disabled Max. VCC, CS < VIL, Output Open Max. VCC, CS > VIH Max. VCC, CS > VIH GND < VO < VCC 7C148 Only 7C148 Only Com’l Mil Com’l Mil Com’l Mil Com’l Mil ±275 15 15 Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.0 −3.0 −10 −50 Min. 2.4 0.4 6.0 0.8 10 50 90 2.0 −3.0 −10 −50 Max. 7C148−35, 45 7C149−35, 45 Min. 2.4 0.4 6.0 0.8 10 50 80 110 10 10 10 10 ±275 ±350 mA mA mA Max. Unit V V V V µA µA mA Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up. Otherwise current will exceed values given (CY7C148 only). 4. For test purposes, not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05059 Rev. ** Page 2 of 9 [+] Feedback CY7C148 CY7C149 AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255Ω R1481 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω C148–4 R1481 Ω ALL INPUT PULSES 3.0V GND < 10 ns 90% 10% 90% 10% < 10 ns C148–5 (a) (b) THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Switching Characteristics Over the Operating Range[2] 7C148−25 7C149−25 Parameter READ CYCLE tRC tAA tACS1 tACS2 tACS tLZ[8] tHZ[8] tOH tPD tPU tWC tWP[9] tWR tWZ tDH tAS tCW tAW [9] [8] 7C148−35 7C149−35 Min. 35 Max. 7C148−45 7C149−45 Min. 45 Max. Unit ns 45 45 45 20 10 5 ns ns ns ns ns 20 30 0 45 35 5 ns ns ns ns ns ns ns 8 ns ns ns ns ns ns ns Description Address Valid to Address Do Not Care Time (Read Cycle Time) Address Valid to Data Out Valid Delay (Address Access Time) Chip Select LOW to Data Out Valid (7C148 only) Chip Select LOW to Data Out Valid (7C149 only) Chip Select LOW to Data Out On Chip Select HIGH to Data Out Off Address Unknown to Data Out Unknown Time Chip Select HIGH to Power-Down Delay Chip Select LOW to Power-Up Delay Address Valid to Address Do Not Care (Write Cycle Time) Write Enable LOW to Write Enable HIGH Address Hold from Write End Write Enable to Output in High Z Data in Valid to Write Enable HIGH Data Hold Time Address Valid to Write Enable LOW Chip Select LOW to Write Enable HIGH Write Enable HIGH to Output in Low Z Address Valid to End of Write 7C148 7C148 7C148 7C149 Min. 25 Max. 25 25[6] 30[7] 15 8 5 0 0 20 0 25 20 5 0 12 0 0 20 0 20 8 0 35 30 5 0 20 0 0 30 0 30 15 10 5 0 0 35 35 35 15 20 30 0 5 WRITE CYCLE 8 0 20 0 0 40 0 35 tDW tOW[8] Notes: 6. Chip deselected greater than 25 ns prior to selection. 7. Chip deselected less than 25 ns prior to selection. 8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady-state voltage with specified loading in part (b) of AC Test Loads. 9. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05059 Rev. ** Page 3 of 9 [+] Feedback CY7C148 CY7C149 Switching Waveforms Read Cycle No. 1 [10,11] tRC ADDRESS tOH DATA OUT PREVIOUS DATA VALID tAA DATA VALID C148–6 Read Cycle No. 2 [10,12] tRC CS tACS tLZ DATA OUT HIGH IMPEDANCE DATA VALID tHZ HIGH IMPEDANCE tPU VCC SUPPLY CURRENT 50% tPD ICC 50% ISB C148–7 Write Cycle No.1 (WE Controlled) tWC ADDRESS tCW CS tAS WE tDW DATA IN DATA–IN VALID tWZ DATA OUT DATA UNDEFINED C148–8 tAW tWP tWA tDH tOW HIGH IMPEDANCE Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CS = VIL. 12. Address valid prior to or coincident with CS transition LOW. Document #: 38-05059 Rev. ** Page 4 of 9 [+] Feedback CY7C148 CY7C149 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [13] tWC ADDRESS tCW CS tAW tWP WE tDW DATA IN tWZ DATA OUT DATA UNDEFINED HIGH IMPEDANCE C148–9 tWR tDH DATAIN VALID Notes: 13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE 1.2 ICC OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C NORMALIZED CCI I, 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 ICC VIN =5.0V TA =25°C NORMALIZED CC SB I, I 1.2 1.0 0.8 0.6 0.4 0.2 ISB VCC =5.0V VIN =5.0V ISB 5.0 5.5 6.0 0.0 −55 25 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 TA =25°C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C VCC =5.0V 0.8 0.6 −55 25 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) Document #: 38-05059 Rev. ** Page 5 of 9 [+] Feedback CY7C148 CY7C149 Typical DC and AC Characteristics TYPICAL POWER–ON CURRENT vs.SUPPLY VOLTAGE (7C148) 3.0 PO TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING 30.0 1.4 NORMALIZED I CC 1.3 1.2 1.1 1.0 0.9 NORMALIZED I CC vs.ACCESS TIME NORMALIZED I 2.0 1.5 1.0 0.5 0.0 0.0 1.0 TA =25°C 1K Ω CSPULL–UP RESISTORTOV CC ISB DELTA tAA (ns) 2.5 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25°C 2.0 3.0 4.0 5.0 0.0 0 200 400 600 800 1000 0.8 10 20 30 40 50 60 SUPPLY VOLTAGE(V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Ordering Information Speed (ns) 25 35 45 Ordering Code CY7C148−25PC CY7C148−35PC CY7C148−35DMB CY7C148−45PC CY7C148−45DMB Package Name P3 P3 D4 P3 D4 Package Type 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) CerDIP 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) CerDIP Operating Range Commercial Commercial Military Commercial Military Speed (ns) 25 35 Ordering Code CY7C149−25PC CY7C149−35PC CY7C149−35DMB CY7C149−35LMB Package Name P3 P3 D4 L50 P3 D4 L50 Package Type 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) CerDIP 18-Pin Rectangular Leadless Chip Carrier 18-Lead (300-Mil) Molded DIP 18-Lead (300-Mil) CerDIP 18-Pin Rectangular Leadless Chip Carrier Operating Range Commercial Commercial Military Commercial Military 45 CY7C149−45PC CY7C149−45DMB CY7C149−45LMB Document #: 38-05059 Rev. ** Page 6 of 9 [+] Feedback CY7C148 CY7C149 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters IOH IOL VIH VIL Max. IIX IOZ ICC ISB[14] Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameters READ CYCLE tRC tAA tACS1 [14] Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 tACS2[14] tACS[15] tOH WRITE CYCLE tWC tWP tWR tDW tDH tAS tAW Notes: 14. 7C148 only. 15. 7C149 only. Document #: 38-05059 Rev. ** Page 7 of 9 [+] Feedback CY7C148 CY7C149 18–Lead(300–Mil) CerDIP D4 MIL−STD−1835 D− 8Config.A 18–Pin Rectangular Leadless ChipCarrier L50 MIL−STD−1835 C−10A 18–Lead(300–Mil) Molded DIP P3 Document #: 38-05059 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback CY7C148 CY7C149 Document Title: CY7C148 / CY7C149 1K x 4 Static RAM Document Number: 38-05059 REV. ** ECN NO. 110170 Issue Date 09/29/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00031 to 38-05059 Document #: 38-05059 Rev. ** Page 9 of 9 [+] Feedback