CY7C150-15PC

50 CY7C150 1Kx4 Static RAM Features • Memory reset function • 1024 x 4 static RAM for control store in high-speed computers • CMOS for optimum speed/power • High speed — 10 ns (commercial) — 12 ns (military) • Low power — 495 mW (commercial) • • • • — 550 mW (military) Separate inputs and outputs 5-volt power supply ±10% tolerance in both commercial and military Capable of withstanding greater than 2001V static discharge TTL-compatible inputs and outputs Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion. Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D0−D3) is written into the memory location specified on the address pins (A0 through A9). Reading the device is accomplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O3). The output pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW. A die coat is used to insure alpha immunity. Functional Description The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles. Logic Block Diagram D0 D1 D2 D3 DATAINPUT CONTROL ROW DECODER A0 A1 A2 A3 A4 A5 SENSE AMPS RS CS OE WE Pin Configuration DIP/SOIC Top View A3 A4 A5 A6 A7 A8 A9 D0 D1 O0 O1 GND 1 2 3 4 5 24 23 22 21 20 6 7C150 19 18 7 8 17 9 16 10 15 14 11 13 12 VCC A2 A1 A0 RS CS WE OE D3 D2 O3 O2 C150-2 O0 O1 O2 O3 64 x 64 ARRA Y COLUMN COLUMN DECODER DECODER C150–1 A6 A7 A8 A9 Selection Guide 7C150−10 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Commercial Military 90 10 7C150−12 12 12 90 100 7C150−15 15 15 90 100 7C150−25 25 25 90 100 35 90 100 7C150−35 Cypress Semiconductor Corporation Document #: 38-05024 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 18, 2003 CY7C150 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................−65°C to+150°C Ambient Temperature with Power Applied ................................................... −55°C to+125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12)..................................................−0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ......................................................−0.5V to+7.0V DC Input Voltage .................................................−3.0V to +7.0V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Military [1] Ambient Temperature 0°C to +70°C −55°C to +125°C VCC 5V ± 10% 5V ± 10% Note: 1. TA is the “instant on” case temperature. Electrical Characteristics Over the Operating Range[2] 7C150 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Current Input HIGH Level Input LOW Level Input Load Current Output Current (High Z) Output Short Circuit Current[3] VCC Operating Supply Current GND < VI < VCC VOL < VOUT < VOH, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Commercial Military Test Conditions VCC = Min., IOH = − 0.4 mA VCC = Min., IOL = 12 mA 2.0 −3.0 −10 −50 Min. 2.4 0.4 VCC 0.8 +10 +50 −300 90 100 Max. Unit V V V V µA µA mA mA mA Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. Not more than 1 output should be shorted at a time. Duration of the short circuit should not exceed 30 seconds. Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Note: 4. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1329 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 202Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R1329 Ω ALL INPUT PULSES R2 202Ω 3.0V 10% GND < 3 ns (b) C150–3 90% 90% 10% < 3 ns C150–4 (a) Equivalent to: THÉVENIN EQUIVALENT OUTPUT 125Ω 1.9V Document #: 38-05024 Rev. *A Page 2 of 11 CY7C150 Switching Characteristics Over the Operating Range[2,5] 7C150−10 Parameter READ CYCLE tRC tAA tOHA tACS tLZCS tHZCS tDOE tLZOE tHZOE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tRRC tSAR tSWER tSCSR tPRS tHCSR tHWER tHAR tLZRS tHZRS Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid CS LOW to Low Z[6] CS HIGH to High Z OE LOW to Low Z [8] [6,7] 7C150−12 Min. 12 Max. 7C150−15 Min. 15 Max. 7C150−25 Min. 25 Max. 7C150−35 Min. 35 Max. Unit ns 35 2 ns ns 20 0 25 20 0 25 35 20 30 5 5 20 20 5 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 70 0 0 0 30 0 40 40 0 ns ns ns ns ns ns ns ns ns ns 25 ns Description Min. 10 Max. 10 2 8 0 6 6 0 6 10 6 8 2 2 6 6 2 0 6 20 0 0 0 10 0 8 10 0 6 24 0 0 0 12 0 12 12 0 12 8 10 2 2 8 8 2 0 0 0 2 12 2 10 0 8 8 0 8 15 11 13 2 2 11 11 2 0 8 30 0 0 0 15 0 15 15 0 8 15 2 12 0 11 10 0 9 25 15 20 5 5 15 15 5 0 12 50 0 0 0 20 0 30 30 0 12 25 15 20 15 20 OE LOW to Data Valid [6] OE HIGH to High Z[6,7] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z Reset Cycle Time Address Valid to Beginning of Reset Write Enable HIGH to Beginning of Reset Chip Select LOW to Beginning of Reset Reset Pulse Width Chip Select Hold After End of Reset Write Enable Hold After End of Reset Address Hold After End of Reset Reset HIGH to Output in Low Z Reset LOW to Output in High Z[6,7] [6] [6] [6,7] WRITE CYCLE 20 RESET CYCLE 20 Notes: 5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device. 7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write. Document #: 38-05024 Rev. *A Page 3 of 11 CY7C150 Switching Waveforms Read Cycle No.1 [9,10] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C150-5 Read Cycle No. 2 CE [9,11] tRC tACS OE tDOE tLZOE HIGH IMPEDANCE tLZCS C150-6 tHZOE tHZCS DATA VALID DATA OUT HIGH IMPEDANCE Write CycleNo.1 (WE Controlled) [8] tWC ADDRESS tSCS CE tSA WE tSD DATA IN DATA IN VALID tHZWE DATA I/O DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA C150-7 Notes: 9. WE is HIGH for read cycle. 10. Device is continuously selected, CS and OE = VIL. 11. Address prior to or coincident with CS transition LOW. Document #: 38-05024 Rev. *A Page 4 of 11 CY7C150 Switching Waveforms (continued) Write Cycle No. (CS Controlled) 2 ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA IN VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED C150-8 [8,12] tWC tSCS tHA tHD Reset Cycle [13] tRRC ADDRESS tSAR WE tSWER tHAR tHWER CS tSCSR tPRS tHCSR RESET tHZRS DATA I/O HIGH IMPEDANCE tLZRS OUTPUT VALID ZERO C150-9 Notes: 12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state. 13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width. Document #: 38-05024 Rev. *A Page 5 of 11 CY7C150 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE 1.2 SB OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE 60 50 40 30 20 10 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 ICC 1.0 0.8 0.6 0.4 0.2 0.0 −55 ISB 25 VCC =5.0V VIN =5.0V NORMALIZED I,CC I NORMALIZED I,CC I ICC 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 TA =25°C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 150 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 5.0 VCC =5.0V TA =25°C VCC =5.0V 0.8 0.6 −55 25 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) TYPICAL POWER–ONCURRENT vs.SUPPLYVOLTAGE 3.0 NORMALIZED I PO 2.5 DELTA tAA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING 30 NORMALIZED I CC NORMALIZED I CC vs.CYCLE TIME 1.1 VCC =5.0V TA =25°C VCC =0.5V 1.0 20 10 VCC =4.5V TA =25°C 0.9 0 0 200 400 600 800 1000 0.8 10 20 30 40 SUPPLY VOLTAGE(V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05024 Rev. *A Page 6 of 11 CY7C150 Truth Table Inputs CS H L L L L WE X H L H X OE X X X L H RS X L H H H Outputs High Z High Z High Z O0−O3 High Z Mode Not Selected Reset Write Read Output Disable Ordering Information Speed (ns) 10 12 Ordering Code CY7C150−10PC CY7C150−10SC CY7C150−12PC CY7C150−12SC CY7C150−12DMB 15 CY7C150−15PC CY7C150−15SC CY7C150−15DMB 25 CY7C150−25PC CY7C150−25SC CY7C150−25DMB 35 CY7C150−35DMB Package Name P13A S13 P13A S13 D14 P13A S13 D14 P13A S13 D14 D14 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) CerDIP Military Military Military Commercial Military Commercial Commercial Operating Range Commercial Document #: 38-05024 Rev. *A Page 7 of 11 CY7C150 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter READ CYCLE tRC tAA tOHA tACS WRITE CYCLE tWC tSCS tAW tHA tSA tPWE tSD tHD RESET CYCLE tRRC tSAR tSWER tSCSR tPRS tHCSR tHWER tHAR 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups Document #: 38-05024 Rev. *A Page 8 of 11 CY7C150 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 24-Lead (300-Mil) Molded DIP P13/P13A Document #: 38-05024 Rev. *A Page 9 of 11 CY7C150 Package Diagrams (continued) 24-Lead Molded SOIC S13 Document #: 38-05024 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C150 Document Title: Cy7C150 1K x4 Static RAM Document Number: 38-05024 REV. ** *A ECN NO. 106810 122462 Issue Date 09/10/01 01/18/03 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00028 to 38-05024 This ECN/Spec will serve as the master signature approval document for all ECN’s referenced to it. ECN’s to datasheets adding power up requirements are covered for signatures when referenced to 122462. Document #: 38-05024 Rev. *A Page 11 of 11