CY7C1512-70ZI

1CY 7C15 12 PRELIMINARY CY7C1512 64K x 8 Static RAM Features • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power — 770 mW • Low standby power — 28 mW • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 H IGH, and WE LOW). The CY7C1512 is available in standard TSOP type I and 450-mil-wide plastic SOIC packages. Functional Description The CY7C1512 is a high-performance CMOS static RAM organized as 65,536 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output enable (OE), Logic Block Diagram Pin Configurations SOIC Top View NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A11 A9 A8 A13 WE CE2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 I/O1 I/O2 64K x 8 ARRAY 1512-2 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O3 I/O4 I/O5 POWER DOWN CE 1 CE2 WE COLUMN DECODER I/O6 I/O7 1512-1 TSOP I Top View (not to scale) OE Selection Guide Maximum Access Time (ns) Maximum Operating Commercial Current (mA) Maximum CMOS Commercial Standby Current (mA) 7C1512-15 15 140 5 7C1512-20 20 130 5 7C1512-25 25 120 5 7C1512-35 35 110 5 7C1512-70 70 110 5 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1996 – Revised October 1996 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................–0.5V to VCC +0.5V DC Input Voltage[1]..................................–0.5V to VCC +0.5V Electrical Characteristics Over the Operating Range[3] 7C1512-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit VCC Operating Supply Current Automatic CE Power–Down Current — TTL Inputs Automatic CE Power–Down Current — CMOS Inputs Current[4] GND < VI < VCC GND < VI < VCC,Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC – 0.3V, or CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC – 0.3V, or CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 –1 –5 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 –300 110 25 2.2 –0.3 –1 –5 Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.3 –1 –5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 –300 140 40 2.2 –0.3 –1 –5 Max. 7C1512-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 –300 130 30 Max. CY7C1512 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL–STD–883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature[2] 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% 7C1512-25 Min. 2.4 0.4 2.2 –0.3 –1 –5 VCC + 0.3 0.8 +1 +5 –300 120 30 Max. Unit V V V V µA µA mA mA mA ISB2 5 5 5 mA 7C1512-35 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs Max. 7C1512-70 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 –300 110 25 Max. Unit V V V V µA µA mA mA mA ISB2 5 5 mA Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 2 PRELIMINARY Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 9 9 CY7C1512 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT R2 255Ω R1 480Ω R1 480Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω GND