CY7C1526JV18-167BZI

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1511JV18 – 8M x 8 CY7C1526JV18 – 8M x 9 CY7C1513JV18 – 4M x 18 CY7C1515JV18 – 2M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high speed systems Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates similar to a QDR-I device with 1 cycle read latency in DLL off mode Available in x8, x9, x18, and x36 configurations Full data coherency, providing most current data Core VDD = 1.8 (± 0.1V); IO VDDQ = 1.4V to VDD Available in 165-ball FBGA package (15 x 17 x 1.4 mm) Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement ■ ■ ■ ■ Functional Description The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1511JV18), 9-bit words (CY7C1526JV18), 18-bit words (CY7C1513JV18), or 36-bit words (CY7C1515JV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Selection Guide Description Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 300 MHz 300 1090 1090 1115 1140 250 MHz 250 790 795 865 1040 167 MHz 167 570 575 615 725 Unit MHz mA Cypress Semiconductor Corporation Document Number: 001-12560 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 31, 2009 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram (CY7C1511JV18) D[7:0] 8 Write Reg Write Reg Write Reg Write Reg Read Add. Decode Write Add. Decode A(20:0) 21 Address Register Address Register 21 A(20:0) 2M x 8 Array 2M x 8 Array 2M x 8 Array 2M x 8 Array K K CLK Gen. RPS Control Logic C C CQ DOFF Read Data Reg. 32 VREF WPS NWS[1:0] Control Logic 16 16 Reg. Reg. Reg. 8 8 8 8 CQ 8 Q[7:0] Logic Block Diagram (CY7C1526JV18) D[8:0] 9 Write Reg Write Reg Write Reg Write Reg Read Add. Decode Write Add. Decode A(20:0) 21 Address Register Address Register 21 A(20:0) 2M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array K K CLK Gen. RPS Control Logic C C CQ DOFF Read Data Reg. 36 VREF WPS BWS[0] Control Logic 18 18 Reg. Reg. Reg. 9 9 9 9 CQ 9 Q[8:0] Document Number: 001-12560 Rev. *E Page 2 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram (CY7C1513JV18) D[17:0] 18 Write Reg Write Reg Write Reg Write Reg Read Add. Decode Write Add. Decode A(19:0) 20 Address Register Address Register 20 A(19:0) 1M x 18 Array 1M x 18 Array 1M x 18 Array 1M x 18 Array K K CLK Gen. RPS Control Logic C C CQ DOFF Read Data Reg. 72 VREF WPS BWS[1:0] Control Logic 36 36 Reg. Reg. Reg. 18 18 18 18 CQ 18 Q[17:0] Logic Block Diagram (CY7C1515JV18) D[35:0] 36 Write Reg Write Reg Write Reg Write Reg Read Add. Decode Write Add. Decode A(18:0) 19 Address Register Address Register 19 A(18:0) 512K x 36 Array 512K x 36 Array 512K x 36 Array 512K x 36 Array K K CLK Gen. RPS Control Logic C C CQ DOFF Read Data Reg. 144 VREF WPS BWS[3:0] Control Logic 72 72 Reg. Reg. Reg. 36 36 36 36 CQ 36 Q[35:0] Document Number: 001-12560 Rev. *E Page 3 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Configuration The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1511JV18 (8M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 A NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI CY7C1526JV18 (8M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 A NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-12560 Rev. *E Page 4 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Configuration The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. [1] (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1513JV18 (4M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 A D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI CY7C1515JV18 (2M x 36) 1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 NC/288M Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 A D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Document Number: 001-12560 Rev. *E Page 5 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Definitions Pin Name D[x:0] IO Pin Description InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1511JV18 − D[7:0] CY7C1526JV18 − D[8:0] CY7C1513JV18 − D[17:0] CY7C1515JV18 − D[35:0] InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. InputNibble Write Select 0, 1 − Active LOW (CY7C1511JV18 Only). Sampled on the rising edge of the K Synchronous and K clocks when write operations are active. Used to select which nibble is written into the device during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device. InputByte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when Synchronous write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1526JV18 − BWS0 controls D[8:0] CY7C1513JV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1515JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1511JV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1526JV18, 4M x 18 (4 arrays each of 1M x 18) for CY7C1513JV18 and 2M x 36 (4 arrays each of 512K x 36) for CY7C1515JV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1511JV18 and CY7C1526JV18, 20 address inputs for CY7C1513JV18 and 19 address inputs for CY7C1515JV18. These inputs are ignored when the appropriate port is deselected. OutputsData Output Signals. These pins drive out the requested data when the read operation is active. Valid Synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in single clock mode. On deselecting the read port, Q[x:0] are automatically tri-stated. CY7C1511JV18 − Q[7:0] CY7C1526JV18 − Q[8:0] CY7C1513JV18 − Q[17:0] CY7C1515JV18 − Q[35:0] InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfers. Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. WPS NWS0, NWS1, BWS0, BWS1, BWS2, BWS3 A Q[x:0] RPS C C Input Clock K Input Clock K Input Clock Document Number: 001-12560 Rev. *E Page 6 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Definitions Pin Name CQ IO Echo Clock (continued) Pin Description CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 24. CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 24. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing. TDO for JTAG. TCK Pin for JTAG. TDI Pin for JTAG. TMS Pin for JTAG. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. CQ Echo Clock ZQ Input DOFF Input TDO TCK TDI TMS NC Output Input Input Input N/A N/A N/A InputReference NC/144M NC/288M VREF VDD VSS VDDQ Power Supply Power Supply Inputs to the Core of the Device. Ground Ground for the Device. Power Supply Power Supply Inputs for the Outputs of the Device. Document Number: 001-12560 Rev. *E Page 7 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional Overview The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, CY7C1515JV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1511JV18, four 9-bit data transfers in the case of CY7C1526JV18, four 18-bit data transfers in the case of CY7C1513JV18, and four 36-bit data transfers in the case of CY7C1515JV18 in two clock cycles. This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then device behaves in QDR-I mode with a read latency of one clock cycle. Accesses for both ports are initiated on the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1513JV18 is described in the following sections. The same basic descriptions apply to CY7C1511JV18, CY7C1526JV18 and CY7C1515JV18. initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses are initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode). When the read port is deselected, the CY7C1513JV18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive output clock (C). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses are initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data is transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C1513JV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, or write operations to a byte write operation. Read Operations The CY7C1513JV18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C or C, or K or K when in single clock mode). To maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be Single Clock Mode The CY7C1511JV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Document Number: 001-12560 Rev. *E Page 8 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Concurrent Transactions The read and write ports on the CY7C1513JV18 operates completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 24. DLL These chips utilize a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL is also reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII/DDRII. Depth Expansion The CY7C1513JV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input deselects the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Document Number: 001-12560 Rev. *E Page 9 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example SRAM #1 Vt R D A R P S # W P S # B W S # ZQ CQ/CQ# Q C C# K K# R = 250ohms D A R P S # W P S # SRAM #4 B W S # ZQ R = 250ohms CQ/CQ# Q C C# K K# DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2 R Vt Vt Truth Table The truth table for CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 follows. [2, 3, 4, 5, 6, 7] Operation Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H RPS WPS H [8] DQ DQ DQ DQ L [9] D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑ L-H L [9] X Q(A) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑ L-H Stopped H X H X D=X Q = High-Z Previous State D=X Q = High-Z Previous State D=X Q = High-Z Previous State D=X Q = High-Z Previous State Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 3. Device powers up deselected with the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request. Document Number: 001-12560 Rev. *E Page 10 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Write Cycle Descriptions The write cycle description table for CY7C1511JV18 and CY7C1513JV18 follows. [2, 10] BWS0/ BWS1/ NWS0 L NWS1 L K L–H K – Comments During the data portion of a write sequence: CY7C1511JV18 − both nibbles (D[7:0]) are written into the device. CY7C1513JV18 − both bytes (D[17:0]) are written into the device. L L – L-H During the data portion of a write sequence: CY7C1511JV18 − both nibbles (D[7:0]) are written into the device. CY7C1513JV18 − both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence: CY7C1511JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1513JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L H L–H L H – L–H During the data portion of a write sequence: CY7C1511JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1513JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence: CY7C1511JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1513JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. H L L–H H L – L–H During the data portion of a write sequence: CY7C1511JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1513JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. H H H H L–H – Write Cycle Descriptions The write cycle description table for CY7C1526JV18 follows. [2, 10] BWS0 L L H H K L–H – L–H – K – L–H – L–H Comments During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Note 10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-12560 Rev. *E Page 11 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Write Cycle Descriptions The write cycle description table for CY7C1515JV18 follows. [2, 10] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L–H – L–H – L–H – L–H – L–H – L–H – K – Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Document Number: 001-12560 Rev. *E Page 12 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 16. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that is placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are used to capture the contents of the input and output ring. The Boundary Scan Order on page 19 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 18. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and is connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 18). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-12560 Rev. *E Page 13 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 IDCODE The IDCODE instruction loads a vendor specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is given a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit is set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-12560 Rev. *E Page 14 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12560 Rev. *E Page 15 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Controller Block Diagram 0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND ≤ VI ≤ VDD Test Conditions IOH = −2.0 mA IOH = −100 μA IOL = 2.0 mA IOL = 100 μA Min 1.4 1.6 0.4 0.2 0.65VDD VDD + 0.3 –0.3 –5 0.35VDD 5 Max Unit V V V V V V μA Notes 12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 13. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2). 14. All voltage referenced to ground. Document Number: 001-12560 Rev. *E Page 16 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions. [16] Figure 2. TAP Timing and Test Conditions 0.9V ALL INPUT PULSES 50Ω TDO Z0 = 50Ω CL = 20 pF 1.8V 0.9V 0V (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 001-12560 Rev. *E Page 17 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Identification Register Definitions Instruction Field Revision Number (31:29) Value CY7C1511JV18 000 CY7C1526JV18 000 CY7C1513JV18 000 CY7C1515JV18 000 Description Version number. Cypress Device ID 11010011011000100 11010011011001100 11010011011010100 11010011011100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID (11:1) ID Register Presence (0) 00000110100 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. 1 1 1 1 Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 109 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-12560 Rev. *E Page 18 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Document Number: 001-12560 Rev. *E Page 19 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. DLL Constraints ■ ■ ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The DLL functions at frequencies down to 120 MHz. If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL. ■ Figure 3. Power Up Waveforms ~ ~ K K ~ ~ Unstable Clock > 1024 Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tie to VDDQ) Document Number: 001-12560 Rev. *E Page 20 of 29 [+] Feedback CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V DC Input Voltage [13] Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch Up Current ................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature (TA) 0°C to +70°C –40°C to +85°C VDD [17] 1.8 ± 0.1V VDDQ [17] 1.4V to VDD .............................. –0.5V to VDD + 0.3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range [14] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD [21] Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Input Reference Voltage VDD Operating Supply [20] Test Conditions Min 1.7 1.4 Typ 1.8 1.5 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 5 5 Unit V V V V V V V V μA μA V mA Note 18 Note 19 IOH = −0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical Value = 0.75V VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 300 MHz (x8) (x9) (x18) (x36) 250 MHz (x8) (x9) (x18) (x36) 167 MHz (x8) (x9) (x18) (x36) −5 −5 0.68 0.75 0.95 1090 1090 1115 1140 790 795 865 1040 570 575 615 725 mA mA Notes 17. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 18. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms