CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
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Separate independent read and write data ports ❐ Supports concurrent transactions 375 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz Available in 2.0 clock cycle latency Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high-speed systems Data valid pin (QVLD) to indicate valid data on the output Single multiplexed address input bus latches address inputs for both read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes Available in x8, x9, x18, and x36 configurations
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■ ■ ■ ■ ■ ■ ■
Cypress Semiconductor Corporation Document Number: 001-05389 Rev. *F
•
198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised March 06, 2008
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Logic Block Diagram (CY7C1541V18)
D[7:0]
8
Write Reg
Read Add. Decode
Write Add. Decode
A(20:0)
21
Address Register
Address Register 2M x 8 Array 2M x 8 Array 2M x 8 Array
21
A(20:0)
2M x 8 Array
K K CLK Gen.
RPS Control Logic
Read Data Reg. CQ 32 VREF WPS NWS[1:0] Control Logic 16 16 Reg. Reg. Reg. CQ
8
Logic Block Diagram (CY7C1556V18)
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Logic Block Diagram (CY7C1543V18)
D[17:0]
18
Write Reg
Read Add. Decode
Write Add. Decode
A(19:0)
20
Address Register
Address Register 1M x 18 Array 1M x 18 Array 1M x 18 Array
20
A(19:0)
1M x 18 Array
K K CLK Gen.
RPS Control Logic
Read Data Reg. 72 VREF WPS BWS[1:0] Control Logic 36 36 Reg. Reg. Reg.
18
Logic Block Diagram (CY7C1545V18)
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Pin Configuration
The pin configuration for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follow.[2]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1541V18 (8M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 A NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1556V18 (8M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 A NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
Note 2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
CY7C1543V18 (4M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 A D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CY7C1545V18 (4M x 36) 1 A B C D E F CQ Q27 D27 D28 Q29 Q30 2 NC/288M Q18 Q28 D20 D29 Q21 3 A D18 D19 Q19 Q20 D21 4 WPS A VSS VSS VDDQ VDDQ 5 BWS2 BWS3 A VSS VSS 6 K K NC VSS VSS 7 BWS1 BWS0 A VSS VSS 8 RPS A VSS VSS VDDQ 9 A D17 D16 Q16 Q15 10 NC/144M Q17 Q7 D15 D6 11 CQ Q8 D8 D7 Q6
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Pin Definitions
Pin Name D[x:0] IO Pin Description InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1541V18 − D[7:0] CY7C1556V18 − D[8:0] CY7C1543V18 − D[17:0] CY7C1545V18 − D[35:0] InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. InputNibble Write Select 0, 1 − Active LOW (CY7C1541V18 Only). Sampled on the rising edge of the K and Synchronous K clocks when write operations are active. Used to select which nibble is written into the device during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device. BWS0, BWS1, BWS2, BWS3 InputByte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when Synchronous write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1556V18 − BWS0 controls D[8:0] CY7C1543V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1545V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1541V18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1556V18, 4M x 18 (4 arrays each of 1M x 18) for CY7C1543V18 and 2M x 36 (4 arrays each of 512K x 36) for CY7C1545V18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1541V18 and CY7C1556V18, 20 address inputs for CY7C1543V18 and 19 address inputs for CY7C1545V18. These inputs are ignored when the appropriate port is deselected. OutputsData Output Signals. These pins drive out the requested data when the read operation is active. Valid Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the read port, Q[x:0] are automatically tri-stated. CY7C1541V18 − Q[7:0] CY7C1556V18 − Q[8:0] CY7C1543V18 − Q[17:0] CY7C1545V18 − Q[35:0] InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. Valid output indicator InputClock InputClock Echo Clock Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0]. Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in the BWS
WPS NWS0, NWS1,
A
Q[x:0]
RPS
QVLD K K CQ
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Pin Definitions
Pin Name ZQ IO Input (continued) Pin Description Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device.The timings in the DLL turned off operation are different from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing. TDO for JTAG. TCK Pin for JTAG. TDI Pin for JTAG. TMS Pin for JTAG. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.
DOFF
Input
TDO TCK TDI TMS NC
Output Input Input Input N/A N/A N/A InputReference
NC/144M NC/288M
VREF VDD VSS VDDQ
Power Supply Power Supply Inputs to the Core of the Device. Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Functional Overview
The CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 are synchronous pipelined burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1541V18, four 9-bit data transfers in the case of CY7C1556V18, four 18-bit data transfers in the case of CY7C1543V18, and four 36-bit data transfers in the case of CY7C1545V18, in two clock cycles. Accesses for both ports are initiated on the positive input clock (K). All synchronous input and output timing are referenced from the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the input clocks (K and K) as well. All synchronous control (RPS, WPS, NWS[x:0], BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1543V18 is described in the following sections. The same basic descriptions apply to CY7C1541V18, CY7C1556V18, and CY7C1545V18.
Read Operations
The CY7C1543V18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to address inputs are stored in the read address register. Following the next two K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]
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Depth Expansion
The CY7C1543V18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the QDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
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The truth table for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follows.[3, 4, 5, 6, 7, 8]
Truth Table
Operation
K
RPS WPS H[9] L
[10]
DQ
DQ
DQ
DQ
L-H Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. Read Cycle: L-H (2.0 cycle Latency) Load address on the rising edge of K; wait two cycles; read data on two consecutive K and K rising edges. NOP: No Operation Standby: Clock Stopped L-H
D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
L[10]
X
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 3) ↑
H
H X
D=X Q = High-Z Previous State
D=X Q = High-Z Previous State
D=X Q = High-Z Previous State
D=X Q = High-Z Previous State
Stopped X
The write cycle description table for CY7C1541V18 and CY7C1543V18 follows. [3, 11]
Write Cycle Descriptions
BWS0/ BWS1/ NWS0 L NWS1 L K L–H K – Comments During the data portion of a write sequence: CY7C1541V18 − both nibbles (D[7:0]) are written into the device, CY7C1543V18 − both bytes (D[17:0]) are written into the device.
L
L
–
L-H During the data portion of a write sequence: CY7C1541V18 − both nibbles (D[7:0]) are written into the device, CY7C1543V18 − both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence: CY7C1541V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1543V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H
L
H
–
L–H During the data portion of a write sequence: CY7C1541V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1543V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence: CY7C1541V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1543V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H
H
L
–
L–H During the data portion of a write sequence: CY7C1541V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1543V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation.
H H
H H
L–H –
Notes 3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 4. Device powers up deselected with the outputs in a tri-state condition. 5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges, also. 8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request. 11. Is based on a write cycle was initiated per the The write cycle description table for CY7C1541V18 and CY7C1543V18 follows. [3, 11] table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the The state diagram for the TAP controller follows.[12] on page 14. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V
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between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update-IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the
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The state diagram for the TAP controller follows.[12]
TAP Controller State Diagram
1
TEST-LOGIC RESET 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
1
1 SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1 EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
1
0
Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP AC Switching Characteristics
Over the Operating Range [16, 17] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [17] Figure 2. TAP Timing and Test Conditions
(a)
tTH
tTL
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IDCODE
001
the vendor ID code andwith Loads the ID register places the register between TDI This operation does SAMPLE Z 0 10
Captures the inpu an t
CY7C1541V18
CY7C1556V18
CY7C1543V18
CY7C1545V18
Instruction Codes
V ocument Number: 001-05389 Rev *F Dalue .
Identification Regi ster Definitions
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Code
RegisterName
RevisionNumber000000000000Versionnumber.
BitSize
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
Document Number: 001-05389 Rev. *F
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Power Up Sequence in QDR-II+ SRAM
QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.
DLL Constraints
■ ■ ■
DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The DLL functions at frequencies down to 120 MHz. If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this,
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) ❐ Apply VDD before VDDQ ❐ Apply VDDQ before VREF or at the same time as VREF Provide stable power and clock (K, K) for 2048 cycles to lock the DLL.
■
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied.. –55°C to +125°C
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ISB1
Automatic Power down Current
Max VDD, 375 MHz Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 333 MHz
x8 x9 x18 x36 x8 x9 x18 x36
525 525 525 410 500 500 500 395 450 450 450 385
mA
mA
300 MHz
x8 x9 x18 x36
mA
AC Electrical Characteristics
Over the Operating Range[14] Parameter VIH Description Input HIGH Voltage Test Conditions V Min Typ Max Unit
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Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 11.82 Ω Ω 2.33 Unit °C/W °C/W
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50Ω RL = 50Ω VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50Ω ALL INPUT PULSES 1.25V 0.75V
[23]
ZQ
(a)
INCLUDING JIG AND SCOPE
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Switching Characteristics
Over the Operating Range [23, 24] CY Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tSA tSC tSCDDR tSD tHA tHC tHCDDR tHD tCO tDOH tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tQVLD tKC Var tKC lock tKC Reset tKHKH tKHKL tKLKH tKHKH tAVKH tIVKH tIVKH tDVKH tKHAX tKHIX tKHIX tKHDX tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ tCHQX1 tCQHQVLD tKC Var tKC lock tKC Reset K Clock Cycle Time Input Clock (K/K) HIGH Input Clock (K/K) LOW K Clock Rise to K Clock Rise (rising edge to rising edge) Address Setup to K Clock Rise Control Setup to K Clock Rise (RPS, WPS) Double Data Rate Control Setup to Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Setup to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise (RPS, WPS) Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise K/K Clock Rise to Data Valid Data Output Hold after Output K/K Clock Rise (Active to Active) K/K Clock Rise to Echo Clock Valid Echo Clock Hold after K/K Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Output Clock (CQ/CQ) HIGH [26] CQ Clock Rise to CQ Clock Rise [26] (rising edge to rising edge) Clock (K/K) Rise to High-Z (Active to High-Z) [27, 28] Clock (K/K) Rise to Low-Z
[27, 28]
Description VDD(Typical) to the First Access [25]
375 MHz 1 2.66 8.40 0.4 0.4 1.13 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – –0.45 – –0.45 –0.2 0.88 0.88 – –0.45 – – – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 –
333 MHz 1 3.0 0.4 0.4 1.28 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – –0.45 – –0.45 –0.2 1.03 1.03 – –0.45 – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 – 8.40
300 MHz 1 3.3 0.4 0.4 1.40 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 – –0.45 – –0.45 –0.2 1.15 1.15 – –0.45 8.40 – – – – – – – – – – – 0.45 – 0.45 – 0.2 – – – 0.45 –
Min Max Min Max Min Max
Unit ms ns tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles
Setup Times
Hold Times
Output Times
Echo Clock High to QVLD Valid [29] Clock Phase Jitter DLL Lock Time (K)
–0.20 0.20 –0.20 0.20 –0.20 0.20 – 2048 0.20 – – 2048 0.20 – – 2048 0.20 –
DLL Timing
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Switching Waveforms
Read/Write/Deselect Sequence [31, 32, 33] t Figure 5. Waveform for 2.0 Cycle Read Latency
NOP 1
K
t KH t KL
READ 2
t CYC
WRITE 3
t KHKH
READ 4
WRITE 5
NOP 6
7
8
K RPS
t SC
tHC
t SC
t HC
WPS A
A0 t SA t HA A1 t HD t SD D10 D11 A2 A3 t SD D12 D13 t HD
D
D30
D31
D32
D33
CQ
CQ
DON’T CARE UNDEFINED
Document Number: 001-05389 Rev. *F
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 375 Ordering Code CY7C1541V18-375BZC CY7C1556V18-375BZC CY7C1543V18-375BZC CY7C1545V18-375BZC CY7C1541V18-375BZXC CY7C1556V18-375BZXC CY7C1543V18-375BZXC CY7C1545V18-375BZXC CY7C1541V18-375BZI CY7C1556V18-375BZI CY7C1543V18-375BZI CY7C1545V18-375BZI CY7C1541V18-375BZXI CY7C1556V18-375BZXI CY7C1543V18-375BZXI CY7C1545V18-375BZXI 333 CY7C1541V18-333BZC CY7C1556V18-333BZC CY7C1543V18-333BZC CY7C1545V18-333BZC CY7C1541V18-333BZXC CY7C1556V18-333BZXC CY7C1543V18-333BZXC CY7C1545V18-333BZXC CY7C1541V18-333BZI CY7C1556V18-333BZI CY7C1543V18-333BZI CY7C1545V18-333BZI CY7C1541V18-333BZXI CY7C1556V18-333BZXI CY7C1543V18-333BZXI CY7C1545V18-333BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free Package Diagram Package Type Operating Range Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1541V18-300BZC CY7C1556V18-300BZC CY7C1543V18-300BZC CY7C1545V18-300BZC CY7C1541V18-300BZXC CY7C1556V18-300BZXC CY7C1543V18-300BZXC CY7C1545V18-300BZXC CY7C1541V18-300BZI CY7C1556V18-300BZI CY7C1543V18-300BZI CY7C1545V18-300BZI CY7C1541V18-300BZXI CY7C1556V18-300BZXI CY7C1543V18-300BZXI CY7C1545V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free Package Diagram Package Type Operating Range Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Document Number: 001-05389 Rev. *F
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Package Diagram
Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195
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Document History Page
Document Title: CY7C1541V18/CY7C1556V18/CY7C1543V18/CY7C1545V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-05389 REV. ** *A ECN NO. 403090 425252 ISSUE DATE See ECN See ECN ORIG. OF CHANGE VEE VEE DESCRIPTION OF CHANGE New Data Sheet Updated the DLL Section Fixed typos in the DC and AC parameter section Updated the switching waveform Updated the Power up sequence Added additional parameters in the AC timing ECN for Show on web Moved the Selection Guide table from page# 3 to page# 1 Modified Application Diagram Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changedeect 72d TTDo
*B *C
437000 461934
See ECN See ECN
IGS NXR
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-05389 Rev. *F
Revised March 06, 2008
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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
