CY7C164

CY7C164 CY7C166 16K x 4 Static RAM Features • High speed — 15 ns • Output enable (OE) feature (CY7C166) • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 110 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected • CY7C164 is available in non Pb-free 22-pin (300-Mil) Molded DIP, CY7C166 in non Pb-free 24-pin Molded SOJ Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. The CY7C166 has an active LOW Output Enable (OE) feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW (and the Output Enable (OE) is LOW for the CY7C166). Data on the four input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A13). Reading the device is accomplished by taking Chip Enable (CE) LOW (and OE LOW for CY7C166), while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. The I/O pins stay in a high-impedance state when Chip Enable (CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166). A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configurations DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 CE GND 1 2 3 4 5 6 7C164 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE A5 A6 A7 A8 A9 A10 A11 A12 A13 CE OE GND SOJ Top View 1 24 2 23 3 22 4 21 5 20 6 7C166 19 18 7 17 8 9 16 10 15 11 14 12 13 VCC A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O3 I/O2 I/O1 I/O0 16K x 4 ARRAY COLUMN DECODER A0 A9 A10 A11 A12 A13 POWER DOWN SENSE AMPS CE WE (OE) (7C166 ONLY) Cypress Semiconductor Corporation Document #: 38-05025 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C164 CY7C166 Selection Guide CY7C164-15 CY7C166-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 15 115 20 CY7C164-25 CY7C166-25 25 105 20 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ............................................ –0.5V to +7.0V DC Input Voltage[1] ......................................... –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range –15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA Max. VCC, CE > VIH, Min. Duty Cycle = 100% Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current[2] Automatic CE Power-Down Current[2] Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC 0.8 +5 +5 115 40 20 2.2 –0.5 –5 –5 Max. Min. 2.4 0.4 VCC 0.8 +5 +5 105 20 20 –25 Max. Unit V V V V µA µA mA mA mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Notes: 1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns. 2. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05025 Rev. *A Page 2 of 9 [+] [+] Feedback CY7C164 CY7C166 AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω C164–5 R1 481Ω ALL INPUT PULSES 3.0V GND 10% 90% 90% 10% < 5 ns C164–6 < 5 ns THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[4] CY7C164-15 CY7C166-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE CYCLE[7] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [5] CY7C164-25 CY7C166-25 Min. 25 Max. Unit ns 25 5 25 12 3 10 5 10 0 20 20 20 20 0 0 15 10 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns Description Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z[5] Z[5, 6] CE HIGH to High 7C166 7C166 7C166 Min. 15 Max. 15 3 15 10 3 8 3 8 0 15 15 12 12 0 0 12 10 0 5 7 CE LOW to Power-Up CE HIGH to Power-Down WE LOW to High Z[5, 6] Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05025 Rev. *A Page 3 of 9 [+] [+] Feedback CY7C164 CY7C166 Switching Waveforms Read Cycle No. 1[8,9] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C164–7 Read Cycle No. 2[8,10] CE tACE OE 7C166 tDOE tLZOE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50% tRC tHZOE tHZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT ICC 50% ISB C164–8 Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CE = VIL. (CY7C166: OE = VIL also). 10. Address valid prior to or coincident with CE transition LOW. Document #: 38-05025 Rev. *A Page 4 of 9 [+] [+] Feedback CY7C164 CY7C166 Switching Waveforms (continued) Write Cycle No. 1(WE Controlled)[7,11] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATAINVALID tHZWE DATA I/O DATA UNDEFINED C164–9 tAW tPWE tHA tHD tLZWE HIGH IMPEDANCE Write Cycle No. 2(CE Controlled)[7,11,12] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATAIN VALID tHD tHA tSCE DATA I/O HIGH IMPEDANCE C164–10 Notes: 11. CY7C166 only: Data I/O will be high-impedance if OE = VIH. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05025 Rev. *A Page 5 of 9 [+] [+] Feedback CY7C164 CY7C166 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 V CC = 5.0V TA = 25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 I SB 5.5 6.0 I CC 1.0 0.8 0.6 0.4 0.2 0.0 –55 I SB 25 NORMALIZED I, I CC NORMALIZED I, I CC I CC V CC = 5.0V V IN = 5.0V 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED t AA 1.3 1.2 1.1 TA = 25°C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA =25°C VCC =5.0V 0.8 0.6 –55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO 2.5 DELTA tAA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC NORMALIZED I CC vs. CYCLE TIME VCC = 5.0V TA = 25°C VIN = 0.5V 1.00 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25°C 0.75 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05025 Rev. *A Page 6 of 9 [+] [+] Feedback CY7C164 CY7C166 CY7C164 Truth Table CE H L L WE X H L High Z Data Out Data In Input/Output Read Write Mode Deselect/Power-Down Active (ICC) Active (ICC) Power Standby (ISB) CY7C166 Truth Table CE H L L L WE X H L H OE X L H H Input/Output High Z Data Out Data In High Z Read Write Select/Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Address Designators Address Name A5 A6 A7 A8 A9 A10 A11 A12 A13 A0 A1 A2 A3 A4 Address Function X3 X4 X5 X6 X7 Y5 Y4 Y0 Y1 Y2 Y3 X0 X1 X2 CY 7C164 Pin CY7C166 Pin Number Number 1 2 3 4 5 6 7 8 9 17 18 19 20 21 1 2 3 4 5 6 7 8 9 19 20 21 22 23 Ordering Information Speed (ns) 15 25 Ordering Code CY7C164-15PC CY7C166-15VC CY7C164-25PC CY7C166-25VC Package Diagram 51-85012 51-85030 51-85012 51-85030 Package Type 22-pin (300-Mil) Molded DIP 24-pin (300-Mil) Molded SOJ 22-pin (300-Mil) Molded DIP 24-pin (300-Mil) Molded SOJ Commercial Operating Range Commercial Document #: 38-05025 Rev. *A Page 7 of 9 [+] [+] Feedback CY7C164 CY7C166 Package Diagrams 22-pin (300-Mil) PDIP (51-85012) 11 1 DIMENSIONS IN INCHES MIN. MAX. 0.250 0.270 12 22 0.030 0.065 1.070 1.120 0.140 0.190 0.115 0.160 0.090 0.110 0.055 0.065 0.015 0.020 0.120 0.140 SEATING PLANE 0.280 0.325 0.015 0.060 0.009 0.012 0.310 0.385 3° MIN. 51-85012-*A 24-pin (300-mil) SOJ (51-85030) PIN 1 ID 12 1 DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] MIN. MAX. PACKAGE WEIGHT 0.75gms PART # 13 24 V24.3 VZ24.3 STANDARD PKG. LEAD FREE PKG. 0.597[15.16] 0.613[15.57] SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48] 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B Document #: 38-05025 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress [+] [+] Feedback CY7C164 CY7C166 Document History Page Document Title: CY7C164/CY7C166 16K x 4 Static RAM Document Number: 38-05025 REV. ** *A ECN NO. 106811 486744 Issue Date 09/10/01 See ECN Orig. of Change SZV NXR Description of Change Change from Spec number: 38-00032 to 38-05025 Removed 20 ns and 35 ns speed bin from Product offering Removed 24-pin (300-Mil) Molded DIP package Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table Document #: 38-05025 Rev. *A Page 9 of 9 [+] [+] Feedback