CY7C185D-12VXI

PRELIMINARY CY7C185D 64K (8K x 8) Static RAM Features • Pin- and function-compatible with CY7C185 • High speed — tAA = 10 ns • Low active power — ICC = 60 mA @ 10 ns • Low CMOS standby power — ISB2 = 3 mA • CMOS for optimum speed/power • Data Retention at 2.0V • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • Available in Lead (Pb)-Free Packages Functional Description[1] The CY7C185D is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.The CY7C185D is in a standard 28-pin 300-mil-wide DIP, SOJ, or SOIC Pb-Free package. Logic Block Diagram Pin Configurations DIP/SOJ/SOIC Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 INPUT BUFFER I/O1 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 I/O6 256 x 32 x 8 ARRAY CE1 CE2 WE OE COLUMN DECODER POWER DOWN I/O7 A10 A11 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A12 A0 A9 Cypress Semiconductor Corporation Document #: 38-05466 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 10, 2005 PRELIMINARY Selection Guide CY7C185D-10 Maximum Access Time Maximum Operating Current Maximum Standby Current 10 60 3 CY7C185D-12 12 50 3 CY7C185D CY7C185D-15 15 40 3 Unit ns mA mA Document #: 38-05466 Rev. *C Page 2 of 10 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[2] ....................................... −0.5V to VCC + 0.5V CY7C185D DC Input Voltage[2].................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C185D-10 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND Current[3] Input Load Current Output Leakage Current Output Short Circuit Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.5 –1 –1 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 –300 60 10 3.0 2.0 –0.5 –1 –1 Max. 7C185D-12 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 –300 50 10 3.0 Max. Unit V V V V µA µA mA mA mA mA VCC Operating Supply Current VCC = Max., IOUT = 0 mA Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle = 100% Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., VOUT = GND Current[3] Input Load Current Output Leakage Current Output Short Circuit Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 7C185D-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Min. 2.4 0.4 2.0 –0.5 –1 –1 VCC + 0.3V 0.8 +1 +1 –300 40 10 3.0 Max. Unit V V V V µA µA mA mA mA mA VCC Operating Supply Current VCC = Max., IOUT = 0 mA Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle = 100% Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V or CE2 ≤ 0.3V VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05466 Rev. *C Page 3 of 10 PRELIMINARY Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board CY7C185D All-Packages TBD TBD Unit °C/W °C/W AC Test Loads and Waveforms 10-ns Device OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Z = 50Ω ALL INPUT PULSES 3.0V 10% 90% 90% 10% ≤ 3 ns High-Z characteristics: 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R1 481 Ω 30 pF* GND (a) Equivalent to: THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V ≤ 3 ns 12, 15-ns Devices R1 481 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω R2 255Ω (b) (c) Switching Characteristics Over the Operating Range [6] 7C185D-10 Parameter Read Cycle tpower[5] tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7] CE1 LOW to Low Z[8] 3 3 5 0 10 0 12 CE2 HIGH to Low Z CE1 HIGH to High Z[7, 8] CE2 LOW to High Z CE1 LOW to Power-Up CE2 to HIGH to Power-Up CE1 HIGH to Power-Down CE2 LOW to Power-Down 3 5 3 3 6 0 15 3 10 10 5 3 6 3 3 7 100 10 10 3 12 12 6 3 7 100 12 12 3 15 15 8 100 15 15 µs ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C185D-12 Min. Max. 7C185D-15 Min. Max. Unit Notes: 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device. Document #: 38-05466 Rev. *C Page 4 of 10 PRELIMINARY Switching Characteristics Over the Operating Range (continued)[6] 7C185D-10 Parameter Write Cycle tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [9] CY7C185D 7C185D-12 Min. 12 10 10 10 0 0 10 7 0 Max. 7C185D-15 Min. 15 12 12 12 0 0 12 8 0 6 3 3 7 Max. Unit ns ns ns ns ns ns ns ns ns ns ns Description Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[7] WE HIGH to Low Z Min. 10 8 8 7 0 0 7 6 0 Max. 6 3 Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR tR[10] [4] Description VCC for Data Retention Data Retention Current Non-L, Com’l / Ind’l L-Version Only Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 Max. 3 1.2 Unit V mA mA ns ns 0 tRC Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR Switching Waveforms Read Cycle No.1[11,12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 11. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 12. WE is HIGH for read cycle. Document #: 38-05466 Rev. *C Page 5 of 10 PRELIMINARY Switching Waveforms (continued) Read Cycle No.2[13,14] CE1 tRC CY7C185D CE2 OE OE tACE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE tHZOE tHZCE DATA VALID tPD ICC HIGH IMPEDANCE VCC SUPPLY CURRENT tPU 50% 50% ISB Write Cycle No. 1 (WE Controlled)[12,14] tWC ADDRESS CE1 tAW CE2 CE WE tSA tSCE2 tPWE tSCEI tHA OE tSD DATA I/O tHD NOTE 15 tHZOE DATA IN VALID Write Cycle No. 2 (CE Controlled)[14,15,16] tWC ADDRESS CE1 tSA CE2 tAW WE tSD DATA I/O DATA IN VALID tHD tSCE2 tHA tSCE1 Notes: 13. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL. 14. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 15. During this period, the I/Os are in the output state and input signals should not be applied. 16. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05466 Rev. *C Page 6 of 10 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[14,15,16,17] tWC ADDRESS CE1 CE2 tSCE1 tSCE2 tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA IN VALID tLZWE tHD tHA CY7C185D Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H High Z High Z Data Out Data In High Z Input/Output Mode Deselect/Power-down Deselect/Power-down Read Write Deselect Ordering Information Speed (ns) 10 Ordering Code CY7C185D-10PXC CY7C185D-10SXC CY7C185D-10VXC CY7C185D-10VXI 12 CY7C185D-12PXC CY7C185D-12SXC CY7C185D-12VXC CY7C185D-12VXI 15 CY7C185D-15PXC CY7C185D-15SXC CY7C185D-15VXC CY7C185D-15VXI Package Name P21 S21 V21 V21 P21 S21 V21 V21 P21 S21 V21 V21 Package Type 28-Lead (300-Mil) Molded DIP (Pb-Free) 28-Lead Molded SOIC (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead (300-Mil) Molded DIP (Pb-Free) 28-Lead Molded SOIC (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead (300-Mil) Molded DIP (Pb-Free) 28-Lead Molded SOIC (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Molded SOJ (Pb-Free) Industrial Industrial Commercial Industrial Commercial Operating Range Commercial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Note: 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05466 Rev. *C Page 7 of 10 PRELIMINARY Package Diagrams 28-Lead (300-Mil) PDIP P21 SEE LEAD END OPTION CY7C185D 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. 0.260[6.60] 0.295[7.49] REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 3° MIN. 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D 28-Lead (300-Mil) Molded SOIC S21 PIN 1 ID 14 1 DIMENSIONS IN INCHES[MM] 0.394[10.01] 0.291[7.39] 0.300[7.62] 0.419[10.64] * MIN. MAX. REFERENCE JEDEC MO-119 PACKAGE WEIGHT 0.85gms 15 28 0.026[0.66] 0.032[0.81] PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.697[17.70] 0.713[18.11] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] TYP. 0.013[0.33] 0.019[0.48] 0.004[0.10] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] 51-85026-*C * Document #: 38-05466 Rev. *C Page 8 of 10 PRELIMINARY Package Diagrams (continued) 28-Lead (300-Mil) Molded SOJ V21 CY7C185D 51-85031-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05466 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C185D 64K (8K x 8) Static RAM (Preliminary) Document Number: 38-05466 REV. ** *A *B ECN NO. 201560 233715 262950 Orig. of Issue Date Change See ECN See ECN See ECN SWI RKF RKF Description of Change Advance Datasheet for C9 IPP CY7C185D DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in Ordering Information Added Tpower Spec in Switching Characteristics table Added Data Retention Characteristics table and waveforms Shaded Ordering Information 1) Reduced Speed bins to -10, -12 and -15 ns 2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6 *C 307593 See ECN RKF Document #: 38-05466 Rev. *C Page 10 of 10