CY7C187-35VC

87 CY7C187 64K x 1 Static RAM Features vided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. • High speed — 15 ns • CMOS for optimum speed/power • Low active power — 495 mW • Low standby power — 220 mW • TTL compatible inputs and outputs • Automatic power-down when deselected Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output (DOUT) pin. The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. Functional Description The CY7C187 utilizes a die coat to insure alpha immunity. The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is pro- Logic Block Diagram Pin Configurations SOJ Top View DI A0 A1 A2 A3 A4 A5 NC A6 A7 SENSE AMPS A12 A13 A14 A15 A0 A1 A2 A3 ROW DECODER INPUT BUFFER 256 x 256 ARRAY DO DOUT WE GND 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 DIP Top View VCC A15 A14 A13 A12 NC A11 A10 A9 A8 DIN CE A0 A1 A2 A3 A4 A5 A6 A7 DOUT WE GND C187–3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 DIN CE C187–2 CE COLUMN DECODER POWER DOWN A4 A5 A6 A7 A8 A9 A10 A11 WE C187–1 Selection Guide[1] 7C187-15 7C187-20 7C187-25 7C187-35 Maximum Access Time (ns) 15 20 25 35 Maximum Operating Current (mA) 90 80 70 70 40/20 40/20 20/20 20/20 Maximum Standby Current (mA) Note: 1. For military specifications, see the CY7C187A datasheet. Cypress Semiconductor Corporation Document #: 38-05044 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C187 DC Input Voltage[2] .........................................–0.5V to +7.0V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 22 to Pin 11) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ............................................ –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL–STD–883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range 7C187-15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL =12.0 mA VIH Input HIGH Voltage Min. Max. 2.4 7C187-20 Min. Max. 2.4 0.4 [2] 7C187-25, 35 Min. Max. Unit 2.4 0.4 V 0.4 V V 2.2 VCC 2.2 VCC 2.2 VCC VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 V IIX Input Load Current GND < VI < VCC –5 +5 –5 +5 –5 +5 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –5 +5 –5 +5 –5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –350 –350 –350 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 90 80 70 mA ISB1 Automatic CE PowerDown Current[4] Max. VCC, CE ≥ VIH 40 40 20 mA ISB2 Automatic CE Power-Down Current Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V 20 20 20 mA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes: 2. VIL (min.) = –3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05044 Rev. ** Page 2 of 9 CY7C187 AC Test Loads and Waveforms R1 329 Ω (480 Ω MIL) 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: (a) R1 329 Ω (480 Ω MIL) 5V OUTPUT ALL INPUT PULSES R2 202 Ω 5 pF (R1 255 Ω MIL) INCLUDING JIG AND SCOPE 3.0V R2 202 Ω (R1 255 Ω MIL) GND 90% 10% 90% 10% ≤ 5 ns ≤ 5 ns (b) C187–4 C187–5 THÉ VENIN EQUIVALENT OUTPUT 125Ω 167Ω 1.73V OUTPUT 1.90V Military Commercial Switching Characteristics Over the Operating Range[6] 7C187-15 Parameter Description Min. Max. 7C187-20 Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low Z[7] 15 3 CE HIGH to High Z tPU CE LOW to Power Up tPD CE HIGH to Power Down ns 20 5 15 3 [7, 8] tHZCE 20 ns 20 5 8 0 ns ns 8 0 15 ns ns ns 20 ns WRITE CYCLE[9] tWC Write Cycle Time 15 20 ns tSCE CE LOW to Write End 12 15 ns tAW Address Set-Up to Write End 12 15 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 12 15 ns tSD Data Set-Up to Write End 10 10 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z 5 5 ns tHZWE WE LOW to High Z [8] 7 7 ns Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05044 Rev. ** Page 3 of 9 CY7C187 Switching Characteristics Over the Operating Range[6] (continued) 7C187-25 Parameters Description Min. Max. 7C187-35 Min. Max. Units READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low Z 25 25 5 CE HIGH to High Z tPU CE LOW to Power Up tPD CE HIGH to Power Down 5 5 [7, 8] ns 35 25 [7] tHZCE 35 ns 35 5 10 0 ns ns 15 0 20 ns ns ns 20 ns [9] WRITE CYCLE tWC Write Cycle Time 20 25 ns tSCE CE LOW to Write End 20 25 ns tAW Address Set-Up to Write End 20 25 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 15 20 ns tSD Data Set-Up to Write End 10 15 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low 5 5 ns tHZWE WE LOW to High Z [8] 7 10 ns Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C187–6 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. Document #: 38-05044 Rev. ** Page 4 of 9 CY7C187 Switching Waveforms Read Cycle No. 2[10, 12] tRC CE tACE tHZCE tLZCE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tPD tPU ICC 50% 50% ISB C187–7 Write Cycle No. 1 (WE Controlled)[11] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED C187–8 Write Cycle No. 2 (CE Controlled) [11, 13] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tSD DATA IN tHD DATA VALID DATA OUT HIGH IMPEDANCE C187–9 Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05044 Rev. ** Page 5 of 9 CY7C187 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED I CC, I SB 1.2 I CC 0.8 0.6 0.4 0.0 4.0 4.5 5.0 0.8 0.6 0.4 VCC =5.0V VIN =5.0V 0.2 ISB 0.2 I CC 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 1.3 NORMALIZED t AA NORMALIZED t AA 1.4 1.2 1.1 TA =25°C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 –55 6.0 25 AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING NORMALIZED t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 2.0 3.0 4.0 SUPPLY VOLTAGE(V) Document #: 38-05044 Rev. ** 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 5.0 2.0 3.0 4.0 140 120 100 VCC =5.0V TA =25°C 80 60 40 20 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED I CC vs.CYCLE TIME 1.25 25.0 20.0 15.0 10.0 0.0 1.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 0 0.0 30.0 VCC =4.5V TA =25°C 5.0 1.0 120 OUTPUT VOLTAGE (V) 125 SUPPLY VOLTAGE (V) 3.0 PO 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE(V) NORMALIZED I 25 OUTPUT SINK CURRENT (mA) 1.0 1.0 0 200 400 600 800 1000 CAPACITANCE (pF) NORMALIZED I CC NORMALIZED ICC, ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC =5.0V TA =25°C VCC =0.5V 1.00 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 9 CY7C187 Address Designators Truth Table Address Name Address Function Pin Number A0 X3 1 A1 X4 2 A2 X5 3 A3 X6 4 A4 X7 5 A5 Y7 6 A6 Y6 7 A7 Y2 8 A8 Y3 14 A9 Y1 15 A10 Y0 16 A11 Y4 17 A12 Y5 18 A13 X0 19 A14 X1 20 A15 X2 21 CE WE Input/Output Mode H X High Z Deselect/Power-Down L H Data Out Read L L Data In Write Ordering Information[14] Speed (ns) 15 20 25 35 Ordering Code Package Name Package Type CY7C187-15PC P9 22-Lead (300-Mil) Molded DIP CY7C187-15VC V13 24-Lead Molded SOJ CY7C187-20PC P9 22-Lead (300-Mil) Molded DIP CY7C187-20VC V13 24-Lead Molded SOJ CY7C187-25PC P9 22-Lead (300-Mil) Molded DIP CY7C187-25VC V13 24-Lead Molded SOJ CY7C187-35PC P9 22-Lead (300-Mil) Molded DIP CY7C187-35VC V13 24-Lead Molded SOJ Operating Range Commercial Commercial Commercial Commercial Note: 14. For military variations, see the CY7C187A datasheet. Document #: 38-05044 Rev. ** Page 7 of 9 CY7C187 Package Diagrams 22-Lead (300-Mil) Molded DIP P9 51-85012-A 24-Lead (300-Mil) Molded SOJ V13 51-85030-A Document #: 38-05044 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C187 Document Title: CY7C187 64K x 1 Static RAM Document Number: 38-05044 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107146 09/10/01 SZV Change from Spec number: 38-00038 to 38-05044 Document #: 38-05044 Rev. ** Page 9 of 9