CY7C192_08

CY7C192 64K x 4 Static RAM with Separate IO Features ■ Functional Description The CY7C192 is a high performance CMOS static RAM organized as 65,536 x 4 bits with separate IO. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power down feature that reduces power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and write enable (WE) inputs are both LOW. Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW while the Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins appears on the four data output pins. The output pins stay in high impedance state when Write Enable (WE) is LOW or Chip Enable (CE) is HIGH. A die coat ensures alpha immunity. High speed ❐ 15 ns CMOS for optimum speed/power Low active power ❐ 860 mW Low standby power ❐ 55 mW TTL-compatible inputs and outputs Automatic power down when deselected Available in Pb-free and non Pb-free 28-Pin Molded SOJ package ■ ■ ■ ■ ■ ■ Logic Block Diagram I0 I1 I2 I3 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER O0 SENSE AMPS 64K x 4 ARRAY O1 O2 O3 COLUMN DECODER POWER DOWN A10 A11 A12 A13 A14 A15 CE WE Cypress Semiconductor Corporation Document #: 38-05047 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 15, 2008 [+] Feedback CY7C192 Pin Configuration Figure 1. 28-Pin Molded SOJ Package Top View A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I0 I1 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 I3 I2 O3 O2 O1 O0 WE Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -15 15 145 10 Unit ns mA mA Document #: 38-05047 Rev. *D Page 2 of 9 [+] Feedback CY7C192 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ........................................ −0.5V to VCC + 0.5V DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................. >900V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f = 0 Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current—TTL Inputs Automatic CE Power Down Current—CMOS Inputs Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.2 −0.5 −5 −5 -15 Min 2.4 0.4 VCC + 0.3V 0.8 +5 +5 145 30 10 Max Unit V V V V μA μA mA mA mA Capacitance Parameter CIN [3] Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 8 10 Unit pF pF COUT [3] Notes 1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05047 Rev. *D Page 3 of 9 [+] Feedback CY7C192 Figure 2. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω R1 481Ω ALL INPUT PULSES 3.0V GND 10% 90% 90% 10% < 3 ns < 3 ns (a) (b) Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[4] -15 Parameter Read Cycle tRC tAA tOHA tACE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[7] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [5] [5, 6] Description Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[5] Z[5,6] Min 15 Max Unit ns 15 3 15 3 7 0 15 15 10 10 0 0 9 9 0 3 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE HIGH to High CE LOW to Power Up CE HIGH to Power Down Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZW\E is less than tLZWE for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05047 Rev. *D Page 4 of 9 [+] Feedback CY7C192 Switching Waveforms Figure 3. Read Cycle No. 1[8, 9] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2[8, 10] tRC CE tACE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT ICC 50% ISB Figure 5. Write Cycle No. 1 (WE Controlled)[7] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA Notes 8.WE is HIGH for read cycle. 9.Device is continuously selected, CE = VIL. 10.Address valid prior to or coincident with CE transition LOW. Document #: 38-05047 Rev. *D Page 5 of 9 [+] Feedback CY7C192 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE Controlled)[7, 11] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN tHZWE DATA OUT HIGH IMPEDANCE DATA VALID tHD tHA tSCE Note 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. Document #: 38-05047 Rev. *D Page 6 of 9 [+] Feedback CY7C192 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C ICC ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 AMBIENT TEMPERATURE(°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 VCC =5.0V VIN =5.0V NORMALIZED ICC NORMALIZED ICC SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 -55 25 125 SUPPLY VOLTAGE (V) TYPICAL POWER ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25°C 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05047 Rev. *D Page 7 of 9 [+] Feedback CY7C192 Ordering Information Speed (ns) 15 Ordering Code CY7C192-15VC CY7C192-15VXC Package Diagram 51-85031 Package Type 28-Pin Molded SOJ 28-Pin Molded SOJ (Pb-free) Operating Range Commercial Package Diagram Figure 7. 28-Pin (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 38-05047 Rev. *D Page 8 of 9 [+] Feedback CY7C192 Document History Page Document Title: CY7C192 64K x 4 Static RAM with Separate IO Document Number: 38-05047 REV. ** *A ECN NO. Issue Date 107149 359716 09/10/01 See ECN Orig. of Change SZV AJU Description of Change Change Spec number from: 38-00076 to 38-05047 Changed Static Discharge Voltage limit in the Maximum Ratings section (page 2) from 2001V to 900V Removed references to CY7C191 Added Pb-free parts to the Ordering Information table and replaced the Package Name column with Package Diagram Removed 20 ns and 25 ns speed bins Changed the Low active power from 220 mW to 55 mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Removed 28-Lead (300-Mil) PDIP package from product offering Updated Ordering Information table *B *C 419549 492500 See ECN See ECN AJU NXR *D 2104606 See ECN VKN/AESA Removed 12 ns speed bin © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. 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Document #: 38-05047 Rev. *D Revised February 15, 2008 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback